JPH07135265A - Manufacture of nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the deterioration of the insulating property of a nonvolatile semiconductor memory by forming an HTO film on the surface of a semiconductor substrate including floating gates and side-wall spacers on the side walls of the floating gates, and then, a control gate on the surface of the substrate including the floating gates and side-wall spacers. CONSTITUTION:After forming floating gates 5 on a semiconductor substrate 1 having LOCOS oxide films 2 and gate oxide films 4 by patterning a polysilicon, oxide film, and nitride film, an HTO film 9 is formed on the surface of the substrate 1 including the gates 5. Then side-wall spacers 9a are formed on the side walls of the gates 5 by etching back the film 9. After forming the spacers 9a, a control gate 10 is formed on the surface of the substrate 1 including the gates 5 and spacers 9a. Therefore, a sufficiently large thickness can be secured for an interlayer insulating film between the gates 5 and gate 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile semiconductor memory, and more particularly to a method for manufacturing a non-volatile semiconductor memory having a two-layer polysilicon gate structure which can be electrically written and erased.

[0002]

2. Description of the Related Art Conventionally, various methods for manufacturing a non-volatile semiconductor memory have been proposed in order to ameliorate a decrease in reliability of a semiconductor device caused by insulation deterioration caused by a manufacturing process. Has been done. For example, a method of manufacturing a non-volatile semiconductor memory having a two-layer polysilicon gate structure in which a control gate is provided on the floating gate so as to cover the floating gate will be described with reference to the drawings.

First, as shown in FIG. 9A, an active region is defined by forming a locos oxide film 52 on a silicon substrate 51, and then a film thickness of about 90 to 110Å is formed on the entire surface of the silicon substrate 51. Forming a gate oxide film 53. Then, by the CVD method, the film thickness is 750 to 1500 Å
Forming a polysilicon layer, and adding N ^{+ to} this polysilicon
Impurity diffusion is performed. Then, a SiO ₂ film 54 having a film thickness of about 100 to 150 Å is formed on the N ⁺ polysilicon by thermal oxidation.
Then, a SiN film 55 having a film thickness of about 150 to 250 Å is further formed on the SiO ₂ film 54 by the CVD method. Then, the polysilicon is patterned by photoetching using the resist 56 as a mask, and the floating gate (FG) 57 is formed so as to cover the active region.

Next, as shown in FIG. 9B, the FG
By HCl oxidizing the sidewall of 57 at 950 ° C.,
Form a sidewall spacer 58 on the sidewall of the FG 57.
At the same time, a film is formed on the entire surface of the silicon substrate 51 including the FG 57.
SiO about 500-800Å₂To form the membrane 59.
By, SiO on FG57₂/ SiN / SiO ₂
An interlayer insulating film made of an (ONO) film is formed.

After that, as shown in FIG.
57 and a film thickness of 750 to 150 on the entire surface of the silicon substrate 51 including the sidewall spacers 58 by the CVD method.
Polysilicon of about 0 Å is formed, and N ⁺ impurity is diffused into this polysilicon. Then, this polysilicon, O
By continuously etching the interlayer insulating film made of NO and FG57 by a photolithography process, F
G57 is separated and control gate (C
G) Form 60.

In the nonvolatile memory thus formed, it is necessary to increase the film thickness of the side wall spacer 58 on the side wall of the FG 57 in order to surely retain the charge stored in the FG 57. However, when the side wall of the FG 57 is oxidized to increase the film thickness of the side wall spacer 58, the FG 57 jumps up, an overhang X (in FIG. 9B) is formed at the end of the FG 57, and the oxidized shape deteriorates. Therefore, in the later step of patterning the polysilicon for forming CG60, isotropic etching must be performed for the purpose of surely removing the polysilicon deposited on the overhang X portion of the FG 57. When the anisotropic etching is performed, there is a problem that the pattern width of the CG 60 causes variations in the line width of the CG 60 and the memory cell characteristics become unstable. Furthermore, FG5
Also in the etching of the FG 57 performed for separating 7, as shown in FIG. 10, a part of the sidewall spacer 58 of the FG 57 serves as a mask and the polysilicon 60a forming the CG 60 is not etched. There is a problem that they remain and cause a short circuit between the CG 60 and the adjacent CG.

Further, as shown in FIG. 11 (e), in order to secure the breakdown voltage between the gate electrode 63 and the select gate (SG) 69, a nonvolatile insulating film having a desired thickness is formed. Shows a method of manufacturing a non-volatile memory. First, as shown in FIG. 11A, a gate oxide film 62 is formed on the entire surface of a silicon substrate 61, and then a polysilicon and HTO film (Hig
An insulating film of h Temperature CVD Silicon Dioxide Film) 64 is formed. These polysilicon and HTO film 6
4 is patterned by a photolithography process using the resist 65 as a mask to form a gate electrode 63.

Next, as shown in FIG. 11 (b), after forming an HTO film 66 of about 250 Å on the silicon substrate 61 as a stopper for SiN etching in a later step,
The SiN film 65 is formed on the HTO film 66 and the gate electrode 63.
To form about 400Å. Then, as shown in FIG. 11C, the SiN film 65 is etched back by anisotropic etching, so that only the sidewall portion of the gate electrode 63 is S-doped.
A sidewall spacer 65a is formed by iN.

Next, as shown in FIG. 11D, in order to form the source / drain regions, arsenic is ion-implanted into a desired region using the resist 67 and the gate electrode 63 as a mask. After that, as shown in FIG.
The HTO film 66 is removed by 1% HF, and the gate electrode 63 is removed.
HCl at 950 ° C. over the entire surface of the silicon substrate 61 including
Selective oxide film 6 of about 120-200Å by oxidation
A sidewall oxide film 68a having a thickness of 8 and 20 to 30 Å is formed. Then, polysilicon is formed on the entire surface of the silicon substrate 61 including the gate electrode 63, and patterned into a desired shape to form SG69.

In the nonvolatile memory thus formed, the HTO film 66 formed on the silicon substrate 61.
Is removed by 1% HF, the HTO film 66 under the sidewall spacer 65a made of SiN is also removed, and an undercut portion is generated. Then, even if the select gate oxide film 68 is formed thereafter, the undercut portion Y is not embedded as shown in FIG. Therefore, when the polysilicon 69 is deposited thereon to form the SG 69, the select gate oxide film 68 between the FG and the SG under the SiN sidewall spacer 65a becomes thin, so that the polysilicon is deposited in the undercut portion Y. Go in,
There was a problem that a breakdown voltage would occur.

Further, as shown in FIG. 13D, a method of manufacturing a non-volatile memory in which an ONO film is formed between the gate electrode 73 and SG79 and between the silicon substrate 71 and SG79 will be described. As shown in FIG. 13A, polysilicon is deposited on the silicon substrate 71 on which the gate oxide film 72 is formed, and the gate electrode 73 is formed by patterning using the resist 74 as a mask.

Then, as shown in FIG. 13B, a CVD-type film is formed on the entire surface of the silicon substrate 71 including the gate electrode 73.
An HTO film 75 is formed as a SiO ₂ film. Further, as shown in FIG. 13C, arsenic is ion-implanted into a desired region using the resist 76 and the gate electrode 73 as a mask to form the source / drain regions.

Thereafter, as shown in FIG. 13 (d), a SiN film 77 is formed on the entire surface of the silicon substrate 71 including the gate electrode 73, and is further oxidized by HCl at 950 ° C. to form Si.
The O ₂ film 78 is formed on the order of 20 to 30 Å. Then, polysilicon is deposited on the silicon substrate 71 containing these,
SG79 is formed by patterning into a desired shape. In the nonvolatile memory thus formed, the interlayer insulating film between the gate electrode 73 and the SG 79 and the select gate oxide films 75, 77 and 78 are formed at the same time. In order to suppress the channel effect and reduce the select gate length, it is necessary to set the effective film thickness of the select gate oxide films 75, 77, 78 (B in FIG. 13D) to 120 to 200Å. On the other hand, in order to secure the breakdown voltage between the gate electrode 73 and SG79, the ONO film on the side wall of the gate electrode 73 (A in FIG. 13D) needs to have an effective film thickness of about 600 Å. However, since the interlayer insulating film between the gate electrode 73 and SG79 and the select gate oxide films 75, 77, 78 are formed in the same process, the select gate oxide film is thinned and the gate electrode 73 is formed.
However, there is a problem that it is not possible to simultaneously secure the breakdown voltage of the interlayer insulating film between the SG and SG79.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method for manufacturing a non-volatile semiconductor memory, which can improve deterioration of reliability of a semiconductor device due to deterioration of insulation caused by a manufacturing process. Has an aim.

[0015]

According to the method for manufacturing a nonvolatile semiconductor memory of the present invention, (i) a polysilicon film, an oxide film and a nitride film are formed on a semiconductor substrate having a locos oxide film and a gate oxide film. After that, the polysilicon, oxide film and nitride film are patterned to form a floating gate, and (ii) (a) an HTO film is formed on the semiconductor substrate including the floating gate and etched back, HT on the sidewall of the floating gate
A side wall spacer is formed of an O film, or (b) after oxidizing the floating gate sidewall, an HTO film is formed on the semiconductor substrate including the floating gate and etched back to form a floating gate sidewall on the floating gate sidewall. A method for manufacturing a nonvolatile semiconductor memory is provided, in which a sidewall spacer is formed of an HTO film, and (iii) a control gate is formed on the semiconductor substrate including the floating gate and the sidewall spacer.

Further, (i) after forming a polysilicon and an oxide film on a semiconductor substrate having a gate oxide film, patterning the polysilicon and the oxide film to form a gate electrode, and (ii) the gate By forming an HTO film on a semiconductor substrate including electrodes and etching back,
After forming a side wall spacer of HTO film on the side wall of the gate electrode and performing desired ion implantation, (iii)
The gate oxide film and the HTO film on the semiconductor substrate are removed, and a selective gate oxide film is formed by thermal oxidation.
v) A method for manufacturing a nonvolatile semiconductor memory is provided, in which a nitride film, an oxide film and a control gate are formed on the semiconductor substrate including the gate electrode and the sidewall spacer.

The semiconductor substrate in the present invention is not particularly limited, but a silicon substrate is preferable. The locos film can be formed by a known method. Further, as the gate oxide film, a SiO ₂ film having a thickness of 90 to 12 is formed by a known method such as thermal oxidation or CVD method.
It can be formed with a degree of 0Å. Polysilicon is preferably used for the floating gate or the gate electrode, and a film thickness of 750 to 1500 is formed by a CVD method or the like.
Å can be formed.

In the case of forming the side wall spacer of only the oxide film on the side wall of the floating gate, first,
It is preferable that an oxide film of about 100 to 150 Å is formed on the floating gate by thermal oxidation in the temperature range of 900 to 1000 ° C., and then a nitride film of about 150 to 250 Å is formed by the CVD method or the like. Then, after that, an HTO film is formed on the entire surface of the floating gate and the substrate and a sidewall spacer is formed by etching this HTO film, or the sidewall of the floating gate is oxidized with HCl at a temperature of 900 to 1000 ° C. It is preferable to form the sidewall spacer by using the HTO film and then form the sidewall spacer by using the HTO film. Thus, it is preferable to form the sidewall spacers on the sidewalls of the floating gate and to form the interlayer insulating film of the ONO film on the upper surface. In this case, the effective film thickness of the ONO film is SiO 2.
_It is preferably about 600 to 800 Å in terms of ₂ . The HTO film can be formed by the CVD method at a temperature of about 700 to 800 ° C. In the case of forming the sidewall spacers using only the HTO film, the film thickness is 1500 to 2500.
Å is preferable. When oxidizing the side wall of the floating gate, it is preferable to form an oxide film having a film thickness of about 100 to 200Å and then stack an HTO film having a film thickness of about 1500 to 2500Å to form a sidewall spacer. The sidewall spacer can be formed by a known method, for example, anisotropic etching. Further, when the control gate is formed on the floating gate, a material normally used as an electrode, for example, polysilicon, tungsten silicide, polycide with tungsten silicide, or the like can be used. The forming method at this time is a known method,
For example, by a CVD method or the like, a film thickness of 1500 to 2000 Å
It is preferable to form it in a degree.

In the non-volatile semiconductor memory of the present invention, when the sidewall spacer of the ONO film is formed on the sidewall of the gate electrode, the sidewall spacer is first formed of the HTO film on the sidewall of the gate electrode, and then selected. The oxide film in the region where the gate oxide film is formed is removed, and an oxide film with a film thickness of about 90 to 150Å is formed by thermal oxidation in the region where the new select gate oxide film is formed. After that, a nitride film is formed on the entire surface of the semiconductor substrate including the gate electrode having the sidewall spacer. At this time, the nitride film is preferably formed by a known method such as a CVD method to have a film thickness of about 100 to 300 Å. Then, an oxide film is further formed on the nitride film. The oxide film at this time has a film thickness of 20 to 3 by thermal oxidation or a CVD method.
It is preferable to form 0Å. That is, the effective film thickness of the interlayer insulating film on the side wall of the gate electrode is 470 to 8 in terms of SiO _2.
The oxide film in the portion formed as the select gate oxide film is formed to a thickness of about 80 Å, and the effective film thickness is 150 to 30 in terms of SiO _2.
It is formed with 0Å. Then, after that, a select gate is formed on the interlayer insulating film and the select gate oxide film. The method and the like in this case can be the same as in the case of forming the control gate.

Although the present invention describes a non-volatile semiconductor memory having a two-layer gate structure, the present invention can be similarly applied to a non-volatile semiconductor memory having a gate structure having three or more layers. .

[0021]

According to the method of manufacturing a non-volatile semiconductor memory of the present invention, after forming a polysilicon film, an oxide film and a nitride film on a semiconductor substrate having a locos oxide film and a gate oxide film, the polysilicon film and the oxide film are formed. And the nitride film is patterned to form a floating gate, and (ii)
(A) An HTO film is formed on the semiconductor substrate including the floating gate and etched back to form a sidewall spacer of the HTO film on the floating gate sidewall, or (b) the floating gate sidewall is oxidized. After that, an HTO film is formed on the semiconductor substrate including the floating gate and etched back to form HT on the sidewall of the floating gate.
A side wall spacer made of an O film is formed, and (iii)
Since the control gate is formed on the semiconductor substrate including the floating gate and the sidewall spacer, a sufficient thickness of the interlayer insulating film between the floating gate and the control gate is ensured, and the interlayer insulation between the floating gate and the control gate is achieved. Even when the film is formed thick, the overhang shape of the sidewall spacer is prevented. Therefore, the etching residue in the subsequent etching process is prevented.

(I) After forming a polysilicon and an oxide film on a semiconductor substrate having a gate oxide film, patterning the polysilicon and the oxide film to form a gate electrode, and (ii) the gate. By forming an HTO film on a semiconductor substrate including electrodes and etching back,
After forming a side wall spacer of HTO film on the side wall of the gate electrode and performing desired ion implantation, (iii)
The gate oxide film and the HTO film on the semiconductor substrate are removed, and a selective gate oxide film is formed by thermal oxidation.
v) Since a nitride film, an oxide film, and a control gate are formed on the semiconductor substrate including the gate electrode and sidewall spacers, a thick H film is formed on the sidewall of the gate electrode.
An insulating film having a small effective thickness is formed on each of the sidewall spacer having the TO film and the select gate oxide film. Therefore, it is possible to prevent the charge stored in the gate electrode from being released and to reduce the size of the device by thinning the selection gate oxide film.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a nonvolatile semiconductor memory according to the present invention will be described with reference to the drawings. Embodiment 1 As shown in FIG. 2, a method for manufacturing a nonvolatile semiconductor memory having a two-layer polysilicon gate structure in which a control gate is provided on a floating gate so as to cover the floating gate will be described with reference to the drawings. To do. Figure 1
(A)-(d) shows the sectional view on the AA line in FIG.

First, as shown in FIG. 1A, an active region 3 is defined by forming a locos oxide film 2 on a silicon substrate 1, and then a film thickness of 90 to 110Å is formed on the entire surface of the silicon substrate 1. Gate oxide film 4 of about 950 ℃ H
Formed by Cl oxidation. Then, a polysilicon film having a film thickness of about 750 to 1500 Å is formed by the CVD method, and N ⁺ impurity is diffused into the polysilicon film. Then N ⁺
A film thickness of 10 is formed on the polysilicon by O ₂ oxidation at 900 ° C.
After forming the SiO ₂ film 6 having a thickness of 0 to 150Å, a film thickness of 150 to _{2 is} further formed on the SiO ₂ film 6 by the CVD method.
The SiN film 7 of about 50Å is formed. Then, the polysilicon is patterned by photoetching using the resist 8 as a mask to form the floating gate (FG) 5 so as to cover the active region 3.

Then, as shown in FIG.
5, silicon substrate 1 including SiO ₂ film 6 and SiN film 7
An HTO film 9 having a film thickness of 1500 to 200Å is formed on the entire upper surface by a CVD method. Thereafter, as shown in FIG. 1C, the HTO film 9 is etched by anisotropic etching to form a sidewall spacer 9a on the sidewall of the FG5. At this time, the HTO film 9 of about 100 to 200 Å is left on the SiN film 7 so as not to reduce the SiN film 7 on the FG 5. Then, an oxide film (not shown) having a film thickness of about 20 to 30 Å is formed on the SiN film 7 by HCl oxidation at 950 ° C.
An interlayer insulating film made of ONO is formed thereover.

Then, CVD is performed on the entire surface of the silicon substrate 1 including the FG 5 and the sidewall spacers 9a.
By the method, polysilicon with a film thickness of about 1500 to 2000 Å is formed, and N ⁺ impurities are diffused into this polysilicon. Next, the polysilicon and ONO interlayer insulating film are continuously etched by a photolithography process to separate the FG 5 into a desired shape and form the control gate (CG) 10.

In the nonvolatile semiconductor memory thus formed, as shown in FIG. 3 which is a sectional view taken along the line BB of FIG. 2, the polysilicon forming the CG 10, the SiO ₂ film 6, the SiN film 7 and the CG 10 are formed. Even when the HTO film 9 is sequentially etched and the FG 5 is further removed by etching, part of the sidewall spacer 9a serves as a mask and etching residue of polysilicon is not generated.

Embodiment 2 First, as shown in FIG. 4A, a locos oxide film 12 is formed on a silicon substrate 11 to form an active region 1.
After specifying 3, the film thickness 90 is formed on the entire surface of the silicon substrate 11.
Gate oxide film 14 of about 110 Å, HC at 950 ° C
It is formed by oxidation. Then, a polysilicon film having a film thickness of about 750 to 1500 Å is formed by the CVD method, and N ⁺ impurity is diffused into the polysilicon film. Then, a film thickness of 100 is formed on the N ⁺ polysilicon by O ₂ oxidation at 900 ° C.
After forming the SiO ₂ film 16 of about 150 Å, a film thickness of 150 to 150 is further formed on the SiO ₂ film 16 by the CVD method.
The SiN film 17 having a thickness of about 250 Å is formed. Then, the polysilicon is patterned by photo-etching using the resist 18 as a mask to cover the active region 13,
FG15 is formed.

Then, as shown in FIG.
By oxidizing the side wall of 15 with HCl at 950 ° C.,
A sidewall spacer 19 of a thermal oxide film having a film thickness of about 100 to 200Å is formed. Then, as shown in FIG. 4C, HTO having a film thickness of 1500 to 200Å is formed on the entire surface of the silicon substrate 1 including the FG 15, the SiO ₂ film 16, the SiN film 17 and the sidewall spacers 19 by the CVD method.
The film 20 is formed.

Next, as shown in FIG. 5D, 100 to 200 is formed on the SiN film 17 by anisotropic etching.
After etching to leave the HTO film 20 of about Å,
By removing the HTO film 20 on the SiN film 17 by etching with 1% HF, the SiN film 17 on the FG 15 is removed.
The FG15 including the sidewall spacers 19 is etched while the HTO film 20 is etched so as not to reduce the film thickness.
Side wall spacer 20a made of HTO
To form. Then, on the SiN film 17, H at 950 ° C.
An oxide film 21 having a film thickness of about 20 to 30 Å is formed by Cl oxidation, and an interlayer insulating film made of ONO is formed.

Then, as shown in FIG. 5E, polysilicon having a film thickness of about 1500 to 2000 Å is formed on the entire surface of the silicon substrate 11 including the FG 15 and the sidewall spacers 19 and 20a by a CVD method. Then
N ⁺ impurities are diffused into this polysilicon. Next, the FG 15 is separated into a desired shape by continuously etching the interlayer insulating film made of polysilicon and ONO by a photolithography process.
To form.

In the nonvolatile semiconductor memory thus formed, as shown in the sectional view of the portion where the control gate is not formed in FIG. 6, CG22 and FG1 are formed.
Even in the case of etching 5, the sidewall spacers 20a do not act as a mask to cause an etching residue of polysilicon.

Example 3 Further, as shown in FIG. 8E, manufacturing of a nonvolatile memory in which an ONO film used as an interlayer insulating film is formed with different thicknesses on the FG and the FG sidewalls. Show the method.

As shown in FIG. 7A, the film thickness 90 to 1
A gate oxide film 32 of about 20 Å is formed on the silicon substrate 31 formed by thermal oxidation by the CVD method to a film thickness of 15
Polysilicon of about 00Å is deposited, and N ⁺ impurities are diffused in this polysilicon. Next, a HT film having a film thickness of about 800 Å is formed on this polysilicon as a CVD-SiO ₂ film.
The O film 34 is formed. Then, using the resist 35 as a mask, the polysilicon and the HTO film 34 are patterned by anisotropic etching, and the HTO film 34 is formed on the upper portion.
Forming a gate electrode 33 having

Then, as shown in FIG. 7B, CVD-S is formed on the entire surface of the silicon substrate 31 including the gate electrode 33.
An HTO film 36 is formed as an iO ₂ film to a film thickness of about 800 Å. Further, as shown in FIG. 7C, the HTO film 36
The HTO film 36 is formed on the silicon substrate 31 so that the silicon substrate 31 is not etched by anisotropic etching.
Is etched to leave about 100 to 200 Å.

Subsequently, as shown in FIG. 8D, in order to form the source / drain regions of the split gate structure, the resist 37 and the gate electrode 33 are used as a mask to ionize arsenic or phosphorus in a desired region. inject. After that, as shown in FIG. 8E, the HTO film 34 or the SiO ₂ film 32 on the silicon substrate 31 is removed by 1% HF.
By removing about 100 to 300 Å, the HTO film 3 is almost completely removed without etching the silicon substrate 31.
4 or the SiO ₂ film 32 is removed. At this time, a film thickness of about 400 to 700 Å remains on the side wall of the gate electrode 33,
The sidewall spacer 36a is formed. Next, an oxide film 40 of about 90 to 150Å is formed by HCl oxidation at 950 ° C. on the select region 39 on the silicon substrate 31, and a SiN film 41 of about 200Å is formed by the CVD method. The SiO ₂ film 42 is formed on the SiN film 41 by HCl oxidation at 950 ° C.
A selection gate ONO film was formed by forming about 30Å. Subsequently, polysilicon is deposited on the silicon substrate 31 containing these, and N ⁺ impurity diffusion is performed on this polysilicon. Then, the selection gate 43 is formed by patterning into a desired shape.

In the nonvolatile memory thus formed, the interlayer insulating film between the gate electrode 33 and the select gate 43 and the silicon substrate 31 and the select gate 43 is formed of the ONO film. The ONO film between the electrode 33 and the select gate 43 can have an effective film thickness of about 600 Å or more, while the ONO film on the select region 39 between the silicon substrate 31 and the select gate 43 has an effective film thickness. The thickness is about 150 to 300Å. Therefore, the withstand voltage of the interlayer insulating film between the gate electrode 33 and the select gate 43 can be ensured, and at the same time, the oxide film 40 serving as the select gate oxide film can be thinned.

[0038]

According to the method of manufacturing a nonvolatile semiconductor memory of the present invention, after the floating gate is formed on the semiconductor substrate, (a) the HT is formed on the sidewall of the floating gate.
Or (b) oxidizing the floating gate sidewalls and then forming an HTO film sidewall spacers on the floating gate sidewalls; and (iii) the floating gate and sidewall spacers. Since the control gate is formed on the upper side, it is possible to secure a sufficient thickness of the interlayer insulating film between the floating gate and the control gate, and even when the interlayer insulating film between the floating gate and the control gate is formed thick, It is possible to prevent the overhang shape of the wall spacers from being generated, and the polysilicon for forming the control gate is not embedded in the overhang portion. Therefore, the etching residue of the control gate in the subsequent process does not occur, and the patterning of the control gate in the subsequent process is facilitated, so that the variation of the control gate width can be prevented. Therefore, it is possible to prevent a short circuit from occurring between adjacent control gates, and it is possible to manufacture a highly reliable nonvolatile semiconductor memory.

After forming the gate electrode on the semiconductor substrate, a sidewall spacer made of an HTO film is formed on the side wall of the gate electrode and desired ion implantation is performed to remove the HTO film on the semiconductor substrate. A selective gate oxide film is formed by thermal oxidation, and (iv) a nitride film, an oxide film, and a control gate are formed on the gate electrode and sidewall spacers, so that the sidewall of the gate electrode has a thick HTO film. An insulating film having a small effective thickness can be formed on each of the sidewall spacers and the select gate oxide film. Therefore, it is possible to prevent the charge stored in the gate electrode from being released, and to secure the breakdown voltage between the gate electrode and the select gate. Further, by thinning the select gate oxide film, it becomes possible to realize the reduction in size of the device.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of a main part showing a first embodiment of a method for manufacturing a nonvolatile semiconductor memory of the present invention.

FIG. 2 is a schematic plan view for explaining the first embodiment of the method for manufacturing the nonvolatile semiconductor memory of the present invention.

FIG. 3 is a sectional view taken along line BB of FIG.

FIG. 4 is a schematic cross-sectional view of a main part showing a second embodiment of the method for manufacturing a nonvolatile semiconductor memory of the present invention.

FIG. 5 is a schematic cross-sectional view of an essential part showing a second embodiment of the method for manufacturing a nonvolatile semiconductor memory of the present invention.

FIG. 6 is a schematic cross-sectional view of a portion where a control gate is not formed in the second embodiment of the method for manufacturing a nonvolatile semiconductor memory of the present invention.

FIG. 7 is a schematic cross-sectional view of a main part showing a third embodiment of the method for manufacturing a nonvolatile semiconductor memory of the present invention.

FIG. 8 is a schematic cross-sectional view of an essential part showing a third embodiment of the method for manufacturing a nonvolatile semiconductor memory of the present invention.

FIG. 9 is a schematic cross-sectional view of a main part showing an embodiment of a conventional method for manufacturing a nonvolatile semiconductor memory.

FIG. 10 is a schematic cross-sectional view of a portion where a control gate is not formed in an example of a conventional method for manufacturing a nonvolatile semiconductor memory.

FIG. 11 is a schematic cross-sectional view of a main part showing a second embodiment of the conventional method for manufacturing a nonvolatile semiconductor memory.

FIG. 12 is a schematic enlarged view of a main part of FIG.

FIG. 13 is a schematic cross-sectional view of a main portion showing a third embodiment of the conventional method for manufacturing a nonvolatile semiconductor memory.

[Explanation of symbols]

 1, 11, 31 Semiconductor substrate (silicon substrate) 4, 14, 32 Gate oxide film 9, 20, 36 HTO film 7, 17, 41 Nitride film 5, 15 Floating gate 33 Gate electrode 9a, 19, 20a, 36a Sidewall Spacer 10,22 Control gate 43 Select gate 40 ・ 41 ・ 42 Select gate oxide film

Claims (2)

[Claims] 1. A floating gate comprising: (i) forming a polysilicon film, an oxide film and a nitride film on a semiconductor substrate having a locos oxide film and a gate oxide film, and then patterning the polysilicon film, the oxide film and the nitride film. And (ii) (a) by forming an HTO film on the semiconductor substrate including the floating gate and performing etch back,
By forming a sidewall spacer of an HTO film on the floating gate side wall, or (b) oxidizing the floating gate side wall, forming an HTO film on the semiconductor substrate including the floating gate, and etching back. A method for manufacturing a non-volatile semiconductor memory, wherein a sidewall spacer made of an HTO film is formed on a sidewall of the floating gate, and (iii) a control gate is formed on the semiconductor substrate including the floating gate and the sidewall spacer. . 2. (i) After forming a polysilicon and an oxide film on a semiconductor substrate having a gate oxide film and then patterning the polysilicon and the oxide film to form a gate electrode, (ii) the gate After forming an HTO film on the semiconductor substrate including the electrodes and etching it back to form a sidewall spacer of the HTO film on the side wall of the gate electrode, and performing desired ion implantation, (iii) on the semiconductor substrate Removing the gate oxide film and the HTO film, and further forming a selective gate oxide film by thermal oxidation, and (iv) forming a nitride film, an oxide film, and a control gate on the semiconductor substrate including the gate electrode and sidewall spacers. A method for manufacturing a non-volatile semiconductor memory, comprising: