JPH0713217Y2 - Lower electrode of semiconductor manufacturing equipment - Google Patents
Lower electrode of semiconductor manufacturing equipmentInfo
- Publication number
- JPH0713217Y2 JPH0713217Y2 JP1988126177U JP12617788U JPH0713217Y2 JP H0713217 Y2 JPH0713217 Y2 JP H0713217Y2 JP 1988126177 U JP1988126177 U JP 1988126177U JP 12617788 U JP12617788 U JP 12617788U JP H0713217 Y2 JPH0713217 Y2 JP H0713217Y2
- Authority
- JP
- Japan
- Prior art keywords
- lower electrode
- wafer
- semiconductor manufacturing
- recess
- wafers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 235000012431 wafers Nutrition 0.000 description 35
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Description
【考案の詳細な説明】 （産業上の利用分野） 本考案はプラズマCVD装置やドライエッチング装置など
の半導体製造装置の下部電極に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a lower electrode of a semiconductor manufacturing apparatus such as a plasma CVD apparatus or a dry etching apparatus.
（従来の技術） 平行平板型プラズマCVD装置について説明すると、上部
電極と下部電極が対向して設けられ、下部電極上にはウ
エハが並べられる。(Prior Art) A parallel plate plasma CVD apparatus will be described. An upper electrode and a lower electrode are provided so as to face each other, and a wafer is arranged on the lower electrode.
成膜動作中はウエハが加熱され、下部電極が回転する。
下部電極表面を平坦面とし、ウエハをその表面上に単に
載せただけの状態で成膜処理を行なうと、ウエハが下部
電極上から滑り落ちることがある。そこで、下部電極表
面にウエハが嵌り込む円形の凹部を形成したものがあ
る。During the film forming operation, the wafer is heated and the lower electrode rotates.
If the film formation process is performed with the lower electrode surface being a flat surface and the wafer simply placed on the surface, the wafer may slip off the lower electrode. Therefore, there is one in which a circular recess into which the wafer is fitted is formed on the surface of the lower electrode.
（考案が解決しようとする課題） ウエハを保持するための凹部が形成された下部電極で
は、その凹部のサイズは特定のウエハのサイズに合わせ
て設計されている。例えば、第３図に示される６インチ
ウエハ２用の凹部４をもつ下部電極1aが設けられている
とすると、サイズの異なったウエハ、例えば４インチウ
エハを処理しようとすれば、第４図に示される４インチ
ウエハ３用の凹部５が設けられた下部電極1bに交換しな
ければならない。下部電極を交換するにはプラズマCVD
装置のチャンバを開ける必要があるが、一般にプラズマ
CVD装置でチャンバを開けるとチャンバ壁面に付着した
窒化膜や酸化膜から微粉末が多量に発生し、チャンバ内
の清掃を行なわなければならない。そのため、下部電極
の交換には約十数時間というような長時間を必要とし、
プラズマCVD装置の稼働効率が悪くなる。(Problems to be Solved by the Invention) In a lower electrode in which a recess for holding a wafer is formed, the size of the recess is designed according to the size of a specific wafer. For example, if a lower electrode 1a having a recess 4 for a 6-inch wafer 2 is provided as shown in FIG. It must be replaced with the lower electrode 1b provided with the recess 5 for the 4-inch wafer 3 shown. Plasma CVD to replace bottom electrode
The chamber of the instrument needs to be opened, but plasma
When the chamber is opened by the CVD device, a large amount of fine powder is generated from the nitride film or oxide film attached to the chamber wall surface, and the inside of the chamber must be cleaned. Therefore, replacement of the lower electrode requires a long time such as about ten hours.
The operation efficiency of the plasma CVD device becomes poor.
この問題は、プラズマCVD装置に限らず、ドライエッチ
ング装置など、ウエハ保持用の凹部が設けられた下部電
極をもつ半導体製造装置には共通に存在する。This problem is not limited to the plasma CVD apparatus, but commonly exists in semiconductor manufacturing apparatuses having a lower electrode provided with a recess for holding a wafer, such as a dry etching apparatus.
本考案はサイズの異なるウエハに対しても共通して使用
することのできる下部電極を備えることによって、半導
体製造装置の稼働効率を上げることを目的とするもので
ある。An object of the present invention is to improve operation efficiency of a semiconductor manufacturing apparatus by providing a lower electrode that can be commonly used for wafers of different sizes.
（課題を解決するための手段） 本考案の下部電極の上面には、多重の円形凹部が内側の
円ほど深さが深くなるように形成されている。(Means for Solving the Problem) On the upper surface of the lower electrode of the present invention, multiple circular recesses are formed such that the inner circle has a deeper depth.
（作用） ウエハに成膜処理やエッチング処理を行なう際、多重の
円形凹部のうち、処理しようとするウエハに合うサイズ
の円形凹部にそのウエハを嵌め込む。(Operation) When a film forming process or an etching process is performed on a wafer, the wafer is fitted into a circular recess having a size suitable for the wafer to be processed among the multiple circular recesses.
（実施例） 第２図に本考案が適用されるプラズマCVD装置の概略を
示す。(Embodiment) FIG. 2 shows an outline of a plasma CVD apparatus to which the present invention is applied.
10は円板状の下部電極であり、その中心が回転軸12で支
持されて回転することができる。下部電極10の表面に
は、円周上に複数個のウエハ２を支持するため、凹部が
形成されており、各凹部にはウエハ２が保持されてい
る。Reference numeral 10 denotes a disk-shaped lower electrode, the center of which is supported by a rotating shaft 12 and can rotate. Recesses are formed on the surface of the lower electrode 10 to support a plurality of wafers 2 on the circumference, and the wafers 2 are held in the respective recesses.
下部電極10の表面に対向して円板状の上部電極14が設け
られている。下部電極10と上部電極14はチャンバ内に設
置され、そのチャンバ内には反応ガスが供給される。下
部電極10と上部電極14間には高周波発振器16が接続さ
れ、下部電極10側が接地されている。高周波発振器16か
ら高周波電圧が印加されてチャンバ内でプラズマ放電が
なされ、ウエハ２上に成膜動作が行なわれる。A disc-shaped upper electrode 14 is provided so as to face the surface of the lower electrode 10. The lower electrode 10 and the upper electrode 14 are installed in a chamber, and a reaction gas is supplied into the chamber. A high frequency oscillator 16 is connected between the lower electrode 10 and the upper electrode 14, and the lower electrode 10 side is grounded. A high frequency voltage is applied from the high frequency oscillator 16 to generate plasma discharge in the chamber, and a film forming operation is performed on the wafer 2.
第１図は一実施例における下部電極の１つの凹部18を示
している。下部電極10の表面に設けられた複数個の凹部
18は、例えば６インチウエハ２にも４インチウエハ３に
も共通に使用できるものとするために、大きいサイズの
ウエハ２用の凹部18aと小さいサイズのウエハ３用の凹
部18bが同心円状に形成されており、小さいサイズの凹
部18bは大きいサイズの凹部18aよりも深く形成されてい
る。FIG. 1 shows one recess 18 of the lower electrode in one embodiment. Multiple recesses provided on the surface of the lower electrode 10
Since 18 can be commonly used for the 6-inch wafer 2 and the 4-inch wafer 3, for example, a concave portion 18a for the large-sized wafer 2 and a concave portion 18b for the small-sized wafer 3 are concentrically formed. The small-sized concave portion 18b is formed deeper than the large-sized concave portion 18a.
20はウエハ2,3をウエハ搬送機構から凹部18に入れた
り、凹部18からウエハ2,3をウエハ搬送機構に移送する
ために、下部電極10の下方からウエハ2,3を押し上げる
治具を挿入する孔である。Reference numeral 20 is a jig for pushing up the wafers 2 and 3 from below the lower electrode 10 to insert the wafers 2 and 3 into the recess 18 from the wafer transfer mechanism or to transfer the wafers 2 and 3 from the recess 18 to the wafer transfer mechanism. It is a hole to do.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be described.
凹部18には大きいサイズ用のもの18aと小さいサイズ用
のもの18bが二重に形成されているので、大きいサイズ
のウエハ２を処理するときは、そのウエハ２は大きいサ
イズの凹部18aに保持され、小さいサイズのウエハ３を
処理するときは、そのウエハ３は小さいサイズの凹部18
bに保持される。Since the large-sized portion 18a and the small-sized portion 18b are double-formed in the concave portion 18, when the large-sized wafer 2 is processed, the wafer 2 is held in the large-sized concave portion 18a. , When processing a small size wafer 3, the wafer 3 will have a small size recess 18
held in b.
このように、２種類のサイズのウエハ2,3に対して搬送
機構のサイズを変更するだけで下部電極10を共通に使用
することができる。In this way, the lower electrode 10 can be used in common by simply changing the size of the transfer mechanism for the two types of wafers 2 and 3.
本考案の下部電極はプラズマCVD装置に限らず、ドライ
エッチング装置にも適用することができる。The lower electrode of the present invention can be applied not only to the plasma CVD apparatus but also to a dry etching apparatus.
実施例は２種類のサイズのウエハに適用するために、二
重の円形凹部が形成されたものを示しているが、３種類
以上のサイズのウエハに適用するには、３重以上に凹部
を形成すればよい。The embodiment shows that a double circular recess is formed in order to apply it to wafers of two different sizes, but in order to apply it to wafers of three or more sizes, three or more recesses are required. It may be formed.
（考案の効果） 本考案の下部電極を備えた半導体製造装置では、サイズ
の異なる複数のウエハに対して同一装置で下部電極を交
換する必要がなく、共通に使用することができる。その
ため半導体製造装置の稼働効率が向上する。(Effect of the Invention) In the semiconductor manufacturing apparatus having the lower electrode of the present invention, it is not necessary to replace the lower electrode in the same apparatus for a plurality of wafers having different sizes, and the same can be used in common. Therefore, the operation efficiency of the semiconductor manufacturing apparatus is improved.
第１図は一実施例を示す部分断面図、第２図は本考案が
適用されるプラズマCVD装置を概略的に示す斜視図、第
３図及び第４図は従来の下部電極を示す部分断面図であ
る。 10……下部電極、2,3……ウエハ、18,18a,18b……凹
部。FIG. 1 is a partial sectional view showing an embodiment, FIG. 2 is a perspective view schematically showing a plasma CVD apparatus to which the present invention is applied, and FIGS. 3 and 4 are partial sectional views showing a conventional lower electrode. It is a figure. 10 ... Lower electrode, 2, 3 ... Wafer, 18, 18a, 18b ... Recessed.
Claims (1)
さが深くなるように形成されている半導体製造装置の下
部電極。1. A lower electrode for a semiconductor manufacturing apparatus, in which multiple circular recesses are formed on an upper surface so that the inner circle has a deeper depth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988126177U JPH0713217Y2 (en) | 1988-09-24 | 1988-09-24 | Lower electrode of semiconductor manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988126177U JPH0713217Y2 (en) | 1988-09-24 | 1988-09-24 | Lower electrode of semiconductor manufacturing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0245631U JPH0245631U (en) | 1990-03-29 |
| JPH0713217Y2 true JPH0713217Y2 (en) | 1995-03-29 |
Family
ID=31377453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988126177U Expired - Lifetime JPH0713217Y2 (en) | 1988-09-24 | 1988-09-24 | Lower electrode of semiconductor manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0713217Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054449A (en) * | 1983-09-05 | 1985-03-28 | Toshiba Corp | Conveying jig for semiconductor wafer |
| JPS6167922A (en) * | 1984-09-12 | 1986-04-08 | Fujitsu Ltd | plasma processing equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5742174Y2 (en) * | 1978-07-28 | 1982-09-17 |
-
1988
- 1988-09-24 JP JP1988126177U patent/JPH0713217Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6054449A (en) * | 1983-09-05 | 1985-03-28 | Toshiba Corp | Conveying jig for semiconductor wafer |
| JPS6167922A (en) * | 1984-09-12 | 1986-04-08 | Fujitsu Ltd | plasma processing equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0245631U (en) | 1990-03-29 |
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