JPH07131832A - Discriminating circuit for digital tone signal - Google Patents

Abstract

PURPOSE:To obtain the discriminating circuit for the digital tone signal which can eliminates the need for its adjustments. CONSTITUTION:The repetition of '0' succession and '1' succession of the sign bit 14 of the input digital tone signal 17 every half period is utilized by a frequency information detection part 6 to inspect the frequency. Then an amplitude information detection part 12 inspects the maximum amplitude by utilizing the presence of the maximum amplitude of the input digital tone signal at a part which is a 1/4 period after the sign bit 14 of the input digital tone signal 17 changes. Further, an AND circuit 13 decides that the input digital tone signal is normal only when the output of the frequency information detection part 6 and the output of the amplitude information detection part 12 are both normal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital tone signal discriminating circuit for discriminating the frequency and amplitude of a received digital tone signal and discriminating whether or not it is transmitted data.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing the configuration of a conventional digital tone signal discrimination circuit.

As shown in FIG. 9, the discrimination circuit has an input terminal 140 for inputting a digital tone signal 117, and the input terminal 140 has a D for converting the input digital tone signal 117 into an analog signal. / A converter 1
30 is connected. A bandpass filter 131 for extracting a predetermined frequency from the output of the D / A converter 130 is connected to the D / A converter 130, and the bandpass filter 131 has a bandpass filter 131. A level detector 132 for detecting the output level is connected. Further, the level detector 132 is connected to a level comparator 133 that compares the output of the level detector 132 with a predetermined level determined in advance, and the level comparator 133 is connected to the level comparator 133. Is connected to the output terminal 141.

Next, the operation will be described.

The digital tone signal 117 input from the input terminal 140 is converted into an analog waveform by the D / A converter 130. The analog output of the D / A converter 130 is a tone signal having a predetermined frequency and amplitude if the input digital tone signal 117 is normal. Then, the bandpass filter 131 extracts a predetermined frequency component, and the level detector 132 detects the amplitude of the predetermined frequency component. Then, the level comparator 33 determines whether the input digital tone signal 117 is pass or fail by comparing the output of the level detector 132 with a predetermined level.

[0006]

However, since the conventional digital tone signal discriminating circuit described above is composed of an analog circuit, it is difficult to make no adjustment, there is a problem in the stability of the circuit, and the integration is difficult. There was a problem that it was difficult.

To solve this problem, Japanese Patent Laid-Open No. 63-286047 discloses a serial-parallel conversion circuit for converting a serially input PCM code into a parallel signal, and the PCM code is prescribed. A comparator for determining whether the level is a threshold level or higher, and a frequency recognition by counting the number of data from when the PCM code exceeds the threshold level to when the polarity changes and exceeds the next threshold level. A frequency recognition counter, a frequency counting counter that counts the number of times that the frequency recognition counter recognizes a desired frequency, and resets the frequency count value when a frequency other than the desired frequency is recognized during a predetermined period. The reset circuit and the frequency counter reach a specified count value within a predetermined period. Discrimination circuit of the PCM digital tone and an output circuit to flag has been proposed when the.

However, JP-A-63-286047
Although the PCM digital tone discrimination circuit disclosed in Japanese Patent Publication can realize the digitization and integration of the circuit,
There is a problem that adjustment to set the threshold level is necessary and no adjustment can be performed.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a discrimination circuit for a digital tone signal capable of eliminating the adjustment of the circuit.

[0010]

According to another aspect of the present invention, there is provided a digital tone signal discriminating circuit in which a sign bit of an input digital tone signal repeats "0" and "1" every half cycle. Using the frequency information detection unit that inspects the frequency by utilizing the fact that the maximum amplitude of the input digital tone signal exists at the 1/4 cycle after the change in the sign bit of the input digital tone signal occurs. AND circuit for determining the input digital tone signal as normal only when both the output of the frequency information detector and the output of the amplitude information detector are normal. And is provided.

According to a second aspect of the present invention, there is provided a digital tone signal discriminating circuit, wherein a shift register circuit for accumulating the sign bit of the input digital tone signal for the period of the input digital tone signal and predetermined data in the shift register circuit. The number of data to add the change points of the output of the pattern comparison circuit and the pattern comparison circuit for judging whether the data accumulated for several minutes can be regarded as the same as the characteristic of the sign bit of the input digital tone signal defined in advance. Comparison result integration period counter to be determined, comparison result change point addition integrator for adding and integrating change points of the output of the pattern comparison circuit for the number of data determined by the comparison result integration period counter, and comparison result change point addition integration Pattern matching number comparator that judges pass / fail for the frequency of the input digital tone signal according to the output of the detector The maximum amplitude inspection is performed by utilizing the frequency information detection unit configured and the fact that the maximum amplitude of the input digital tone signal exists at a quarter period after a change occurs in the sign bit of the input digital tone signal. And an AND circuit that determines that the input digital tone signal is normal only when both the output of the frequency information detector and the output of the amplitude information detector are normal. It is what

The discrimination circuit of the digital tone signal according to the third aspect of the present invention utilizes the fact that the sign bit of the input digital tone signal repeats "0" continuation and "1" continuation every half cycle. The frequency information detector that performs the inspection, the code change detector that detects the change of the code bit of the input digital tone signal, and the output of the code change detector determines the data that maximizes the absolute value of the amplitude of the input digital tone signal. Maximum amplitude position detector, an amplitude detection integral period counter that determines the number of amplitude information data of the input digital tone signal to be added by counting the outputs of the maximum amplitude position detector, specified by the maximum amplitude position detector Amplitude information of the number of data specified by the integration period counter for amplitude detection in the amplitude information of the input digital tone signal is added and integrated. An output of the amplitude information addition integrator and an amplitude information detection unit configured to determine whether the amplitude of the input digital tone signal is acceptable or not according to the output of the amplitude value addition integrator, and the frequency information detection unit. And an output of the amplitude information detection section are both normal, and an AND circuit that determines the input digital tone signal as normal is provided.

According to a fourth aspect of the present invention, there is provided a digital tone signal discriminating circuit which comprises a shift register circuit for accumulating sign bits of an input digital tone signal for a period of the input digital tone signal, and predetermined data in the shift register circuit. The number of data to add the change points of the output of the pattern comparison circuit and the pattern comparison circuit for judging whether the data accumulated for several minutes can be regarded as the same as the characteristic of the sign bit of the input digital tone signal defined in advance. Comparison result integration period counter to be determined, comparison result change point addition integrator for adding and integrating change points of the output of the pattern comparison circuit for the number of data determined by the comparison result integration period counter, and comparison result change point addition integration Pattern matching number comparator that judges pass / fail for the frequency of the input digital tone signal according to the output of the detector A frequency information detector configured, a code change detector that detects a change in the sign bit of the input digital tone signal, and data that maximizes the absolute value of the amplitude of the input digital tone signal is determined by the output of the code change detector. Maximum amplitude position detector, an amplitude detection integral period counter that determines the number of amplitude information data of the input digital tone signal to be added by counting the outputs of the maximum amplitude position detector, specified by the maximum amplitude position detector Input according to the output of the amplitude value addition integrator that adds and integrates the amplitude information of the number of data specified by the amplitude detection integration period counter in the amplitude information of the input digital tone signal Amplitude information detecting section composed of an addition integral value comparator for judging whether the amplitude of the digital tone signal is acceptable, and And it is characterized in that and a logical product circuit determines that the normal input digital tone signal only if the output of the amplitude information detector are both were normal.

According to a fifth aspect of the present invention, there is provided a digital tone signal discriminating circuit, wherein the shift register circuit stores the sign bit of the input digital tone signal for the period of the input digital tone signal, and the predetermined data in the shift register circuit. The number of data to add the change points of the output of the pattern comparison circuit and the pattern comparison circuit for judging whether the data accumulated for several minutes can be regarded as the same as the characteristic of the sign bit of the input digital tone signal defined in advance. Comparison result integration period counter to be determined, comparison result change point addition integrator for adding and integrating change points of the output of the pattern comparison circuit for the number of data determined by the comparison result integration period counter, and comparison result change point addition integration Pattern matching number comparator that judges pass / fail for the frequency of the input digital tone signal according to the output of the detector The configured frequency information detector, the code change detector that detects the change of the sign bit of the input digital tone signal, and the maximum that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal by the output of the code change detector. Amplitude position detector, maximum amplitude position detector Amplitude comparator that determines whether the input digital tone signal is within the allowable range, amplitude comparison that adds by counting the outputs of maximum amplitude position detector Comparison result integration period counter that determines the number of output of the comparator, amplitude comparison result integration amplitude comparison result addition integrator that adds and integrates the number of amplitude comparator outputs specified by the period counter, and amplitude comparison result addition An amplitude information detection unit composed of an addition integral value comparator for judging whether the amplitude of the input digital tone signal is acceptable or not according to the output of the integrator; Is characterized in further comprising a logical product circuit determines that the normal input digital tone signal only if the outputs of the amplitude information detector in the multi-address detection section were both successful.

According to a sixth aspect of the present invention, there is provided a digital tone signal discriminating circuit which delays a code bit of an input digital tone signal by a data amount of about half a cycle of the input digital tone signal. An exclusive OR circuit that outputs the exclusive OR of the sign bit and the output of the delay circuit, a disagreement integration period counter and a disagreement integration period counter that determine the number of data to which the output of the exclusive OR circuit is added The number of discrepancies that adds and integrates the output of the exclusive OR circuit for the number of data determined by the number of discrepancies and the number of discrepancies that determines the pass / fail of the frequency of the input digital tone signal according to the output of the number of discrepancies Frequency information detection unit composed of comparator, code change detector for detecting change of code bit of input digital tone signal, code change The maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal by the output of the output device, and the amplitude information of the input digital tone signal that is added by counting the output of the maximum amplitude position detector Amplitude detecting integral period counter for determining the number of data, and amplitude information for the number of data designated by the amplitude detecting integral period counter of the amplitude information of the input digital tone signal designated by the maximum amplitude position detector An amplitude value addition integrator that adds and integrates an amplitude value addition integrator that determines whether the amplitude of the input digital tone signal is acceptable or not according to the output of the amplitude value addition integrator; An AND circuit that determines the input digital tone signal as normal only when both the output of the detector and the output of the amplitude information detector are normal. It is characterized in further comprising a.

According to a seventh aspect of the present invention, there is provided a digital tone signal discriminating circuit for delaying a sign bit of an input digital tone signal by a data amount of about half a cycle of the input digital tone signal. An exclusive OR circuit that outputs the exclusive OR of the sign bit and the output of the delay circuit, a disagreement integration period counter and a disagreement integration period counter that determine the number of data to which the output of the exclusive OR circuit is added The number of discrepancies that adds and integrates the output of the exclusive OR circuit for the number of data determined by the number of discrepancies and the number of discrepancies that determines the pass / fail of the frequency of the input digital tone signal according to the output of the number of discrepancies A frequency information detection unit composed of a comparator, a code change detector for detecting a change in the code bit of the input digital tone signal, and a code change detector. Maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal by the output of the detector. Whether the input digital tone signal specified by the maximum amplitude position detector is within the allowable range. Specified by the amplitude comparison result integration period counter, the amplitude comparison result integration period counter that determines the number of amplitude comparator outputs to add by counting the outputs of the maximum amplitude position detector Amplitude comparison result summing integrator for adding and integrating the outputs of the number of amplitude comparators, and an amplitude comparison result summing integral value comparator for judging whether the amplitude of the input digital tone signal is acceptable or not according to the output of the addition integrator. The input digital tone signal is normal only when both the amplitude information detection unit output and the frequency information detection unit output and the amplitude information detection unit output are normal. It is characterized in further comprising a logical product circuit for determining.

The discrimination circuit of the digital tone signal according to the present invention utilizes the fact that the sign bit of the input digital tone signal repeats "0" continuation and "1" continuation every half cycle. It is characterized in that it is provided with a frequency information detection unit for performing inspection.

According to a ninth aspect of the present invention, there is provided a digital tone signal discriminating circuit provided with a code converter for separating an input digital tone signal having an arbitrary code into a code bit and amplitude information. Is.

According to a tenth aspect of the present invention, there is provided a digital tone signal discriminating circuit provided with a serial-parallel converter for converting a serial input digital tone signal inputted in serial into a parallel signal.

[0020]

In the discrimination circuit of the digital tone signal according to the invention described in claim 1, the frequency information detecting unit uses that the sign bit of the input digital tone signal repeats "0" continuous and "1" continuous every half cycle. Then, the frequency is inspected, and the maximum amplitude of the input digital tone signal exists at the 1/4 cycle after the change in the sign bit of the input digital tone signal occurs by the amplitude information detection unit. The amplitude is checked, and the input digital tone signal is determined to be normal by the AND circuit only when both the output of the frequency information detector and the output of the amplitude information detector are normal. This makes it possible to eliminate adjustment of the circuit.

In the digital tone signal discriminating circuit according to the second aspect of the present invention, in the frequency information detecting section, the shift register circuit stores the sign bit of the input digital tone signal for the period of the input digital tone signal, and the pattern comparing circuit. Determines whether the data accumulated by the predetermined number of data in the shift register circuit can be regarded as the same as the characteristic of the sign bit of the input digital tone signal defined in advance, and the comparison result integration period counter Determines the number of data points to which the change points of the output of the pattern comparison circuit are added, and adds and integrates the change points of the output of the pattern comparison circuit for the number of data points determined by the comparison result integration period counter by the comparison result change point addition integrator Then, according to the output of the comparison result changing point addition integrator It is determined whether or not the frequency of the input digital tone signal has passed, and it is determined that the maximum amplitude of the input digital tone signal exists at a quarter period after the change in the sign bit of the input digital tone signal by the amplitude information detection unit. The maximum amplitude is inspected by utilizing it, and the input digital tone signal is determined to be normal by the AND circuit only when both the output of the frequency information detector and the output of the amplitude information detector are normal. This makes it possible to eliminate adjustment of the circuit.

In the digital tone signal discriminating circuit according to the third aspect of the present invention, the frequency information detecting unit uses that the sign bit of the input digital tone signal repeats "0" continuous and "1" continuous every half cycle. Then, the amplitude information detector detects the change of the sign bit of the input digital tone signal by the sign change detector, and the maximum amplitude position detector detects the change of the input digital tone signal by the output of the sign change detector. Determine the data that maximizes the absolute value of the amplitude, and determine the number of data of the amplitude information of the input digital tone signal to be added by counting the output of the maximum amplitude position detector by the amplitude detection integration period counter. Amplitude detection product of the amplitude information of the input digital tone signal specified by the maximum amplitude position detector by the value addition integrator Amplitude information of the number of data designated by the period counter is added and integrated, and the addition / integration value comparator determines whether the amplitude of the input digital tone signal is acceptable or not according to the output of the amplitude value addition and integrator. And the output of the amplitude information detector are both normal, the logical product circuit determines that the input digital tone signal is normal. This makes it possible to eliminate adjustment of the circuit.

In the discrimination circuit of the digital tone signal according to the present invention, in the frequency information detecting section, the shift register circuit accumulates the sign bit of the input digital tone signal for the period of the input digital tone signal, and the pattern comparison circuit. Determines whether the data accumulated by the predetermined number of data in the shift register circuit can be regarded as the same as the characteristic of the sign bit of the input digital tone signal defined in advance, and the comparison result integration period counter Determines the number of data points to which the change points of the output of the pattern comparison circuit are added, and adds and integrates the change points of the output of the pattern comparison circuit for the number of data points determined by the comparison result integration period counter by the comparison result change point addition integrator Then, according to the output of the comparison result changing point addition integrator In the amplitude information detector, the sign change detector detects the sign bit change of the input digital tone signal, and the maximum amplitude position detector inputs the sign change detector output. Determine the data for which the absolute value of the amplitude of the digital tone signal is maximum, and count the output of the maximum amplitude position detector by the amplitude detection integration period counter to add the number of data of the amplitude information of the input digital tone signal. The amplitude value addition integrator adds and integrates the amplitude information of the number of data specified by the amplitude detection integration period counter among the amplitude information of the input digital tone signal specified by the maximum amplitude position detector, The addition and integration value comparator determines whether the amplitude of the input digital tone signal is acceptable or not according to the output of the amplitude value addition and integrator, and determines the frequency information. Determined to be normal input digital tone signal by AND circuit only when the outputs of the amplitude information detector in the detector are both were normal. This makes it possible to eliminate adjustment of the circuit.

In the digital tone signal discriminating circuit according to the invention of claim 5, in the frequency information detecting section, the shift register circuit stores the sign bit of the input digital tone signal for the period of the input digital tone signal, and the pattern comparing circuit. Determines whether the data accumulated by the predetermined number of data in the shift register circuit can be regarded as the same as the characteristic of the sign bit of the input digital tone signal defined in advance, and the comparison result integration period counter Determines the number of data points to which the change points of the output of the pattern comparison circuit are added, and adds and integrates the change points of the output of the pattern comparison circuit for the number of data points determined by the comparison result integration period counter by the comparison result change point addition integrator Then, according to the output of the comparison result changing point addition integrator In the amplitude information detector, the sign change detector detects the sign bit change of the input digital tone signal, and the maximum amplitude position detector outputs the sign change detector with the output of the sign change detector. Data that maximizes the absolute value of the amplitude of the input digital tone signal is determined, and the amplitude comparator determines whether the input digital tone signal specified by the maximum amplitude position detector is within the allowable range. The number of outputs of the amplitude comparator to be added is determined by counting the maximum amplitude position detector output by the comparison result integration period counter, and is specified by the amplitude comparison result integration period counter by the amplitude comparison result addition integrator. Number of amplitude comparator outputs are added and integrated, and the added and integrated value comparator compares the amplitudes of the input digital tone signals according to the output of the amplitude comparison result addition and integrator. The judgment is determined to be normal input digital tone signal by AND circuit only when the outputs of the amplitude information detector in the frequency information detecting unit is normal both. This makes it possible to eliminate adjustment of the circuit.

In the digital tone signal discriminating circuit according to the present invention, the sign bit of the input digital tone signal is delayed by the delay circuit in the frequency information detecting section by the data of about half the cycle of the input digital tone signal. , The exclusive OR circuit outputs the exclusive OR of the sign bit of the input digital tone signal and the output of the delay circuit, and the number of discrepancies integration period counter determines the number of data to add the output of the exclusive OR circuit. Then, the output of the exclusive OR circuit for the number of data determined by the number-of-mismatch integration period counter is added and integrated by the number-of-mismatch add-integrator, and the number-of-mismatch comparator compares the output of the number-of-mismatch integrator The pass / fail of the frequency of the input digital tone signal is judged, and the input digital tone is detected by the code change detector in the amplitude information detector. Detecting a change in the sign bit of No.,
The maximum amplitude position detector determines the data that maximizes the absolute value of the amplitude of the input digital tone signal at the output of the code change detector, and the amplitude detection integral cycle counter counts the maximum amplitude position detector output. By determining the number of amplitude information data of the input digital tone signal to be added,
Amplitude value Integral value of the number of data specified by the integration period counter for amplitude detection in the amplitude information of the input digital tone signal specified by the maximum amplitude position detector by the addition integrator is added and integrated value The comparator determines whether the amplitude of the input digital tone signal is acceptable or not according to the output of the amplitude value integrator, and only when both the output of the frequency information detector and the output of the amplitude information detector are normal The product circuit determines that the input digital tone signal is normal. This makes it possible to eliminate adjustment of the circuit.

In the digital tone signal discriminating circuit according to the seventh aspect of the present invention, in the frequency information detecting section, the delay circuit delays the sign bit of the input digital tone signal by about half the period of the input digital tone signal. , The exclusive OR circuit outputs the exclusive OR of the sign bit of the input digital tone signal and the output of the delay circuit, and the number of discrepancies integration period counter determines the number of data to add the output of the exclusive OR circuit. Then, the output of the exclusive OR circuit for the number of data determined by the number-of-mismatch integration period counter is added and integrated by the number-of-mismatch add-integrator, and the number-of-mismatch comparator compares the output of the number-of-mismatch integrator The pass / fail of the frequency of the input digital tone signal is judged, and the input digital tone is detected by the code change detector in the amplitude information detector. Detecting a change in the sign bit of No.,
The maximum amplitude position detector determines the data that maximizes the absolute value of the amplitude of the input digital tone signal at the output of the sign change detector, and the amplitude comparator inputs the input digital tone signal specified by the maximum amplitude position detector. Is within the permissible range, the output of the maximum amplitude position detector is counted by the amplitude comparison result integration cycle counter, the number of amplitude comparator outputs to be added is determined, and the amplitude comparison result is added. Amplitude comparison result integration by the integrator Adds and integrates the outputs of the amplitude comparators of the number specified by the cycle counter, and the addition integral value comparator gives the amplitude comparison result. If the output of the frequency information detector and the output of the amplitude information detector are both normal, the logical product circuit determines that the input digital tone signal is normal. A constant. This makes it possible to eliminate adjustment of the circuit.

In the discrimination circuit of the digital tone signal according to the present invention, the frequency information detecting unit uses the sign bit of the input digital tone signal to repeat "0" continuation and "1" continuation every half cycle. Then, the frequency is inspected, the pass / fail judgment of the digital tone signal is performed only by the frequency, and the amplitude information detector and the AND circuit can be omitted to simplify the circuit.

According to a ninth aspect of the present invention, there is provided a digital tone signal discriminating circuit, wherein a code converter separates an input digital tone signal having an arbitrary code into a code bit and amplitude information, and an input digital tone having an arbitrary code. It can be generalized according to the signal.

According to a tenth aspect of the present invention, a digital tone signal discriminating circuit converts a serial input digital tone signal serially input by a serial-parallel converter into a parallel signal, and corresponds to the serial input digital tone signal serially input. Then, it can be generalized.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

Example 1. FIG. 1 shows claims 1 to 4.
It is a block diagram which shows the structure of the discrimination circuit of the digital tone signal based on the invention described above.

The discrimination circuit for the digital tone signal has an input terminal 42 for inputting the sign bit 14 of the input digital tone signal 17 and an input terminal 43 for inputting the amplitude information 15 of the input digital tone signal 17. The input digital tone signal 17 is input to the input terminal 42.
A frequency information detection unit 6 for inspecting a frequency is connected by utilizing the fact that the sign bit 14 of “0” and “1” are repeated every half cycle, and the input terminals 42 and 43 are connected to The amplitude information detection unit 12 for inspecting the amplitude utilizes the fact that the maximum amplitude of the input digital tone signal 17 exists at a quarter period after the change occurs in the sign bit 14 of the input digital tone signal 17. It is connected. Further, the frequency information detecting unit 6 and the amplitude information detecting unit 12 include the output of the frequency information detecting unit 6 and the amplitude information detecting unit 12.
The AND circuit 13 that determines the input digital tone signal to be normal is connected only when both the output and the output are normal, and the output terminal 44 that outputs the determination result is connected to the AND circuit 13. There is.

Then, the frequency information detector 6 changes the output of the shift register circuit 1 for accumulating the sign bit 14 of the input digital tone signal 17 for the period of the input digital tone signal 17 and the pattern comparison circuit 2 described later. The shift register circuit 1 has a comparison result integration period counter 3 that determines the number of data points to be added.
A pattern comparison circuit 2 is connected to determine whether or not the data accumulated by the predetermined number of data in the shift register circuit 1 can be regarded as having the same characteristics as the code bit of the predetermined input digital tone signal. ing. Further, the pattern comparison circuit 2 and the comparison result integration period counter 3
A comparison result change point addition integrator 4 for adding and integrating the change points of the output of the pattern comparison circuit 2 for the number of data determined by the comparison result integration period counter 3 is connected to the. The integrator 4 is connected to a pattern matching number comparator 5 that determines pass / fail of the frequency of the input digital tone signal 17 according to the output of the comparison result change point addition integrator 4.

The amplitude information detector 12 has a code change detector 7 for detecting a change in the code bit 14 of the input digital tone signal 17, and the code change detector 7
A maximum amplitude position detector 8 that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal 17 by the output of the sign change detector 7 is connected to the. And
The maximum amplitude position detector 8 is connected to an amplitude detecting integration period counter 9 that determines the number of data of the amplitude information 15 of the input digital tone signal 17 to be added by counting the output of the maximum amplitude position detector 8. The maximum amplitude position detector 8, the amplitude detection integral period counter 9 and the input terminal 43.
Is an amplitude value addition for adding and integrating the amplitude information of the data number specified by the amplitude detection integration period counter 9 in the amplitude information 15 of the input digital tone signal 17 specified by the maximum amplitude position detector 8. The integrator 10 is connected. Further, the amplitude value addition integrator 10 is connected with an addition integration value comparator 11 that determines pass / fail of the amplitude of the input digital tone signal 17 according to the output of the amplitude value addition integrator 10.

FIG. 2 is a diagram showing the input digital tone signal 17. In the figure, 18 is a number temporarily assigned to the digital tone signal, and 19 is a digital tone signal waveform. Reference numeral 20 indicates the content of the sign bit of the digital tone signal, 21 indicates the content of the sign bit of the digital tone signal delayed by a half cycle, and 22 indicates the exclusive OR of the sign bit 20 and the sign bit 21. .

Therefore, it can be seen from FIG. 2 that the sign bit 20 of the digital tone signal repeats "0" continuous and "1" continuous every half cycle. The frequency inspection is performed by utilizing this property. In the case of FIG. 2, data number 0
And the data number 1 change the sign bit, and there is a point of maximum amplitude after 1/4 cycle (data number 5 or 6). Amplitude inspection is performed using this property.

Next, the operation of this embodiment will be described.

The sign bit 14 of the input digital tone signal 17 input from the input terminal 42 is sequentially accumulated for one cycle by the shift register circuit 1 of the frequency information detecting section 6. Then, the pattern comparison circuit 2 outputs the output of the shift register circuit 1 to the code bit 20 as shown in FIG.
Is compared with a pattern of repeating "0" and "1" every half cycle. In the pattern comparison circuit 2, when the output of the shift register circuit 1 and the pattern of the code bit 20 shown in FIG. 2 completely match, or when the output of the shift register circuit 1 and the code bit 20 shown in FIG. It may be determined that they are the same even when the patterns are similar.

When the detection is performed with a similar pattern, there is a possibility that the output of the shift register circuit 1 has a plurality of timings for determining that it is a characteristic pattern in one cycle of the digital tone signal. Therefore, the comparison result change point addition integrator 4 extracts only the change points of the pattern comparison circuit 2, and the comparison result integration period counter 3
The change points of the output of the pattern comparison circuit 2 are added by the number of data determined by. Since the output of the comparison result change point addition integrator 4 corresponds to the degree of approximation between the sign bit 14 and the characteristic pattern, the output of the comparison result change point addition integrator 4 in the pattern matching number comparator. Frequency inspection is performed by inspecting.

On the other hand, in the amplitude information detecting section 12, if the input digital tone signal 17 is a normal digital tone signal, the maximum value of the amplitude exists 1/4 cycle after the change of the sign bit 14. The sign change detector 7 is
The change in the sign bit 14 of the input digital tone signal 17 is detected, and the maximum amplitude position detector 8 specifies the data in which the amplitude information 15 becomes maximum about 1/4 cycle after the change in the sign bit 14. Then, the amplitude value addition integrator 10 adds the data designated by the maximum amplitude position detector 8 by the number of data designated by the amplitude detection integration period counter 9. The output of the amplitude value integrator 10 corresponds to the amplitude of the input digital tone signal 17. Then, the value added by the amplitude detecting integral period counter 9 is inspected by the adding integral value comparator 11, and the input digital tone signal 17
Conduct the amplitude inspection.

Further, the judgment result 16 is judged to be normal only when the output of the frequency information detector 6 and the output of the amplitude information detector 12 are both normal by the AND circuit 13.

Example 2. In the first embodiment, the amplitude information 15 is sequentially added and the results are compared. However, the present invention is not limited to this, and the amplitude information 15 may be sequentially compared and the comparison result may be added. .

FIG. 3 is a block diagram showing the structure of a digital tone signal discriminating circuit according to the present invention, wherein amplitude information 15 is sequentially compared and the comparison results are added. It should be noted that the same components as those in FIG.

In FIG. 3, 23 is an amplitude comparison result integration period coefficient unit for designating the number of data, 24 is an amplitude value comparator for sequentially comparing the amplitude information 15 designated by the maximum position detector 8, and 25 is , An amplitude comparison result addition integrator that adds the comparison result by the number of data designated by the amplitude comparison result integration period coefficient device 23, and 26 is an addition comparison result comparator that determines whether the amplitude is acceptable or not.

Therefore, the amplitude information detecting section 12 sequentially compares the amplitude information 15 designated by the maximum position detector 8 by the amplitude value comparator 24, and the comparison result by the amplitude comparison result integration period coefficient unit 23. The specified amount of data is added by the amplitude comparison result addition integrator 25, and the addition comparison result comparator 26 is added.
The pass / fail of the amplitude is determined by.

Example 3. In the first and second embodiments described above,
The sign bit 14 of the input digital tone signal 17 is compared with a characteristic pattern. However, if odd high frequencies are not a particular problem, the configuration shown in FIG. 4 can be adopted.

FIG. 4 is a block diagram showing a configuration of a digital tone signal discriminating circuit according to the sixth aspect of the present invention. It should be noted that the same components as those in FIG.

In FIG. 4, reference numeral 34 is a delay circuit for delaying the code bit 14 by data corresponding to about half the cycle of the input digital tone signal 17, and 35 is the code bit 14
And an output of the delay circuit 34 and an exclusive OR circuit for calculating an exclusive OR. Further, 36 is a mismatch number integration period counter that determines the number of data to be added by the output of the exclusive OR circuit 35, and 37 is an exclusive OR for the number of data determined by the mismatch number integration period counter 36. Circuit 3
It is a disagreement addition integrator that adds and integrates the output of 5
Reference numeral 8 denotes a mismatch number comparator which determines whether the frequency of the input digital tone signal 17 is acceptable or non-defective according to the output of the mismatch number addition integrator 37.

Next, the operation of this embodiment will be described.

If it is a normal digital tone signal, the code bit 14 repeats "0" continuation and "1" continuation every half cycle. The frequency information detection unit 6 detects the repetition of "0" continuation and "1" continuation as follows. That is, the sign bit 14 is delayed by a half cycle in the delay circuit 34,
The sign bit 14 and the output of the delay circuit 34 are input to the exclusive OR circuit 35, and the exclusive OR circuit 35 calculates the exclusive OR of the sign bit 14 and the output of the delay circuit 34.

Then, the output of the exclusive OR circuit 35 is
As indicated by reference numeral 22 in FIG. 2, all are "1" in the case of a normal digital tone signal. This exclusive OR circuit 35
Is added by the number-of-mismatch addition integrator 37 by the number of data designated by the number-of-mismatch integration cycle counter 36. The output of the non-matching number addition integrator 37 corresponds to the degree of repetition of "0" continuity and "1" continuity for each half cycle of the sign bit 14. Then, the frequency of difference is checked by inspecting the output of the number-of-mismatch adder / integrator 37 by the number-of-mismatch comparator 38.

Example 4. FIG. 5 is a block diagram showing the configuration of a digital tone signal discrimination circuit according to the invention of claim 7.

A feature of this embodiment is that the amplitude information detecting section 12 shown in FIG. 3 and the frequency information detecting section shown in FIG. 4 constitute a digital tone signal discriminating circuit. The same components as those in FIGS. 3 and 4 are designated by the same reference numerals and the description thereof will be omitted. Even with such a configuration, the same effect as that of the above-described embodiment can be obtained.

Example 5. FIG. 6 is a block diagram showing the configuration of a discrimination circuit for a digital tone signal according to the eighth aspect of the present invention.

The feature of this embodiment is that the frequency information detecting section 206 determines whether the input digital tone signal 217 is passed or failed.
It is to carry out only by the frequency according to. Therefore, the amplitude information detector 12 and the AND circuit 13 are not required, and the circuit can be simplified. It should be noted that the same effect can be obtained even if the frequency information detection unit 206 has the configuration shown in FIG.

Example 6. FIG. 7 is a block diagram showing the configuration of a digital tone signal discriminating circuit according to the present invention.

In the above embodiment, the input digital tone signal 217 is assumed to be a code that can be separated into the code bit 214 and the amplitude information 215, but there is a problem that it cannot correspond to any input digital tone signal. It was Therefore, in this embodiment, a code converter 227 for separating the arbitrary input digital tone signal 217 into the code bit 214 and the amplitude information 215 is provided so that it can correspond to the arbitrary input digital tone signal.
Although FIG. 7 shows an example in which the code converter 227 is arranged in the discrimination circuit of FIG. 4, the same effect can be obtained by combining it with any of the discrimination circuits of FIGS. 1, 3, and 5. .

Example 7. FIG. 8 is a block diagram showing a configuration of a digital tone signal discrimination circuit according to the tenth aspect of the present invention. The same components as those in FIG. 7 are designated by the same reference numerals and the description thereof will be omitted.

In the above-mentioned embodiment, the input digital tone signal 217 is supplied as parallel data, but the serial input digital tone signal 229 is added by adding the serial-parallel converter 228 to the input side.
Can correspond to. In FIG. 8, the code converter 22
Although the example in which 7 is arranged in the discrimination circuit in FIG. 7 is shown, the same effect can be obtained by combining any of the discrimination circuits in FIGS. 1 to 5.

[0060]

As described above, according to the inventions described in claims 1 to 7, the frequency information detecting unit causes the sign bit of the input digital tone signal to be "0" continuous every half cycle. The frequency is inspected by repeating "1" continuous and 1/4 after the change in the sign bit of the input digital tone signal is generated by the amplitude information detector.
The amplitude is checked by using the existence of the maximum amplitude of the input digital tone signal at the cycle, and the logic is checked only when both the output of the frequency information detector and the output of the amplitude information detector are normal. Since the product circuit is configured to determine that the input digital tone signal is normal, the adjustment for setting the threshold level becomes unnecessary, and the circuit can be adjusted.

According to the eighth aspect of the present invention, the frequency information is detected by utilizing the fact that the sign bit of the input digital tone signal repeats "0" continuation and "1" continuation every half cycle. Since the digital tone signal pass / fail judgment is performed only by the frequency, the amplitude information detector and the AND circuit can be omitted, and the circuit can be simplified.

According to the ninth aspect of the invention, since the input digital tone signal having an arbitrary code is separated by the code converter into the code bit and the amplitude information, the input digital tone signal having an arbitrary code. Generalization can be achieved corresponding to the signal.

According to the tenth aspect of the present invention, since the serial input digital tone signal serially input by the serial-parallel converter is converted into the parallel signal, it corresponds to the serial input digital tone signal input serially. Then, generalization can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a discrimination circuit for a digital tone signal according to the invention described in claims 1 to 4.

FIG. 2 is a diagram showing an input digital tone signal according to the present invention.

FIG. 3 is a block diagram showing a configuration of a discrimination circuit for a digital tone signal according to a fifth aspect of the invention.

FIG. 4 is a block diagram showing a configuration of a discrimination circuit for a digital tone signal according to a sixth aspect of the invention.

FIG. 5 is a block diagram showing a configuration of a discrimination circuit for a digital tone signal according to a seventh aspect of the invention.

FIG. 6 is a block diagram showing a configuration of a discrimination circuit for a digital tone signal according to an eighth aspect of the invention.

FIG. 7 is a block diagram showing a configuration of a discrimination circuit for a digital tone signal according to the invention described in claim 9;

FIG. 8 is a block diagram showing a configuration of a digital tone signal discrimination circuit according to the tenth aspect of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional digital tone signal discrimination circuit.

[Explanation of symbols]

 1 shift register circuit 2 pattern comparison circuit 3 comparison result integration period counter 4 comparison result change point addition integrator 5 pattern matching number comparator 6 frequency information detection unit 7 sign change detector 8 maximum amplitude position detector 9 amplitude detection integration Period counter 10 Amplitude value addition integrator 11 Addition integral value comparator 12 Amplitude information detection unit 13 AND circuit 23 Amplitude comparison result integration Period counter 24 Amplitude value comparator 25 Amplitude comparison result Addition integrator 26 Addition comparison result comparator 27 code converter 28 serial-parallel converter 34 delay circuit 35 exclusive OR circuit 36 disagreement number integration period counter 37 disagreement number addition integrator 38 disagreement number comparator

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[Procedure amendment]

[Submission date] February 24, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

The digital tone signal 117 input from the input terminal 140 is converted into an analog waveform by the D / A converter 130. The analog output of the D / A converter 130 is a tone signal having a predetermined frequency and amplitude if the input digital tone signal 117 is normal. Then, the bandpass filter 131 extracts a predetermined frequency component, and the level detector 132 detects the amplitude of the predetermined frequency component. Then, the level comparator 133 determines whether the input digital tone signal 117 is pass or fail by comparing the output of the level detector 132 with a predetermined level.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

However, JP-A-63-286047
Although the PCM digital tone discrimination circuit disclosed in Japanese Patent Publication can realize the digitization and integration of the circuit,
There is a problem that it is not possible to determine an abnormal state with respect to an excessive input .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0060

[Correction method] Change

[Correction content]

[0060]

As described above, according to the inventions described in claims 1 to 7, the frequency information detecting unit causes the sign bit of the input digital tone signal to be "0" continuous every half cycle. The frequency is inspected by repeating "1" continuous and 1/4 after the change in the sign bit of the input digital tone signal is generated by the amplitude information detector.
The amplitude is checked by using the existence of the maximum amplitude of the input digital tone signal at the cycle, and the logic is checked only when both the output of the frequency information detector and the output of the amplitude information detector are normal. Since the product circuit is configured to judge the input digital tone signal as normal, the amplitude information
The maximum value and the minimum value can be set for the information judgment, and the circuit can be adjusted.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Explanation of Codes] 1 shift register circuit 2 pattern comparison circuit 3 comparison result integration period counter 4 comparison result change point addition integrator 5 pattern matching number comparator 6 frequency information detection unit 7 sign change detector 8 maximum amplitude position detector 9 amplitude detection integration cycle counter 10 amplitude value addition integrator 11 addition integration value comparator 12 amplitude information detection unit 13 AND circuit 23 amplitude comparison result integration cycle counter 24 amplitude value comparator 25 amplitude comparison result addition integrator 26 Addition / comparison result comparator 227 Code converter 228 Serial / parallel converter 34 Delay circuit 35 Exclusive OR circuit 36 Discrepancy number integration period counter 37 Discrepancy number addition integrator 38 Discrepancy number comparator

Claims (10)

[Claims] 1. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information represented by a sign bit and several bits, wherein the sign bit of the input digital tone signal is "0" every half cycle. A frequency information detection unit that inspects the frequency by repeating "1" and "1" continuity, and an input digital tone at a quarter cycle after a change occurs in the sign bit of the input digital tone signal. Input only when both the output of the frequency information detection unit and the output of the amplitude information detection unit, which performs the inspection of the maximum amplitude by utilizing the existence of the maximum amplitude of the signal, are normal. A circuit for discriminating a digital tone signal, comprising: a logical product circuit for judging that the digital tone signal is normal. 2. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information expressed by a sign bit and several bits, wherein the sign bit of the input digital tone signal is the period of the input digital tone signal. A pattern for determining whether or not the shift register circuit for storing only the amount of data, and the data accumulated by the predetermined number of data in the shift register circuit can be regarded as having the same characteristic as the code bit of the input digital tone signal defined in advance Add the change points of the output of the comparison circuit and the pattern comparison circuit Determine the number of data to add the comparison result integration period counter, add the change points of the output of the pattern comparison circuit for the number of data determined by the comparison result integration period counter Input according to the output of the comparison result change point addition integrator to be integrated and the comparison result change point addition integrator. A frequency information detection unit consisting of a pattern match number comparator that determines pass / fail of the frequency of the digital tone signal, and the input digital tone at a quarter period after the change in the sign bit of the input digital tone signal. Input only when both the output of the frequency information detection unit and the output of the amplitude information detection unit, which performs the inspection of the maximum amplitude by utilizing the existence of the maximum amplitude of the signal, are normal. A circuit for discriminating a digital tone signal, comprising: a logical product circuit for judging that the digital tone signal is normal. 3. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information represented by a sign bit and several bits, wherein a sign bit of the input digital tone signal is "0" every half cycle. By the output of the frequency information detection unit that inspects the frequency by using the repetition of "1" and "1" continuity, the code change detector that detects the change of the sign bit of the input digital tone signal, and the output of the sign change detector Maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal, and determines the number of amplitude information data of the input digital tone signal to be added by counting the output of the maximum amplitude position detector Amplitude detection integral cycle counter, of the amplitude information of the input digital tone signal specified by the maximum amplitude position detector The amplitude value addition integrator that adds and integrates the amplitude information for the number of data specified by the amplitude detection integration period counter, and the pass / fail of the amplitude of the input digital tone signal is determined according to the output of the amplitude value addition integrator. An amplitude information detection unit including an addition integral value comparator, and a logic that determines the input digital tone signal as normal only when both the output of the frequency information detection unit and the output of the amplitude information detection unit are normal. A product tone circuit, and a discrimination circuit for a digital tone signal, comprising: 4. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information expressed by a sign bit and several bits, wherein the sign bit of the input digital tone signal is the period of the input digital tone signal. A pattern for determining whether or not the shift register circuit for storing only the amount of data, and the data accumulated by the predetermined number of data in the shift register circuit can be regarded as having the same characteristic as the code bit of the input digital tone signal defined in advance Add the change points of the output of the comparison circuit and the pattern comparison circuit Determine the number of data to add the comparison result integration period counter, add the change points of the output of the pattern comparison circuit for the number of data determined by the comparison result integration period counter Input according to the output of the comparison result change point addition integrator to be integrated and the comparison result change point addition integrator. The output of the frequency information detection unit, which consists of a pattern match number comparator that determines pass / fail of the frequency of the digital tone signal, the code change detector that detects the change of the sign bit of the input digital tone signal, and the output of the code change detector Maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal, and determines the number of amplitude information data of the input digital tone signal to be added by counting the output of the maximum amplitude position detector Amplitude detecting integral cycle counter, amplitude for adding and integrating the amplitude information of the data number designated by the amplitude detecting integral cycle counter among the amplitude information of the input digital tone signal designated by the maximum amplitude position detector Determines whether the amplitude of the input digital tone signal is acceptable or not according to the output of the value addition integrator and the amplitude value addition integrator The input digital tone signal is determined to be normal only when both the output of the frequency information detecting unit and the output of the amplitude information detecting unit are normal. An AND circuit, and a discrimination circuit for a digital tone signal, comprising: 5. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information expressed by a sign bit and several bits, wherein the sign bit of the input digital tone signal is the period of the input digital tone signal. A pattern for determining whether or not the shift register circuit for storing only the amount of data, and the data accumulated by the predetermined number of data in the shift register circuit can be regarded as having the same characteristic as the code bit of the input digital tone signal defined in advance Add the change points of the output of the comparison circuit and the pattern comparison circuit Determine the number of data to add the comparison result integration period counter, add the change points of the output of the pattern comparison circuit for the number of data determined by the comparison result integration period counter Input according to the output of the comparison result change point addition integrator to be integrated and the comparison result change point addition integrator. Input by the frequency information detection unit consisting of a pattern matching number comparator that judges pass / fail of the frequency of the digital tone signal, the code change detector that detects the change of the code bit of the input digital tone signal, and the output of the code change detector A maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the digital tone signal, and an amplitude comparator that determines whether the input digital tone signal specified by the maximum amplitude position detector is within the allowable range. , Amplitude comparison result integration period counter for determining the number of outputs of the amplitude comparator to be added by counting the maximum amplitude position detector output, and the number of amplitude comparators specified by the amplitude comparison result integration period counter Depending on the output of the amplitude comparison result addition integrator that adds and integrates the output and the amplitude comparison result addition integrator, The input digital tone signal is output only when both the output of the frequency information detecting section and the output of the amplitude information detecting section are normal, and the amplitude information detecting section configured by an addition integral value comparator that determines pass / fail of the width. A discriminator circuit for a digital tone signal, comprising: a logical product circuit for judging normality. 6. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information expressed by a sign bit and several bits, wherein the sign bit of the input digital tone signal is the period of the input digital tone signal. A delay circuit that delays about half the period of data, an exclusive OR circuit that outputs the exclusive OR of the sign bit of the input digital tone signal and the output of the delay circuit, and data that adds the output of the exclusive OR circuit. Discrepancy count integration period counter that determines the number, Discrepancy count addition integrator that adds and integrates the outputs of the exclusive OR circuits for the number of data determined by the discrepancy count integration period counter, and the output of the discrepancy number addition integrator A frequency information detection unit composed of a mismatch count comparator that determines pass / fail for the frequency of the input digital tone signal according to A sign change detector that detects a change in the sign bit of the digital tone signal, a maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal from the output of the sign change detector, a maximum amplitude position Amplitude detection integration period counter for determining the number of pieces of amplitude information data of the input digital tone signal to be added by counting the output of the detector, of the amplitude information of the input digital tone signal designated by the maximum amplitude position detector. Of the amplitude value of the input digital tone signal is judged according to the output of the amplitude value addition integrator that adds and integrates the amplitude information for the number of data specified by the amplitude detection integration period counter in Amplitude information detection unit composed of an addition integral value comparator, and the output of the frequency information detection unit and the output of the amplitude information detection unit are both Discrimination circuit of the digital tone signal, characterized in that it also comprises a logical product circuit determines that the normal input digital tone signal only if was normal. 7. A digital tone signal discriminating circuit for discriminating an input digital tone signal composed of amplitude information expressed by a sign bit and several bits, wherein the sign bit of the input digital tone signal is the period of the input digital tone signal. A delay circuit that delays about half the period of data, an exclusive OR circuit that outputs the exclusive OR of the sign bit of the input digital tone signal and the output of the delay circuit, and data that adds the output of the exclusive OR circuit. Discrepancy count integration period counter that determines the number, Discrepancy count addition integrator that adds and integrates the outputs of the exclusive OR circuits for the number of data determined by the discrepancy count integration period counter, and the output of the discrepancy number addition integrator And a frequency information detection unit composed of a mismatch count comparator that determines pass / fail of the frequency of the input digital tone signal according to Sign change detector that detects a change in the sign bit of the input digital tone signal, maximum amplitude position detector that determines the data that maximizes the absolute value of the amplitude of the input digital tone signal from the output of the sign change detector, maximum amplitude position Amplitude comparator that determines whether the input digital tone signal specified by the detector is within the allowable range. Determines the number of amplitude comparator outputs to be added by counting the outputs of the maximum amplitude position detector. Input according to the output of the amplitude comparison result integration period counter, the amplitude comparison result addition integrator that adds and integrates the outputs of the number of amplitude comparators specified by the amplitude comparison result integration period counter, and the output of the amplitude comparison result addition integrator Amplitude information detection unit configured by an addition integral value comparator that determines pass / fail of the amplitude of the digital tone signal, and output of the frequency information detection unit and amplitude information Discrimination circuit of the digital tone signal, characterized in that it comprises a logical product circuit determines that the normal input digital tone signal only if the output of the detecting portion are both were normal. 8. A digital tone signal discriminating circuit for discriminating an input digital tone signal, wherein the sign bit of the input digital tone signal repeats "0" continuation and "1" continuation every half cycle. A circuit for discriminating a digital tone signal, comprising a frequency information detector for inspecting a frequency. 9. A code converter for separating an input digital tone signal consisting of an arbitrary code into a code bit and amplitude information, according to any one of claims 1 to 8. Discrimination circuit for digital tone signals according to paragraph. 10. A serial-parallel converter for converting a serial input digital tone signal, which is serially input, into a parallel signal is provided, and the serial-parallel converter is provided in any one of claims 1 to 9. Discrimination circuit for digital tone signals.