JPH07131493A - Decoding circuit for nonencoded bit - Google Patents

Abstract

PURPOSE:To provide the nonencoded bit decoding circuit which can reduce the scale of the circuit without any deterioration in error correcting capability. CONSTITUTION:This nonencoded bit decoding circuit is equipped with an area deciding means 13 which outputs area information corresponding to a group of symbols specified with a received symbol in a symbol group set by specific bit arrangement required for nonencoded bit decoding from the received symbol, a delay means 15 which delays the area information outputted from the area deciding means 13 by the time required to decode encoded bits at a Viterbi decoding part 11, and a nonunecoded bit decoding means 17 which inputs the output of this delay means 15 and the Viterbi-decoded bits from the Viterbi decoding part 11 and decodes them to output nonencoded bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-coded bit decoding circuit of a trellis decoding circuit for decoding trellis coded modulated information symbols.

[0002]

2. Description of the Related Art In recent years, in the field of broadcasting and the like, a trellis coded modulation system is used as a coding method for obtaining a coding gain in a limited frequency band. For the coding method and effects, see, for example, "Trellis-" by G. Ungerboeck.
Coded Modulation with Redundant Signal Sets Part
I; Introduction "and his work" Trellis-Coded Modulatio "
nWith Redundant Signal Sets Part II; State of the A
rt '', IEEE Communications Magazine, 1987-Vol.25.No.2
Are described in.

A brief overview will be given below. The general form of the trellis encoder is shown in FIG. Referring to FIG. 11, information symbol (k + m) bits are converted to uncoded bits (k bits).
And the encoded bits (n bits) obtained by expanding the m bits by the convolutional encoder 101 are modulation symbols (k + n).
Bits are modulated and transmitted. The trellis coded modulation system is characterized by the arrangement of the modulation symbols.

FIG. 10 shows an example in which k = 2, m = 1, n = 2 and the modulation method is 16QAM. In the example shown in FIG. 10, the upper 2 bits correspond to non-coded bits and the lower 2 bits correspond to coded bits. From the configuration of the trellis encoder shown in FIG. 11, it is clear that the coded bits of the lower 2 bits have a larger inter-code distance. Therefore, for the upper 2 bits, the inter-code distance is determined by the modulation symbol arrangement.

In FIG. 10, for example, a symbol ◯ is a symbol whose lower 2 bits are “00”, a symbol “11”, a symbol “01”, and a symbol “10”. Is. By arranging as shown in FIG. 10, for symbols that differ only in the upper 2 bits, the distance in the modulation symbol arrangement is maximized and the total inter-code distance is taken, which is the basic principle of the trellis coded modulation method. Is.

By the way, the receiving side decodes this by the Viterbi algorithm. The basic state transition diagram of the decoding includes parallel state transitions as shown in FIG. That is, in the case of this example, among the state transitions from time (j-1) to time j, focusing on the transition from state {0,0} to state {0,0}, the possible encoder output is There are four ways. In this case, the number of cases where 2 bits of non-coding can be taken is four, which corresponds to the symbol of ◯ in FIG. Also, for the coded bits “11”, four branches corresponding to the symbols of Δ are input to the state {0,0} at time j. Therefore, the path selection at this node is to select the path having the closest distance to the received symbol sequence from the eight paths.

Further, in the case of soft decision of the received symbol, it is assumed that the position e of the received symbol is detected by the soft decision at a position as shown in FIG. In this case, first, the branch metric is obtained to obtain the path metric. At this time, it is clear that the distance to the symbol ∘8 is the shortest among the distances to the four ∘ symbols.

[0008] In the text, ○ 8 means that 8 is entered in ○ (for example, refer to FIG. 8), and similarly ΔF is △.
It means the one in which F is entered. That is, by writing a character immediately after the figure, it means that the character is written in the figure.

In this way, when the path is selected by using the branch metric, the time (j-
The path (Rj-1) left in 1) is common to the four paths passing through the path of the symbol ◯, so the path (Rj-1)
The path metric for -1) is also common. Therefore,
The difference in path metric for these four paths is equal to the difference in branch metric for each of the O symbols. Therefore, the calculation of the path metric for selecting the path can be represented by the calculation for the path passing through ∘8. Therefore, this ∘8 is called a representative symbol.

Regarding the symbol Δ, from FIG. 13, ΔF
Is the closest to the received symbol, and ΔF is the representative symbol. Therefore, it is sufficient to consider only the path passing through ΔF among the paths indicated by the dotted lines in FIG. 14, and the path metric of the path passing through ∘8 is compared with the pulse metric of the path passing through ΔF, and the likelihood is large. , That is, the path with the smaller path metric is selected. Thus, in trellis decoding, it is not necessary to calculate the branch metric for all symbols, and it is sufficient to calculate the branch metric only for the representative symbol determined by the position of the received symbol.

In this way, the coded bit at time j is decoded by the Viterbi algorithm, and it is "0".
If it is 1 ”, the possible modulation symbols of the representative symbol set ∘8, ΔF, ⊚2, □ 5 at time j are □ 5 whose lower 2 bits are“ 01 ”.
The non-coded bit is “01” which is the upper 2 bits. That is, the non-coded bits can be decoded using the Viterbi-decoded coded bits.

To summarize the above, the basic structure of trellis decoding is roughly divided into an uncoded bit decoding unit 105 and a Viterbi decoding unit 103 as shown in FIG. In addition,
Viterbi-decoded coded bits are used for decoding the non-coded bits.

FIG. 16 shows the configuration of the conventional uncoded bit decoding unit in more detail. This is k = 2,
In this example, m = 1 and n = 2.

First, the soft decision value of the received symbol is 10 bits (q
= 10), four representative symbols are detected by the representative symbol detection unit 113. Each symbol is 4bit
However, since the upper 2 bits are decoded, the representative symbols may be detected in the upper 2 bits. When a T-stage path memory is used for Viterbi decoding, that is, when T received symbols are used for decoding one symbol, the decoding requires a processing time of T steps.
At 5, a delay corresponding to this processing time is applied. Then, the coded bits (2
uncoded bits, which is a possible combination of
The non-coded bit selector 117 selects and outputs. The remaining 1 bit obtained by removing the non-coded bits from the information symbol (3 bits) is directly obtained from the Viterbi decoding circuit 111.

[0015]

However, according to the example of FIG. 10 described above, there are nine possible sets of representative symbols (J = 9), and although it can be represented by 4 bits originally (3 <Log ₂ J <4) According to the configuration shown in FIG. 16, the output of the representative symbol detection unit 113 is 8 bits and redundant. In particular, if the representative symbol detection unit 113 is composed of a ROM, the scale will be 2 ¹⁰ × 8≉8 kbits = 16k transistors, and the T-stage shift register 115 will have T = 3.
If 22 transistors are required for 1 bit as 2, the scale will be 8 × 32 × 22 = 5632 transistors (see FIG. 2).

The present invention has been made in view of the above problems, and an object of the present invention is to provide a non-coded bit decoding circuit capable of reducing the circuit scale without deteriorating the error correction capability.

[0017]

In order to achieve the above object, the first invention of the present application is to convolutionally encode a part of a predetermined number of bits for an information symbol composed of a plurality of bits on the transmission side. A Viterbi decoding unit based on a received symbol obtained by demodulating at the receiving side a coded bit, the rest of the bits being non-coded bits and paired with the coded bits, and being trellis coded and modulated. A non-coded bit decoding circuit of a trellis decoding circuit that decodes non-coded bits using coded bits decoded by, wherein a symbol group set in a predetermined bit arrangement, that is, a received symbol from a subset is selected. For the area determination unit that outputs area information corresponding to a specified symbol, that is, a set of representative symbols, and area information output from this area determination unit The delay means for delaying the time required for decoding the coded bits in the Viterbi decoding section, and the output of this delay means and the coded bits that are Viterbi decoded by the Viterbi decoding section are input and decoded. The gist is to have a non-coded bit decoding unit that outputs coded bits.

Specifically, on the transmitting side, with respect to an information symbol composed of a plurality of bits, m bits that are a part of the information symbol are convolutionally coded, and the remaining k bits are coded as n (> m) bits. Trellis coded modulation of (k + m) bits in combination with the coded bits is performed with the bits as uncoded bits, and the received signal is decoded by the Viterbi decoding circuit with the received symbol demodulated by the demodulator as an input. In a trellis decoding circuit configured to decode k non-coded bits by using n coded bits, a set of representative symbols (2 ⁿ Symbol) and information for one-to-one correspondence with the received symbol area determination means, and a delay corresponding to the time required to decode the coded bits. And to delay means inputs the its output the Viterbi decoding coded bits, and the uncoded bits decoder outputs the uncoded bits by decoding.

According to a second aspect of the present invention, the non-coded bit decoding circuit according to the first aspect further comprises amplitude limiting means for limiting the amplitude of the received symbol, and the area information is output on the output of the amplitude limiting means. The main point is to get it.

Further, the third invention of the present application is as follows.
The area information of the non-coded bit decoding circuit described in (3) is smaller than log ₂ J, where J is the number of symbols specified by the received symbols of the possible symbol group, that is, a subset, that is, a set of representative symbols. The gist is that it is not represented, for example, it is represented by the minimum number of bits.

[0021]

The non-coded bit decoding circuit of the first invention of the present application is
Corresponds to a symbol group that is set by the region determination means in a predetermined bit arrangement required for non-coded bit decoding from the received symbol, that is, a symbol specified by the received symbol from the subset, that is, a set of representative symbols. Area information is determined, and the determined area information is output. The delay means delays the area information by the time required for the Viterbi decoding unit to decode the coded bits. The output of the delay unit and the coded bits that are Viterbi-decoded by the Viterbi decoding unit are input to the non-coded bit decoding unit and decoded to output the non-coded bits.

Since the non-coded bit decoding circuit of the second invention of the present application further comprises the amplitude limiting means for limiting the amplitude of the received symbol, the efficiency can be further improved.

In the non-coded bit decoding circuit of the third invention of the present application, the region information is lo when the number of symbol sets specified by the received symbols of the possible symbol group is J.
It is represented by the minimum number of bits that is not smaller than g ₂ J, for example.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an uncoded bit decoding circuit according to the present invention.

The configuration of this embodiment will be described below with reference to FIG. In the non-coded bit decoding circuit of this embodiment, the received symbols are input to the Viterbi decoding unit 11 and the area determination unit 13, respectively. An uncoded bit decoder 17 is serially connected to the area determination unit 13 via a T-stage shift register 15. The coded bits output from the Viterbi decoding unit 11 are input to the non-coded bit decoder 17. As a result, the Viterbi decoding unit 11 obtains a Viterbi decoded bit, and the non-coded bit decoder 17 obtains a non-coded bit. In the configuration example shown in FIG. 1, (k = 2, m = 1, n = 2).

Next, the operation of this embodiment will be described. FIG. 3 shows an example of the positional relationship between the output of the area determination unit 13 shown in FIG. 1 and the received symbol. In the case of the nine-valued soft decision shown in FIG. 3, the dotted line indicates the boundary of each area, and there are nine areas in total, and a 4-bit numerical value is assigned to each area. In addition, these are one-to-one with nine sets of representative symbols.
It corresponds with. For example, when the position of the received symbol is a, the output of the area determination unit 13 is (0010), which corresponds to the set of representative symbols {□ 9, ○ C, ◎ 6, △ 3}.

When the received symbol is at the position of b, the output of the area judgment unit 13 is (0110), which corresponds to the set of representative symbols {○ C, □ 5, △ 3, ◎ 2}. . If the received symbol is exactly on the boundary,
The correction ability is not affected even if it is included in either area.

To represent the set of representative symbols, 4 bits should be sufficient because there are only 9 ways in the example of FIG. Therefore, in order to obtain the area information indicating in which area the received symbol is located, the area determination unit 13 that associates the received symbol with the set of representative symbols and determines in which area the received symbol is located.

The area determination unit 13 determines which representative symbol group the received symbol corresponds to one-to-one, and outputs an area determination bit (4 bits) as area information. This area determination bit is delayed by the T-stage shift register 15 as a delay means by a time corresponding to the decoding processing time in the Viterbi decoding unit 11, and is output to the non-coding bit decoder 17. This non-coded bit decoder 17 has a delay output of 4bi of the T-stage shift register 15.
t and the coded bit (2
bit) and are decoded to output the uncoded bit 2 bits. At this time, there are only 9 sets of representative symbols,
Each set is represented by 4 bits, and it is clear that if the lower 2 bits are determined by this, the upper 2 bits can be uniquely determined.

The non-encoded bit decoding section (area determination section 13, T stage shift register 15, non-encoded bit decoder 17) of the present embodiment shown in FIG. 1 and the conventional non-encoded bit shown in FIG. Decoding unit (representative symbol detection unit 113, T
Stage shift register 115, uncoded bit selector 11
FIG. 2 shows a chart comparing 7) and 7) by the number of transistors constituting each. Referring to FIG. 2, in terms of the number of transistors, (A) representative symbol detection / region determination part and (B) T-stage shift register part are dominant in (C) uncoded bit selector / decoder part. It can be seen that the conventional about 22K transistor is about half the size of about 11K transistor in this embodiment.

Further, in the example of 9-value soft decision shown in FIG.
When areas of h and Qch are independently determined as shown in FIG. 4, the input / output relationship is as shown in FIG. 5 (for each channel). It is clear from FIG. 5 that it is not necessary to decode all 5 bits of each channel, and only the upper 3 bits are required. Therefore, when it is composed of ROM, it is 2 ³ × 2
= 16-bit ROM can be realized with two ROMs.

Next, a second embodiment according to the present invention will be described with reference to FIG. FIG. 6 is a diagram showing an output example of the area determination means when the branch metric is obtained after the received symbol is subjected to amplitude limitation.

Even if the branch metric is obtained after limiting the amplitude of the received symbol as shown in FIG. 6, the correction capability is not deteriorated. This is because the order of the Euclidean distance for each representative symbol does not change even if the amplitude is limited. For example, the received symbol c shown in FIG.
The representative symbol closest to is □ 9, and ○ C and ◎
The distance is small in the order of 6 and Δ3. Even in the received symbol d after the amplitude is limited, there is no change in this order.

When the area determination is performed on the received symbol d after the amplitude is limited in this way, a circuit configuration with higher efficiency (small scale) becomes possible.

FIG. 7 shows the input / output relationship of the area determining means of each channel at this time. Input "011", "01"
0 "," 001 "," 000 "," 111 "," 11 "
Since there are 7 types of "0" and "101", only these 7 types should be decoded.

Next, a third embodiment according to the present invention will be described with reference to FIGS. FIG. 8 shows an example of a better signal arrangement when the number of uncoded bits is 2 bits or more (non-coded 2 bits).
).

In this, first, a symbol group set with a predetermined bit arrangement, that is, an uncoded 2-bit (higher-order 2 bits) arrangement in each subset symbol of the subset is mapped by a Gray code. Specifically, for example, when paying attention to a symbol of ◯ (lower 2 bits are “00”), adjacent symbols ◯ 0 and ◯ 4, and a symbol ◯ 0
And ◯ 8 should be different only in 1 bit.

Next, among the representative symbols of each subset,
Adjacent ones are arranged so that the lower 2 bits of the coded bits differ by only 1 bit. In particular,
For example, □ 5 and ◯ C, and □ 5 and Δ3 which are adjacent to each other are made to differ by only 1 bit for the lower 2 bits.

By doing so, the magnitude relationship between the Euclidean distance and the Hamming distance for the non-coded bits matches. In addition, since the magnitude relationship between the Euclidean distance and the Hamming distance is the same for the coded bits to be subjected to Viterbi decoding, the BER characteristic is 0.1 to 0. It is improved by about 3 dB.

FIG. 9 shows an example in which a simulation experiment is performed by a computer by applying the amplitude limitation and the region determination of the second embodiment using the signal arrangement shown in FIG. In the figure, graph [a] is the BER characteristic of uncoded QPSK,
Graph [b] is the BER characteristic of 16QAM, graph [c]
Is an asymptotic lower bound (theoretical value) of BER and characteristics of 16TCM of this embodiment calculated based on the above-mentioned document. In the graph [d], the bit number of the soft decision value of the received symbol is 10 bits.
It is a BER characteristic by simulation in the case of (q = 10). Graph [e] is the BER when q = 12
It is a characteristic. In this case, in the area determination means, I,
Q, 6-bit input and 2-bit output respectively. As shown in the first or second embodiment, it is not necessary to decode all 6 bits, and the upper 3 bits of I and Q respectively.
It can also be realized by decoding each (the upper 3 bits are 6 bits
Of accuracy). Further, when q = 12, the region determination can be performed more accurately, so that good characteristics are obtained.

The number of bits of the above-mentioned area determination output is not smaller than log ₂ J with respect to the number J of symbol (representative symbol) pairs specified by the received symbol,
It is optimal to use the minimum number of bits. For example, in the example shown in FIG. 3, J = 9 and 3 <log ₂ J <4, so the number of bits of the region determination output is 4 in each of the above embodiments.

If the number of bits of the output of this area determination is 4 or more (the number of bits not smaller than log ₂ J), it can be realized by an arbitrary number.

For example, when the number of bits is 5, even if 4 or 4 bits indicating each area shown in FIG. 3 are added with 0 or 1 to form 5 bits, an area judgment output corresponding to each area on a one-to-one basis can be obtained. You can In this case, the circuit scale of the non-encoded bit decoding unit is 5/4 times as large as that of the first embodiment shown in FIG. 2 and therefore requires 14 to 15K transistors, but is smaller than the conventional 22K transistor. be able to.

[0044]

As described above, according to the present invention, the circuit scale of the non-coded bit decoding circuit of the trellis decoding circuit can be reduced without deteriorating the error correction capability.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a non-coded bit decoding unit according to an embodiment of the present invention.

FIG. 2 is a chart for comparing the non-coded bit decoding unit shown in FIG. 1 with a conventional non-coded bit decoding unit.

FIG. 3 is a diagram showing a relationship between a received symbol position and an output of a region determination means.

FIG. 4 is a diagram showing a configuration of an area determination unit when the area determination is independently performed for the I channel and the Q channel.

5 is a chart showing the input / output relationship of the area determination means shown in FIG.

FIG. 6 is a diagram showing an output example of a region determination means when an amplitude limit is included.

FIG. 7 is a table showing the input / output relationship of the area determination means when amplitude is restricted.

FIG. 8 is a diagram showing an example of a better signal arrangement.

FIG. 9 is a diagram showing BER characteristics by a computer simulation experiment.

FIG. 10 is a diagram showing an example of a trellis-coded modulation symbol arrangement.

FIG. 11 is a diagram showing a general form of a trellis encoder.

FIG. 12 is a diagram showing an example of parallel state transitions.

FIG. 13 is a diagram showing received symbols and branch metrics.

FIG. 14 is a block diagram showing an example of representative symbols and state transitions.

FIG. 15 is a diagram showing a basic form of a trellis decoder.

FIG. 16 is a block diagram showing a schematic configuration of a conventional non-coded bit decoding unit.

[Explanation of symbols]

 11 Viterbi decoding unit 13 area determination unit 15 T-stage shift register 17 non-coded bit decoder.

Claims (3)

[Claims] 1. An information symbol composed of a plurality of bits on the transmission side is convolutionally coded by convolutionally coding a predetermined number of bits of a part of the information symbols, and the remaining bits are coded as uncoded bits. Trellis that decodes non-coded bits using the coded bits decoded by the Viterbi decoding unit based on the received symbols obtained by demodulating the trellis coded modulation in pairs with the coded bits on the receiving side. A non-coded bit decoding circuit of the decoding circuit, which includes area determining means for outputting area information corresponding to a set of symbols specified by the received symbol from a symbol group set in a predetermined bit arrangement; A delay unit that delays the area information output from the area determination unit by a time required for decoding the coded bits in the Viterbi decoding unit, and an output of the delay unit. And a coded bit that has been Viterbi-decoded by the Viterbi decoding unit, and a non-coded bit decoding unit that outputs a non-coded bit by decoding the coded bit. . 2. The non-coded bit decoding circuit according to claim 1, further comprising amplitude limiting means for limiting the amplitude of the received symbol, and obtaining area information about an output of the amplitude limiting means. 3. The area information is represented by a bit number that is not smaller than log ₂ J, where J is the number of symbol sets specified by received symbols in the possible symbol groups. The non-coded bit decoding circuit according to claim 1 or 2, characterized in that: