JPH07130984A - Mos gate semiconductor device - Google Patents

Abstract

PURPOSE:To increase a breakdown-resistant amount in a turning-off operation and to shorten the time for the turning-off operation. CONSTITUTION:An n<-> type semiconductor region 12 is formed at the upper part of a p<+> type semiconductor substrate 11. A p-type channel region 13 and a p<+> type gate region 14 which surrounds the p-type channel region 13 are formed on the surface part of the n<-> type semiconductor region 12. In addition, an n<+> type cathode region 15 is formed on the surface part inside the p-type channel region 13. A p<+> type cathode short-circuit region 31 is formed on the surface part of the n<-> type semiconductor region 12 by keeping an interval of a channel length P from the p<+> type cathode region 15 so as to be shallower than the p<+> type gate region 14. The n<+> type cathode region 15 and the p<+> type cathode short-circuit region 31 are short-circuited electrically. A silicon oxide film 17 which is spread up to the upper part of the p<+> type gate region 14 is formed on the surface of the n<-> type semiconductor region 12 between the p<+> type gate region 14 and the p<+> type cathode short-circuit region 31. Gate electrodes 20 are formed on the surface of the silicon oxide film 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS gate semiconductor device, and more particularly to a MOS gate semiconductor device having a cathode short structure.

[0002]

2. Description of the Related Art Power semiconductor devices for controlling a large amount of power have been widely used. However, these semiconductor devices are required to have low power consumption, high speed switching and high breakdown voltage depending on their applications.

FIG. 2 shows a cathode short circuit type MOS gate thyristor as an example of a semiconductor device intended for high speed switching. In the figure, the anode region p
^An n ⁻ type semiconductor region 12 is formed on the upper surface of the ⁺ type semiconductor substrate 11, and a p type channel region 13 is selectively formed on the surface of the n ⁻ type semiconductor region 12.
Further, on the surface of the n ⁻ type semiconductor region 12, a p ⁺ type gate region 14 is formed deeper than the p type channel region 13 so as to surround and connect to the p type channel region 13. Further, in the surface portion of the n ⁻ type semiconductor region 12, the p ⁺ type gate region 14 is separated from the p ⁺ type semiconductor region 12 by a predetermined distance d.
A mold cathode short region 16 is formed. Also,
An n ⁺ type cathode region 15 is selectively formed on the surface of the p type channel region 13.

A silicon oxide film 17 is formed on the upper surface of the n ^-- type semiconductor region 12 in which the above-mentioned region is formed, but one surface of each of the n ⁺ -type cathode region 15 and the p ⁺ -type cathode short region 16 is formed. Part of the silicon oxide film 17
Have been selectively removed. Then, the silicon oxide film 17 is connected to the respective surfaces of the n ⁺ type cathode region 15 and the p ⁺ type cathode short region 16 from which the silicon oxide film 17 has been removed,
A cathode electrode 18 and a cathode shorting electrode 19 are formed respectively, and the electrodes are electrically short-circuited. On the surface of the silicon oxide film 17, p ⁺
On the n ⁻ type semiconductor region 12 located between the type gate region 14 and the p ⁺ type cathode short region 16, and from the upper portion of the p ⁺ type gate region 14 to the end of the p ⁺ type cathode short region 16. The gate electrode 20 is formed so as to rise. On the other hand, on the lower surface of the p ⁺ type semiconductor substrate 11,
The anode electrode 21 is formed uniformly.

Next, the operation of the cathode short circuit type MOS gate thyristor having the above construction will be described with reference to FIG. In the turn-on operation, by applying a positive voltage to the gate, a displacement current utilizing the gate capacitance is injected from the p ⁺ type gate region 14 and the p type channel region 13 into the n ⁺ type cathode region 15. This current causes electrons to be emitted from the n ⁺ type cathode region 15 to the p type channel region 13, and the electrons reach the p ⁺ type semiconductor substrate 11. Electrons reaching the p ⁺ -type semiconductor substrate 11, a p ⁺ -type semiconductor substrate 11 n ^- promotes the injection of holes into the semiconductor region 12, flows the holes into the n ⁺ type cathode region 15, the thyristor Enters the latch-up state.

On the other hand, in the turn-off operation, by applying a negative voltage to the gate, the p ⁺ type gate regions 14 and p
^The vicinity of the surface of the n ⁻ type semiconductor region 12 between the ⁺ type cathode short region 16 is inverted from n type to p type to form a p channel. As a result, excess holes existing in the n ⁻ type semiconductor region 12 and the p ⁺ type gate region 14 are swept out to the cathode terminal through the p channel and the p ⁺ type cathode short region 16, and the anode-cathode is removed. Cut off carrier flow.

As described above, the cathode short-circuit type M having the above structure
In the OS gate thyristor, excess carriers are extinguished in a short time at turn-off to realize high-speed switching (higher frequency).

[0008]

By the way, in the cathode short circuit type MOS gate thyristor having the above structure, in general,
The p ⁺ type cathode short region 16 is formed by thermally diffusing the p type impurity introduced into the surface of the n ⁻ type semiconductor region 12. In the formation of the semiconductor region by such thermal diffusion, the depth of the semiconductor region is determined according to the amount of impurities to be introduced, the diffusion time, the diffusion temperature, and the like. Further, the lateral spread is diffused at a substantially constant ratio with the depth.

However, in the formation of the semiconductor region by the thermal diffusion as described above, the spread of the semiconductor region follows a Gaussian distribution, so that the depth and the lateral spread of the formed semiconductor region vary. .

An example in which the spread of the semiconductor region varies will be described with reference to FIG. In the figure, the semiconductor regions 13 'to 16' are the semiconductor regions 13 to 16 respectively.
The semiconductor regions are formed in the same step as, and the same numbers correspond to each other.

In the thyristor cell A shown on the left side of the figure, the distance d between the p ⁺ type gate region 14 and the p ⁺ type cathode short region 16 near the surface of the n ⁻ type semiconductor region 12 (of the MOS transistor The channel length) is an appropriate distance designed in advance. However, as mentioned above,
Since the spread of the semiconductor region formed by thermal diffusion varies, it is difficult to accurately control the channel length of the MOS transistor, and the p ⁺ type gate region in the thyristor cell B shown on the right side of FIG. 14 '
And the distance d'between the p ⁺ -type cathode short region 16 '
May be different from the distance d.

When the distance d'is small, the distance of the p channel formed near the surface of the n ^-- type semiconductor region 12 in the turn-off operation becomes short, and the electric resistance of the p channel becomes small. Therefore, at the time of turn-off, the n ⁻ type semiconductor region 12 and the p ⁺ type gate region 1 are
When the excess carriers existing in 4 ′ were swept out to the cathode terminal, the carrier flow was concentrated in the p channel having a small distance d ′, and the destruction due to heat generation was likely to occur there.

In the latch-up state of the thyristor, most of the carriers flowing from the anode side reach the cathode terminal through the n ⁺ type cathode region 15 (15 '), but some carriers are , P ⁺ type gate region 14 (14 ′), n ⁻ type semiconductor region 12 and p ⁺
Type cathode short circuit region 16 (16 ')
It flows out through the np transistor. At this time,
When the distance d ′ is small, the amplification factor of the parasitic pnp transistor is high, and the carriers flowing out through the parasitic pnp transistor increase. Therefore, the current flowing through the thyristor portion decreases and the on-voltage increases. Was there.

On the other hand, when the distance d'is large, the distance of the p-channel formed at turn-off becomes long, and the resistance of the p-channel becomes large. Therefore,
It becomes difficult to sweep out the excess carriers through the p channel, and the turn-off time of the thyristor cell becomes long.

As described above, the conventional cathode short circuit type MOS
In the gate thyristor, variations in the spread of the semiconductor region due to thermal diffusion have caused problems such as a decrease in breakdown resistance at turn-off, an increase in on-voltage, and an increase in turn-off time.

The present invention solves the above problems,
It is an object of the present invention to realize a MOS gate type semiconductor device which has a high breakdown resistance at turn-off and a short turn-off time.

[0017]

In a MOS gate semiconductor device according to a first aspect of the present invention, a second conductivity type second semiconductor region is selected on a surface portion of a first conductivity type first semiconductor region. From the second semiconductor region to the surface of the first semiconductor region by selectively forming a third semiconductor region of the first conductivity type on the surface of the second semiconductor region. A fourth semiconductor region of the second conductivity type is selectively formed at a predetermined interval so as to be shallower than the second semiconductor region. Then, the third semiconductor region and the fourth semiconductor region are electrically connected, and insulation is provided on the surface of the first semiconductor region between the second semiconductor region and the fourth semiconductor region. A film is formed, and an electrode is provided on the insulating film.

In a MOS gate semiconductor device according to a second aspect of the present invention, the second conductivity type channel region is selectively formed on the surface portion of the first conductivity type first semiconductor region, and the first conductivity type channel region is formed.
A second conductivity type gate region is formed on the surface of the semiconductor region so as to surround the channel region, and a first conductivity type cathode region is selectively formed on the surface of the channel region. A second conductive type second semiconductor region is formed on the surface portion of the semiconductor region at a predetermined distance from the gate region and is shallower than the gate region, and the second conductive type is formed on the lower surface of the first semiconductor region. Forming an anode region of the. Here, the first semiconductor region is a semiconductor region having a low impurity concentration, and is, for example, an epitaxial layer.

The cathode region and the second semiconductor region are electrically connected (that is, the second semiconductor region is a cathode short region), and the gate region and the cathode short region are connected to each other. An insulating film made of, for example, an oxide film (SiO ₂ ) is formed on the surface of the first semiconductor region, and a gate electrode is provided on the insulating film.

A MOS gate semiconductor device according to a third aspect of the present invention is based on the MOS gate semiconductor device according to the second aspect, and is formed by extending the insulating film to an upper portion of the gate region, Further, a gate electrode is formed even on the upper surface of the expanded insulating film.

[0021]

The operation of the present invention will be described with respect to the MOS gate semiconductor device according to the second aspect. When the cathode short region is formed by thermally diffusing impurities from the surface of the first semiconductor region, the spread of the cathode short region follows a Gaussian distribution. Therefore, if the cathode short region is formed shallow, the depth of the cathode short region and The variation in the lateral spread is small.

When the variation in the lateral spread of the cathode short region decreases, the distance between the cathode short region and the gate region near the surface of the first semiconductor region, that is, the channel length of the MOS transistor used for the turn-off operation. Variation is reduced.

Therefore, it is possible to prevent the current concentration caused by the shortened channel length and the decrease in the turn-off speed caused by the increased channel length.

Further, since the cathode short region is formed shallow, the base width of the parasitic transistor composed of the cathode short region, the first semiconductor region and the anode region is widened, and its amplification factor is lowered, so that the turn-off time is shortened. It

Further, by forming the cathode short region shallow, the base width of the parasitic transistor formed of the cathode short region, the first semiconductor region and the gate region is widened and its amplification factor is lowered, so that the semiconductor device is turned on. In this state, the carriers flowing out through the parasitic transistor are reduced, and the increase of ON resistance can be prevented.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross section of a cathode short circuit type MOS gate thyristor which is an embodiment of the present invention. In the figure, the same reference numerals as those used to describe the conventional example in FIG. 2 indicate the same parts.

That is, the n ⁻ type semiconductor region 12 (corresponding to the first semiconductor region of claims 1 and 2) is formed by epitaxial growth or the like on the upper surface of the p ⁺ type semiconductor substrate 11 which is the anode region. Then, on the surface of the n ⁻ type semiconductor region 12, the p type channel region 13 and the p type channel region 13 are formed.
^{A +} type gate region 14 (the regions 13 and 14 correspond to the second semiconductor region of claim 1) is formed, and the surface of the p type channel region 13 is selectively n ^+.
The mold cathode region 15 (corresponding to the third semiconductor region of claim 1) is formed.

Further, in the surface portion of the n ⁻ type semiconductor region 12, the p ⁺ type cathode short region 31 (the fourth semiconductor region of claim 1 is separated from the p ⁺ type gate region 14 by a distance D (channel length D). (Corresponding to the second semiconductor region of claim 2) is formed shallower than the p ⁺ type gate region 14. As an example, for the p ⁺ type gate region 14 formed to a depth of about 4 μm, the p ⁺ type cathode short region 3 is formed.
1 is formed to a depth of 1 μm or less.

The p ⁺ -type cathode short region 31 is formed, for example, by forming the p-type channel region 13 and the p ⁺ -type gate region 14 and then implanting a p-type impurity at a predetermined position on the surface of the n ⁻ -type semiconductor region 12. Then, the p-type impurity is thermally diffused. This thermal diffusion is caused by the n ⁺ type cathode region 15
It is also possible to perform thermal diffusion simultaneously to form the. That is, n is formed on a part of the surface of the p-type channel region 13.
After implanting the type impurities, p-type impurities are implanted at a predetermined position on the surface of the n ⁻ type semiconductor region 12, or impurities are implanted in the reverse order, and the impurities are diffused in the same step.

The depth of the p ⁺ type cathode short region 31 and the lateral expansion thereof are appropriately determined by the impurity concentration of the n ⁻ type semiconductor region 12, the amount of p type impurities implanted into the surface, the diffusion time, the diffusion temperature and the like. Can be adjusted by setting to, but its spread follows a Gaussian distribution. Therefore, for example, by setting the diffusion temperature low and the diffusion time short, p
^{If the +} type cathode short region 31 is formed shallowly, p ⁺
Variations in the depth and lateral spread of the mold cathode short region 31 are reduced.

As a result, the variation in the distance between the p ⁺ type gate region 14 and the p ⁺ type cathode short region 31 near the surface of the n ⁻ type semiconductor region 12 becomes small. In other words, the variation in the channel length of the MOS transistors included in each of the thyristor cells forming the cathode short circuit type MOS gate thyristor becomes small.

The formation of the oxide film, the electrodes, etc. is the same as the structure described with reference to FIG. That is, the silicon oxide film 17 is formed on the upper surface of the n ⁻ type semiconductor region 12 in which the above region is formed, and the n ⁺ type cathode region 15 and the p ⁺ type cathode region 15 in which the silicon oxide film 17 is selectively removed are formed. A cathode electrode 18 and a cathode short-circuit electrode 19 are formed so as to be connected to the respective surfaces of the cathode short-circuit region 31, and these electrodes are electrically short-circuited. Further, on the surface of the silicon oxide film 17, n between the p ⁺ type gate region 14 and the p ⁺ type cathode short region 31 is formed.
^A gate electrode 20 is formed on the ⁻ type semiconductor region 12 so as to extend from the upper part of the p ⁺ type gate region 14 to the end of the p ⁺ type cathode short region 31. An anode electrode 21 is uniformly formed on the lower surface of the p ⁺ type semiconductor substrate 11.

The operation of the cathode short circuit type MOS gate thyristor having the above structure is the same as that of the conventional one described with reference to FIG. 2. A positive voltage is applied to the gate to turn it on, and a negative voltage is applied to the gate. Is turned off by applying.

At turn-off, the p ⁺ type gate region 14
A p-channel is formed in the vicinity of the surface of the n ⁻ type semiconductor region 12 between the n ⁻ type semiconductor region 12 and the p ⁺ type cathode short region 31, and the excess in the n ⁻ type semiconductor region 12 and the p ⁺ type gate region 14 is provided via the p channel. Since the carriers are swept out to the cathode terminal, when the channel length becomes shorter, the resistance value of the channel becomes smaller and the carrier flow concentrates at the channel.

However, in the MOS gate thyristor of this embodiment, since the variation of the channel length D among the thyristor cells is small, current concentration caused by the shortening of the channel length D is less likely to occur and the breakdown resistance at turn-off is reduced. Get higher

When the channel length D becomes long, the resistance value of the channel becomes large, and the turn-off time of the thyristor cell having the channel becomes long, but in the MOS gate thyristor of this embodiment, the channel of each thyristor cell is increased. Since the variation of the length D is small, it is possible to prevent the turn-off characteristic from deteriorating.

Further, the p ⁺ type cathode short region 31
By forming shallow, the width of the n ⁻ type semiconductor region 12 between the p ⁺ type cathode short region 31 and the p ⁺ type semiconductor substrate 11 is widened. Therefore, the base width of the parasitic pnp transistor including the p ⁺ -type cathode short region 31, the n ⁻ -type semiconductor region 12, and the p ⁺ -type semiconductor substrate 11 is widened, and the amplification factor thereof is lowered. Done in time, the turn-off time is shorter.

By the way, in the ON state (latch-up state) of the MOS gate thyristor of this embodiment, the main current flows between the anode and the cathode, but some of the carriers flowing out from the p ⁺ type semiconductor substrate 11 are p ^+. The cathode terminal is reached via the parasitic pnp transistor formed of the type gate region 14, the n ⁻ type semiconductor region 12, and the p ⁺ type cathode short region 31. The larger the current flowing through this parasitic pnp transistor, the higher the on-resistance of the thyristor.

However, in the MOS gate thyristor of this embodiment, the p ⁺ type cathode short region 31 is shallowly formed. Therefore, from the p ⁺ type gate region 14 to p ⁺
The path E through which carriers pass to the type cathode short region 31 becomes longer than that in the conventional case (represented by E ′), that is, the base width of the parasitic pnp transistor is widened, and the amplification factor of the parasitic pnp transistor is increased. Becomes smaller. Therefore, the current flowing through this parasitic pnp transistor becomes small, and the n ⁺ type cathode region 15
Since it is possible to suppress the decrease in the main current that reaches, it is possible to prevent the on-resistance of the thyristor from increasing.

Although the p ⁺ type cathode short region 31 is formed to a depth of 1 μm or less in the above embodiment, the present invention uses the p ⁺ type cathode short region 31 as a conventional one ( Conventionally, since the p ⁺ type gate region 14 is formed in the same step, the p ⁺ type cathode short region 31 and the p ⁺ type gate region 14 are formed at the same depth. Including all.

Although the MOS gate thyristor has been described as the above embodiment, the present invention is not limited to this. For example, an n ⁺ type semiconductor substrate is used instead of the p ⁺ type semiconductor substrate 11. It can also be applied to transistor structures.

[0042]

As described above, in the MOS gate semiconductor device of the present invention, since the cathode short region is formed shallow, the variation in the spread of the cathode short region is small, and the MOS transistor for sweeping out excess carriers at turn-off is provided. Since the variation in the channel length is small, the current concentration caused by the shortened channel length is unlikely to occur, and the breakdown resistance at turn-off is increased. Further, it is possible to prevent the turn-off speed from being lowered due to the increase in the channel length.

Furthermore, by forming the cathode short region shallow, the base width of the parasitic transistor becomes wider and its amplification factor becomes smaller, so that the current flowing out through the parasitic transistor is small and the increase in the on-resistance is prevented. be able to. Therefore, it is useful for improving the efficiency of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a cathode short circuit type MOS gate thyristor taken as an example of the present invention.

FIG. 2 is a cross-sectional view of a conventional cathode short circuit type MOS gate thyristor.

[Explanation of symbols]

11 p ⁺ type semiconductor substrate (anode region) 12 n ⁻ type semiconductor region 13 p type channel region 14 p ⁺ type gate region 15 n ⁺ type cathode region 17 silicon oxide film 18 cathode electrode 19 cathode shorting electrode 20 gate electrode 21 anode Electrode 31 p ⁺ type cathode short circuit area

Claims (3)

[Claims] 1. A second semiconductor region of the second conductivity type is selectively formed on a surface portion of the first semiconductor region of the first conductivity type, and the first conductivity type is formed on a surface portion of the second semiconductor region. A third semiconductor region of the mold is selectively formed, and the second semiconductor region is spaced apart from the second semiconductor region by a predetermined distance on the surface of the first semiconductor region.
A fourth semiconductor region of the second conductivity type is formed shallower than the second semiconductor region, and electrically connects the third semiconductor region and the fourth semiconductor region to each other. A semiconductor device, wherein an insulating film is formed on a surface of the first semiconductor region between the insulating film and the fourth semiconductor region, and an electrode is provided on the insulating film. 2. A channel region of the second conductivity type is selectively formed on the surface of the first semiconductor region of the first conductivity type, and the channel region is surrounded by the surface of the first semiconductor region. A second conductivity type gate region is formed, a first conductivity type cathode region is selectively formed on a surface portion in the channel region, and a predetermined space is provided from the gate region on the surface portion of the first semiconductor region. A second conductive type second semiconductor region shallower than the gate region is formed, and a second conductive type anode region is formed on the lower surface of the first semiconductor region, and the cathode region and the second region are formed. A semiconductor region is electrically connected, an insulating film is formed on the surface of the first semiconductor region between the gate region and the second semiconductor region, and a gate electrode is provided on the insulating film. A semiconductor device characterized by the above. 3. The semiconductor device according to claim 2, wherein the insulating film is formed up to the upper part of the gate region, and a gate electrode is formed up to the upper surface of the insulating film.