JPH07129425A - Reboot processing method - Google Patents

Abstract

(57) [Summary] [Purpose] When an irreparable failure occurs due to the main processor, the main processor is restarted without requiring any key operation by the operator and without lowering the system operation rate. A failure detecting means for detecting an unrepairable failure by a main processor, a failure notifying means for notifying a failure detected by the failure detecting means, and a main processor of the main processor based on the notification from the failure notifying means. A sub-processor that executes the restart processing is provided, and the main processor is restarted by the sub-processor for an unrecoverable failure of the main processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reboot processing method for an electronic computer system, and more particularly to a reboot processing method when an unrepairable failure occurs by a main processor.

[0002]

2. Description of the Related Art Conventionally, when a system restarting process (rebooting process) is generally required when a failure occurs in an electronic computer system (hereinafter referred to as a system), it is disclosed in Japanese Patent Laid-Open No. 3-259314. As a technique, a method of selectively restarting software by an operator's key operation is known.

Further, Japanese Patent Laid-Open No. 4-171517 discloses a technique for detecting a software failure of a system by a hardware circuit, forcibly turning off / on the power of the system, and restarting the system. Has been done.

[0004]

However, in the former case of the prior art, there is a problem that the key operation by the operator is required every time a failure occurs, and the operator must be on standby at all times.

In the latter method, the power supply is always turned off / on even if the software fault can be repaired by the main processor, and the system operation rate is lowered.

An object of the present invention is to reboot a main processor when an unrepairable failure occurs by the main processor, without requiring a key operation by an operator and without lowering the operating rate of the system. It is to provide a processing method.

[0007]

In order to achieve the above object, the present invention provides a failure detecting means for detecting an unrepairable failure by the main processor in an electronic computer system having a main processor, and the failure detecting means. A failure notification means for notifying a failure detected by the sub-processor, and a sub-processor for executing a restart process of the main processor based on the notification from the failure notification means,
The main processor is restarted by the sub-processor for the unrepairable failure of the main processor.

Further, the sub-processor is configured to retry when the main processor fails to restart.

Further, the sub-processor is to retry by turning off / on the main power supply for supplying the power supply voltage to the main processor.

[0010]

According to the above means, when an unrepairable failure occurs by the main processor, this failure is detected by the failure detection means and notified by the failure notification means.

Then, based on this notification, the sub processor executes the restart process of the main processor.

Further, the sub-processor retries when the main processor fails to restart.

Further, the sub-processor retries by cutting / turning on the main power supply for supplying the power supply voltage to the main processor.

Thus, when an unrecoverable failure occurs by the main processor, the sub processor ensures that the main processor is restarted.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of an electronic computer system to which the present invention is applied. Figure 1
In, the hardware is configured by a portion that operates on the main power supply 1 (hereinafter referred to as the main power supply operation unit 100) and a portion that operates on the auxiliary power supply 2 (hereinafter referred to as the auxiliary power supply operation unit 200).

The main power supply operating unit 100 comprises a main processor 3 for performing various processes, a main memory 4 for operating a UNIX program 5, and a system control unit 7 for controlling the interface between the main processor 3 and the main memory 4. .

Further, the system control unit 7 is connected to a system disk 6 in which a UNIX program 5 is stored via a system bus 9, and via a local bus 10a,
Boot RO that stores a program that performs system startup processing and processing that depends on system hardware
Sub processor 13 by M8 and interrupt signal 12
Is connected to the sub-processor interrupt circuit 11 for generating the interrupt.

The sub-processor interrupt circuit 11 has an INT_REG 20a as a register, and the main processor 3 tells the sub-processor 13 the main power supply operating unit 1
When a process related to power control of 00 is requested, an interrupt can be generated by writing "1" in "bit 0" of INT_REG 20a of the register and transmitting the interrupt signal 12.

The auxiliary power supply operation unit 200 is connected to the sub processor 13 for controlling / monitoring the main processor 3 via the local bus 10b, and comprises a ROM 14 for storing a control program for the sub processor 13.

A power / reset controller 15, a shared memory 16, and a panel controller 19 are connected to the local bus 10b.

The power / reset control unit 15 sets / cancels the reset signal 17 and resets the main processor 3 according to an instruction from the sub-processor 13 and also turns off / turns off the power.
The main signal 1 is controlled by the closing signal 18.

The shared memory 16 includes the main processor 3,
Writing and reading are possible from both the sub-processor 13 and the sub-processor 13, and it provides a place for information exchange between the processors.

FIG. 6 is a diagram showing the memory allocation of the shared memory. 6, INT_REQ 600, which is an area for managing an interrupt request from the main processor 3 to the sub processor 13, and the main processor 3
CPU_STAT, which is the area for managing the startup status of
The E601 and the like are held in the memory.

The contents of INT_REQ 600 include a power-off request (0x00) 602 for turning off the main power supply 1 of the main power supply operating unit 100, a reset request (0x01) 603 for "resetting" the main processor 3, and a main processor. 3 is a reboot request (0x02) 604 requesting "restart".

When the interrupt from the main processor 3 occurs, the sub processor 13 refers to the contents of INT_REQ 600, recognizes the request, and performs a process satisfying the request.

The contents of CPU_STATE 601 include system start-up processing start (0x00) 605, system start-up processing in progress (0x01) 606, system start-up processing failure (0x02) 607, and system start-up processing normal end (0xFF). There are 608 and the like.

The sub-processor 13 is CPU_STAT.
By referring to the contents of E601, the execution state of the system startup processing of the main processor 3 is grasped.

The panel control unit 19 uses PNL as a register.
_REG 20b, which reads the pressing status of the power on / off switch on the system panel by the operator.

In the PNL_REG 20b, "bit 0" means a power-on switch, "bit 1" means a power-off switch, and "bit 2" means an alarm switch.

For example, when the power-on button on the system panel is pressed by the operator at system startup, the panel control unit 19 causes the register PNL_REG 20 to operate.
Set "1" to "bit 0" of b.

The sub-processor 13 periodically refers to the register. When "1" is set in the "bit 0" of the register PNL_REG 20b, the sub-processor 13 recognizes that the operator has instructed the power-on through the system panel and power-on. The signal 18 turns on the main power supply 1.

Next, the operation of the hardware according to the present invention will be described by taking the startup process of the main processor 3 as an example.

The hardware to which the present invention is applied operates when the auxiliary power supply 2 is "on". When the system is powered on by the operator pressing the power-on button (not shown) on the system panel, the panel control unit 19 sets "1" to "bit 0" of the register PNL_REG 20b.

The sub processor 13 uses the register PNL_R.
When "1" is set in "bit 0" of the EG 20b, the main power supply 1 is turned on by the power-on signal 18 via the power / reset control unit 15, and the reset signal 17 is set / released. The operation of the main processor 3 is started.

When the main processor 3 starts its operation,
The system start-up processing program stored in the boot ROM 8 is executed, processing such as diagnosis / initialization of the main memory 4 is performed, the UNIX program 5 is read from the system disk 6 and expanded in the main memory 4, and the UNIX
The program execution right is passed to the program 5.

Next, the operation when a failure occurs in the computer system having the above hardware configuration will be described below.

First, a failure occurs, which is caused by software on the main processor 3 (boot ROM in this embodiment).
8), which is realized by a program that performs processing dependent on the hardware in 8) and notifies to the sub-processor 13 will be described with reference to FIG.

FIG. 2 is a flow chart showing a processing procedure when a failure occurs according to the present invention.

In FIG. 2, first, when a failure occurs,
The software on the main processor 3 analyzes and logs the failure (S201). And step 20
It is determined whether the system control processing of the main processor 3 can be continued based on the analysis in 1 (S20).
2) If it is possible to continue (S202: Yes), the process proceeds to step 205 to continue the system control process.

When it is not possible to continue (S202: No),
It is determined whether the failure can be repaired (S203). If the restoration is possible (S203: Yes), the restoration processing is performed (S204), and the system control processing is continued (S20).
5).

If the data cannot be restored (S203: No),
The software on the main processor 3 requests the sub-processor 13 to restart the system. This writes a reboot request (0x02) 604, which is a code for requesting system restart, in the INT_REQ 600 in the shared memory 16 (S206).

Next, "1" is set in "bit 0" of the register INT_REG 20a in the sub-processor interrupt circuit 11.
Is written (S207) and the interrupt signal 12 is generated to interrupt the sub-processor 13.

After that, the main processor 3 is in an infinite loop until it is reset by the sub processor 13 again.

Next, the interrupt processing of the sub processor 13 which receives the interrupt by the main processor 3 will be described with reference to FIG.

FIG. 3 is a flowchart showing a processing procedure at the time of interruption by the sub processor of the embodiment.

In FIG. 3, a program for controlling the sub processor 13 is stored in the ROM 14, and when an interrupt is received from the main processor 3, the INT_REQ 600 in the shared memory 16 is referred to and the main processor 3 is referred to.
The content of the interrupt request from is grasped (S301).

In step 301, the interrupt request is a power-off request (0x00) 6 for turning off the main power source 1 (6).
It is determined whether the value is 02 or not, and a power-off request (0x0
0) 602 (S301: Yes), the power-off processing routine is activated (S302), and the interrupt processing ends (S303).

If it is not the power off request (0x00) 602 (S301: No), it is determined whether the interrupt request is the reset request (0x01) 603 of the main processor 3 (S304).

If it is the reset request (0x01) 603 (S304: Yes), the main processor reset processing routine is started (S305), and the interrupt processing is ended (S306).

If it is not the reset request (0x01) 603 (S304: No), it is judged whether the interrupt request is a system restart request, that is, a reboot request (0x02) 604 (S307).

If it is the reboot request (0x02) 604 (S307: Yes), the reboot processing routine is activated (S308) and the interrupt processing is ended (S309).

Thereafter, these processes are repeated according to the contents of the interrupt request. In this embodiment, INT_REQ60
Since the reboot request (0x02) 604 is written in the code 0 by the main processor 3, the reboot processing routine is started.

Next, the system restart processing executed by the control program on the sub processor 13 and the system startup processing executed by the main processor 3 will be described with reference to FIGS. 4 and 5.

FIG. 4 is a flow chart showing the processing procedure when the system is started up according to the embodiment.

In FIG. 4, the control program on the sub-processor 13 is a variable retry_co which is a variable indicating the number of retries when the reboot processing routine is started.
unt is set to 4 (S400).

Then, a timer for monitoring the state of the main processor 3 is set. In this embodiment, "10,000" is set in timer1 which is a timer for monitoring whether the main processor 3 operates normally, and the UNIX program 5 is normally loaded from the system disk 6 to the main memory 4. "600" is set to timer2, which is a timer for monitoring whether or not it has reached (S401).

Next, the sub-processor 13 writes the system start-up processing start (0x00) 605 as a code in the CPU_STATE 601 of the shared memory 16 (S402), and the power / reset control unit 15 transmits the reset signal 17. Then, the main processor 3 is reset, the operation is started, and the system start-up process is started (S403).

The control program on the sub processor 13 waits for 1 millisecond after starting the operation of the main processor 3 in step 403 (S404).

Next, the sub processor 13 uses the CPU_ST
The ATE 601 is being monitored, the main processor 3 has started normal operation, and the CPU_STATE 601 is executing the system startup processing as a code “0x01” 60
When 6 is written (S405: Yes), the control program on the sub-processor 13 recognizes that the main processor 3 has started the system startup processing, and waits for 1 second (S406).

Then, during this wait, the main processor 3 normally terminates the system startup processing, and writes the system startup normal termination (0xFF) 608 as a code to the CPU_STATE 601 (S407: Yes). Recognize that the system has started up normally and terminate the reboot process normally.

Next, the operation of the hardware when some trouble occurs in the system during the above processing will be described.

First, the processing when the software on the main processor 3 is faulty and cannot be repaired by the main processor 3 will be described.

The control program on the sub processor 13 monitors the CPU_STATE 601, and as a code, "0x01" 60 during system startup processing is being executed.
When 6 is not written (S405: No), time
Decrement r1 (S408).

Then, it is determined whether or not timer1 has become "0" (S409). If timer1 is not "0" (S409: No), the procedure returns to step 404 and 1
After waiting for a millisecond, the process proceeds to step 405 and the CPU
Continue monitoring _STATE 601.

The above processing is repeated until timer1 becomes "0", and CPU_STAT is exceeded even if the monitoring time set in timer1 (10 seconds in this embodiment) is exceeded.
If the value of E601 is not updated, it is timed out in step 409, it is recognized that the software on the main processor 3 has a failure, and step 410 is executed.
Go to.

In step 410, the retry count is decremented and it is determined whether or not retry_count is "0" (S411).

If retry_count is not "0" (S411: No), retry is performed for the number of times of retry_count. At this time, the sub processor 13
The above control program disconnects the main power supply 1 by the power supply disconnection signal 18 via the power supply / reset control unit 15 (S4).
12), turn on the main power supply 1 (S413), and step 40
Returning to 1, the startup process of the main processor 3 is restarted.

In the above processing, retry_count is 0.
Is repeated until it becomes "retry_c" at step 411.
When the count reaches “0”, it is recognized that the system restart processing has failed (S411: Yes),
Reboot processing is terminated abnormally.

On the other hand, in step 407, the control program on the sub-processor 13 is CPU_STATE.
When 601 is being monitored and the system startup processing normal end (0xFF) 608 is not written as a code (S407: NO), the process proceeds to step 414.

If the system start-up processing abnormal end (0x02) is written in the CPU_STATE 601 by the main processor 3 as a code (S
414: Yes), the control program on the sub-processor 13 recognizes that the main processor 3 has failed in the system start-up process, and proceeds to step 410 to retry.

In step 410, retry_cou
Decrement nt and retry until retry_count becomes "0".

At this time, as a retry method, the main power source 1 is turned off by the power source disconnection signal 18 (S412), the main power source 1 is turned on by the power source on signal 18 (S413), and the process returns to step 401 to start the system. To start again.

In step 414, CPU_
When the system startup processing abnormal end (0x02) is not written in STATE 601 as a code (S
414 :: No), and timer2 is decremented (S415).

Then, it is determined whether timer2 has become "0" (S416). If timer2 is not “0” (S416: No), the procedure returns to step 406,
After waiting for 1 second, the process proceeds to step 407 and CPU_
Continue monitoring STATE 601.

The above processing is repeated until timer2 becomes "0", and CPU_STATE is exceeded even if the monitoring time set in timer2 (10 minutes in this embodiment) is exceeded.
If the value of 601 is not updated, it is timed out in step 416, it is recognized that the system startup processing is not normally performed, the process proceeds to step 410, and the retry is performed as described above.

Next, a case where the system startup processing by the main processor 3 is not normally completed will be described.

FIG. 5 is a flow chart showing the processing procedure at the time of startup by the main processor.

In FIG. 5 (step 40 in FIG. 4)
5) When the main processor 3 starts operating normally,
The system startup process execution (0x01) 606 is written in the CPU_STATE 601 as a code, and the system startup process is executed (S500).

Next, the main processor 3 loads the UNIX program 5 from the system disk 6 into the main memory 4
(S501).

Then, it is determined whether or not the processing in step 501 has been normally completed (S502), and if it is normally completed (S502: Yes), CPU_STATE 601
Then, as a code, the system startup process ends normally (0
xFF) 608 is written (S503), and the system startup processing is ended.

At step 501, the system disk 6
If the UNIX program 5 is not normally loaded from the computer (S502: No), the main processor 3
The system startup processing abnormal end (0x02) 607 is written as a code in U_STATE 601 (S50
4) Recognize that the system startup processing has terminated abnormally.

As described above, according to this embodiment, the following can be achieved.

That is, in the computer system including the main processor 3 for performing various processes and the sub-processor 13 for controlling / monitoring it, (1) If a system failure occurs, boot it
When the software on the main processor 3 stored in the OM 8 detects the notification, the sub processor 13 is notified, and the sub processor 13 receiving the notification can control the restart of the system.

(2) The sub-processor 13 controls the restart of the system, so that the restart of the system can be performed even when the unrepairable failure by the main processor 3 occurs. .

(3) When the system restart is unsuccessful, the system restart process can be surely performed by performing the retry by disconnecting / turning on the main power supply 1.

(4) As a method for restarting the system,
First, the power supply / reset control unit 15 sends a reset signal 17 to reset and start the main processor 3 without turning off / on the main power supply 1. It can be shortened.

Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to this, and can be realized by other methods.

For example, as another embodiment, the control program of the sub processor 13 in FIG. 4 is changed as follows.

The main power source 1 OFF / ON process in steps 412 and 413 is performed after the timer is set in step 401, and if the number of retries is not "0" in step 411, the process returns to step 412.

By doing so, the system restart at the occurrence of a failure and the retry at the failure of restart can always be made by cutting off / on the main power supply 1, and the main power supply operation unit. It is possible to more reliably carry out the restarting process.

[0092]

As described above, according to the present invention, in an electronic computer system having a main processor,
Failure detection means for detecting an unrepairable failure by the main processor, failure notification means for notifying the failure detected by the failure detection means, and restart of the main processor based on the notification from the failure notification means Since a sub-processor that executes the raising process is provided and the main processor is restarted by the sub-processor for the unrecoverable failure of the main processor, the key operation by the operator is not required and the operator does not need to be always on standby. There is an effect.

Further, since the sub-processor retries when the main processor fails to restart, the restarting process of the main processor is surely executed.

Further, since the sub processor retries by cutting / turning on the main power supply for supplying the power supply voltage to the main processor, the restarting process of the main processor is executed more reliably.

As a result, the restart process is executed only when an unrepairable failure occurs by the main processor, so that there is no effect that the operating rate of the computer system will not be lowered due to unnecessary disconnection of the main power supply. is there.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a block configuration of an embodiment of an electronic computer system to which the present invention is applied.

FIG. 2 is a flow chart showing a processing procedure at the time of failure notification of the main processor of the embodiment.

FIG. 3 is a flowchart showing a processing procedure at the time of interruption by the sub processor of the embodiment.

FIG. 4 is a flowchart showing a processing procedure at the time of restarting by the sub processor of the embodiment.

FIG. 5 is a flowchart showing a processing procedure when the main processor of the embodiment is started up.

FIG. 6 is a diagram showing allocation in a shared memory according to an embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main power supply of computer system, 2 ... Auxiliary power supply of computer system, 3 ... Main processor, 4 ... Main memory, 5 ... UNIX program, 6 ... System disk, 7 ... System control part, 8 ... Boot ROM, 9 System bus, 10 Local bus, 11 Sub processor interrupt circuit, 12 Interrupt signal, 13 Sub processor, 14 ROM, 15 Power supply / reset control unit, 16
... Shared memory 17 ... Reset signal, 18 ... Power off / on signal, 19
... Panel control unit, 20 ... Register, 100 ... Main power supply operating unit, 200 ... Auxiliary power supply operating unit.

Claims (3)

[Claims] 1. An electronic computer system having a main processor, failure detecting means for detecting an unrepairable failure by the main processor, failure notifying means for notifying a failure detected by the failure detecting means, and the failure. It is characterized in that a sub-processor for executing the restart processing of the main processor is provided based on the notification from the notification means, and the main processor is restarted by the sub-processor for an unrepairable failure of the main processor. Reboot processing method. 2. The reboot processing method according to claim 1, wherein the sub-processor retries when the main processor fails to restart. 3. The reboot processing method according to claim 1, wherein the sub-processor performs a retry by turning off / on a main power supply for supplying a power supply voltage to the main processor.