JPH07120638B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming a wiring layer for wiring a circuit element provided on a semiconductor layer on an insulator. It is a thing.

[Conventional technology]

Thick 1000 Å on the insulator to improve the performance of semiconductor devices
An attempt has been made to provide a semiconductor single crystal layer of about (= 0.1 μm) and to manufacture a circuit element composed of a MOS transistor (hereinafter referred to as a thin film transistor) or the like on the semiconductor single crystal layer.

In addition, there is a demand for heat resistant wiring for this thin film transistor, and wiring made of a compound with a refractory metal such as titanium (Ti) or a semiconductor has been developed.

2 (a) to 2 (e) are step-by-step sectional views showing a conventional method for forming a heat-resistant wiring of a thin film transistor, which will be described below with reference to the drawings.

In FIG. 2 (a), 1 is a single crystal silicon substrate, 2 is a silicon dioxide film (SiO ₂ , hereinafter referred to as an oxide film), and its thickness is
It is 0.5 μm to 1 μm. Reference numeral 3 is a single crystal silicon film having a thickness of 1000Å. Structures 1 to 3 are so-called SOI (Silicon O
n Insulator) structure, SIMOX (Separati
on by IMplanted OXygen) method or laser recrystallization method. Reference numeral 4 is a gate electrode made of polycrystalline silicon heavily doped with phosphorus, 5 is an oxide film, and 6 is a contact which is opened on the oxide film 5 and reaches the single crystal silicon 3.

Next, as shown in FIG. 2B, 1000 Å of polycrystalline silicon 7 is deposited in the region including the contact 6 where the heat resistant wiring is to be formed. Then, as shown in FIG. 2 (c), titanium 8 is deposited on the entire surface by sputtering to a thickness of 700 Å.
After that, lamp annealing is performed for 1 minute in a N ₂ atmosphere at 700 ° C. to react titanium 8 with polycrystalline silicon 7 to form titanium silicide (TiSi ₂ ).

Next, it is soaked in a sulfuric acid solution to remove unreacted titanium (titanium on the oxide film 5). Further, in order to completely react and combine the polycrystalline silicon 7 and the titanium 8, a lamp anneal is performed in an N ₂ atmosphere at 800 ° C. for 1 minute to form a titanium silicide 9
2D is formed.

First, as shown in FIG. 2 (e), the interlayer insulating film
10, M with aluminum wiring 11 formed and heat resistant wiring
An OS transistor is formed on the insulator. Here, the heat resistant wiring is used as a bit line of a MOS type memory element or a wiring of a three-dimensional circuit element in which the thin film transistors are laminated in multiple layers.

[Problems to be Solved by the Invention]

In such a heat resistant wiring of a thin film transistor, since the specific resistance of the polycrystalline silicon 3 is very large, in order to reduce the contact resistance between the wiring 9 and the single crystal silicon layer 3, the polycrystalline silicon layer 3 is completely removed. Therefore, if the amount of titanium is small, the resistance cannot be reduced.

On the other hand, from such requirements, if the film thickness of titanium 8 is made thicker than the film thickness of the polycrystalline silicon 7 equivalent to the chemical equivalent for forming titanium silicide, and the amount of titanium is increased,
Titanium is oversupplied in the silicidation reaction, and a phenomenon occurs in which silicon atoms are sucked up at the contact portion with the single crystal silicon 3. Since the single crystal silicon 3 is formed on the insulator and its film thickness is as thin as 1000Å, it is impossible to supply silicon atoms infinitely because of titanium silicide formation. In this case, as shown in FIG. As shown in the enlarged cross-sectional view of the contact portion, the high resistance region 12 made of low density silicon atoms is formed in the contact portion.
Will occur.

Therefore, in the conventional manufacturing method, in order to form a contact portion having low resistance, it is necessary to deposit the amount of titanium and the amount of polycrystalline silicon so that they are chemically equivalent to each other. This is impossible, and there is a problem that the contact portion has a high resistance regardless of whether the amount of titanium is large or small as described above.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a method of manufacturing a semiconductor device capable of forming a heat resistant wiring that does not include a high resistance region on a thin film transistor.

[Means for Solving the Problems]

According to the method of manufacturing a semiconductor device of the present invention, a first non-single-crystal semiconductor layer, a refractory metal layer, and a second non-single-crystal semiconductor are provided in a wiring formation region on a semiconductor active layer formed on an insulator. After sequentially forming the layers, the first and second semiconductor layers and the refractory metal layer are combined to form a wiring layer, and the first semiconductor layer, the refractory metal layer, and When the second semiconductor layers are sequentially formed, the layer thicknesses of the respective layers are adjusted so that the first semiconductor layer has a high melting point in the step of combining the first and second semiconductor layers with the high melting point metal layer. The layer thickness is such that it combines with the metal layer and the semiconductor active layer does not combine with the refractory metal layer.

[Action]

In the present invention, after the first non-single-crystal semiconductor layer, the refractory metal layer, and the second non-single-crystal semiconductor layer are sequentially formed in the wiring formation region on the semiconductor active layer formed on the insulator, A wiring layer is formed by combining the first and second semiconductor layers and the refractory metal layer, and the first semiconductor layer, the refractory metal layer, and the second semiconductor layer are formed. In the step of combining the first and second semiconductor layers with the refractory metal layer, the first semiconductor layer is completely combined with the refractory metal layer when the layers are sequentially formed, Moreover, since the semiconductor active layer has a layer thickness that does not combine with the refractory metal layer, the non-single-crystal semiconductor layer in contact with the active layer is completely combined with the refractory metal and constitutes the active layer. Realization of low resistance heat resistant wiring in which atoms are prevented from combining with refractory metals Wear.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that in the description of this embodiment, the description overlapping with the description of the conventional technique will be appropriately omitted.

FIG. 1 (a) shows the structure shown in FIG. 2 (a), in which a polycrystalline silicon 71 having a thickness of 300 Å, a titanium 81 having a thickness of 700 Å, and a polycrystalline silicon 72 having a thickness of 1000 Å are sequentially formed on the entire surface. It has been deposited.

Thereafter, as shown in FIG. 1B, the polycrystalline silicon 71, 72 and titanium 81 are removed by etching leaving a wiring region. This etching is performed by the reactive ion etching method using CF ₄ as a main component of etching gas.

After that, for silicidation reaction, lamp annealing is performed in an N ₂ atmosphere at 800 ° C. for 1 minute to react titanium and silicon, and unreacted on the titanium silicide 91 as shown in FIG. 1 (c). A structure in which the polycrystalline silicon 73 remains is obtained. After that, the unreacted polycrystalline silicon layer 73 is removed, and aluminum wiring is formed thereover via the insulating film 10 by the same method as the conventional method shown in FIG. 2 (d) to complete the circuit element. .

In this embodiment, since the film thickness of the polycrystalline silicon 71 under the titanium 81 is half or less than the film thickness (1000Å) necessary for forming titanium silicide, the single crystal silicon 3 and the titanium silicide 91 are formed. The polycrystalline silicon does not remain in the contact portion 6 of the above, and the silicidation reaction is rapidly performed to the upper portion where the polycrystalline silicon 72 including the crystal grain boundary having a higher atomic transfer rate inside the single crystal silicon 3 exists. Therefore, the silicon atoms in the single crystal silicon 3 are not sucked up due to the silicidation reaction, the high resistance region is not formed, and the resistance of the contact portion can be reduced. In addition, since it is not necessary to deposit the amount of titanium and the amount of polycrystalline silicon in a stoichiometrically equivalent amount as in the conventional case, the process can be simplified.

Although polycrystalline silicon is used as the non-single-crystal semiconductor layer in the above-mentioned embodiments, an amorphous semiconductor layer may be used.

In addition, although titanium was used as the refractory metal,
This may be a refractory metal other than titanium as long as it is a refractory metal capable of forming a stable compound with a semiconductor, and in this case, the same effect as that of the above-described embodiment can be obtained.

〔The invention's effect〕

As described above, according to the present invention, the first non-single-crystal semiconductor layer, the refractory metal layer, and the second non-single-crystal semiconductor are provided in the wiring formation region on the semiconductor active layer formed on the insulator. After sequentially forming the layers, the first and second semiconductor layers and the refractory metal layer are combined to form a wiring layer, and the first semiconductor layer, the refractory metal layer, and When the second semiconductor layers are sequentially formed, the layer thicknesses of the respective layers are adjusted so that the first semiconductor layer has a high melting point in the step of combining the first and second semiconductor layers with the high melting point metal layer. Combined with the metal layer, and, since the semiconductor active layer has a layer thickness so as not to combine with the refractory metal layer, the non-single crystal semiconductor layer in contact with the active layer is completely combined with the refractory metal, In addition, it is possible to suppress the combination of the atoms that make up the active layer with refractory metals, and have low resistance and heat resistance. There is an effect that wiring can be realized.

[Brief description of drawings]

1 (a) to 1 (c) are sectional views for explaining the method of manufacturing a semiconductor device according to an embodiment of the present invention by step,
FIGS. 3A to 3E are cross-sectional views by step showing a method for manufacturing a conventional semiconductor device, and FIG. 3 is an enlarged cross-sectional view of a contact portion of a conventional semiconductor device. In the figure, 1 is a single crystal silicon substrate, 2 is an oxide film, 3
Is a single crystal silicon layer, 4 is a gate electrode, 5 is an oxide film, 6
Are contacts, 71, 72, 73 are polycrystalline silicon, 81 is titanium, and 91 is titanium silicide. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuro Inoue, 4-chome, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSE Research Laboratory (72) Tadashi Nishimura 4-chome, Mizuhara, Itami City, Hyogo Prefecture Address Mitsubishi Electric Co., Ltd. LSI Research Institute (56) Reference JP-A-61-230373 (JP, A) JP-A-62-166568 (JP, A)

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a semiconductor active layer formed on an insulator, comprising: a first step of forming a non-single-crystal first semiconductor layer in a wiring formation region on the semiconductor active layer. A second step of forming a refractory metal layer on the first semiconductor layer, a third step of forming a non-single-crystal second semiconductor layer on the refractory metal layer, A first semiconductor layer formed by the first to third steps, including a first step of forming a wiring layer by combining a second semiconductor layer and the refractory metal layer The layer thicknesses of the refractory metal layer and the second semiconductor layer are adjusted so that the first semiconductor layer is completely combined with the refractory metal layer in the fourth step, and the semiconductor active layer is A method of manufacturing a semiconductor device, wherein the layer thickness is set so as not to combine with the refractory metal layer.