JPH07115198A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a method for manufacturing a semiconductor device using a silicide electrode (wiring), which is capable of forming a local wiring by using a salicide technique. A step of selectively oxidizing the surface of a silicon semiconductor substrate to form a field oxide film, and defining a silicon surface bounded at least in part by the field oxide film, and the silicon surface and the field oxide film. Depositing a cobalt film over the cobalt film, depositing a silicon film on the cobalt film and patterning to form a silicon film pattern extending from the silicon surface onto the field oxide film; Forming a TiN film on the film, heating the substrate to cause a silicide reaction between the cobalt film and the silicon surface and between the cobalt film and the silicon film pattern, and the remaining TiN film and Co Removing the film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon semiconductor device, and more particularly to a method of manufacturing a semiconductor device using a silicide electrode (wiring).

[0002]

2. Description of the Related Art In semiconductor integrated circuits, miniaturization of constituent elements and reduction of circuit power consumption are required. To reduce power consumption, CMOS (complementary metal-oxide-semi)
conductor) circuit is advantageous. The miniaturization of the MOS transistor causes a problem of a short channel effect in which a drain current which is not controlled by the gate voltage flows due to the application of the drain voltage. Such a short channel effect is likely to occur when the depth of the source / drain regions becomes larger than the distance (channel length) between them.

In order to prevent the short channel effect, it is desirable to make the impurity diffusion regions of the source / drain regions shallow. However, if the impurity diffusion region is made shallow, the resistance of the impurity diffusion region becomes high. In order to reduce the resistance, it is effective to form a low resistance film on the surface of the impurity diffusion region. From this point of view, the silicidation technology is becoming more important.

The thickness of a silicon electrode (wiring) such as a gate electrode is not increased so much,
Lower resistance is desired and similar silicidation techniques can be applied. In particular, the silicon gate of the MOS transistor and the source / drain region can be silicidized in the same process.

5A-5C, 6A-6C, 7A-7C,
8A and 8B show an example of a method for manufacturing a MOS transistor using a conventional self-aligned silicidation (salicide) technique.

As shown in FIG. 5A, a buffer oxide film 137 and a silicon nitride (SiN _x ) film 138 are deposited on the surface of the p-type silicon substrate 121, for example. A resist mask is formed on the silicon nitride film 138, and the silicon nitride film 138 is patterned into a predetermined shape. afterwards,
The resist mask is removed. The silicon nitride film 138 functions as a shielding film against oxygen and functions as a mask in the thermal oxidation process.

As shown in FIG. 5B, the silicon substrate 121
Are heated to a high temperature and brought into contact with an oxidizing atmosphere to form a thermal oxide film 122 on the surface of the silicon substrate 121 not covered with the silicon nitride film 138. In this way, local oxidation of silicon (LOCOS) occurs outside the region masked by the silicon nitride film 138.
Oxide film is formed. Such an oxide film is usually called a field oxide film.

As shown in FIG. 5C, after the LOCOS oxidation is completed, the silicon nitride film 138 is removed and the buffer oxide film 1 is removed.
37 is also removed. After that, the gate oxide film 123 having a thickness of, for example, about 10 nm is formed again by thermal oxidation or the like.

As shown in FIG. 6A, the gate oxide film 12 is formed.
3. On the field oxide film 122, for example, a thickness of 15
The polycrystalline silicon film 124 of about 0 nm is formed by CVD (chemic
al vapor deposition).

As shown in FIG. 6B, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the deposited polycrystalline silicon film 124. When forming a p-channel MOS transistor on an n-type silicon substrate,
P-type impurities such as boron B are ion-implanted. Further, although the case where the impurities are ion-implanted after the deposition of the polycrystalline silicon film has been described, the polycrystalline silicon film doped with the impurities may be deposited. Further, when the amount of impurities in polycrystalline silicon film 124 is sufficiently increased by the subsequent ion implantation, the ion implantation step of FIG. 6B may be omitted.

As shown in FIG. 6C, the polycrystalline silicon film 1
A resist pattern is formed on the polycrystalline silicon film 124 using the resist pattern as an etching mask.
The gate oxide film 123 is etched.

The patterning of the gate electrode is carried out by reactive ion etching (RI) using Cl ₂ + O ₂ or HBr as an etching gas.
E). In this way, the silicon substrate 1
21 a gate oxide film 123 and a polycrystalline silicon film 1 on the surface
The insulated gate electrode structure formed at 24 is formed.

In the case of the LDD (lightly doped drain) structure, after forming the gate electrode structure, n-type impurities such as phosphorus or arsenic are lightly ion-implanted to form shallow n-type regions 126a and 127a. The n-type impurities are simultaneously ion-implanted into the polycrystalline silicon film 124.

As shown in FIG. 7A, a silicon oxide film 125 having a thickness of, for example, about 200 nm is deposited by CVD. As shown in FIG. 7B, the deposited silicon oxide film 125 is anisotropically etched by RIE using CF ₄ + CHF ₃ mixed gas as an etching gas. When RIE is performed until the silicon oxide film 125 on the flat surface is completely etched, the silicon oxide film 125 remains only on the side wall of the gate electrode structure. Thus, the sidewall 125 of the gate electrode is formed.

As shown in FIG. 7C, the sidewall 12
Using the gate electrode 124 formed with No. 5 as a mask, an n-type impurity of phosphorus or arsenic is ion-implanted at a higher concentration to form a source region 126 and a drain region 127.

As shown in FIG. 8A, a Ti film 128 having a thickness of, for example, about 50 nm is formed on the entire surface of the substrate 121 by sputtering or the like. The Ti film 128 includes a source region 126, a drain region 127, a polycrystalline gate electrode 1
It contacts silicon above 24, but is deposited on silicon oxide in other areas.

As shown in FIG. 8B, for example, the temperature is about 70.
Heat treatment is performed at 0 ° C. for about 30 seconds. By this heat treatment, the Ti film 128 that is in contact with silicon undergoes a silicidation reaction to become a titanium silicide film 128a.

After Ti and silicon are reacted to form titanium silicide, the substrate 121 is immersed in a mixed solution of ammonia water and hydrogen peroxide to remove the unreacted Ti film 128. Further, heat treatment is performed at a temperature of about 800 ° C. for a time of about 30 seconds to further promote the silicidation reaction. By the two-step heat treatment, Ti is formed on the surfaces of the polycrystalline silicide gate electrode 124, the source region 126, and the drain region 127.
A Si ₂ film is formed.

Titanium silicide has several phases, and the two-step heat treatment described above effectively causes T
It can be iSi ₂ . In this way, when the MOS transistor is formed on the silicon surface surrounded by the field oxide film, the silicide film can be formed in a self-aligned manner only on the gate electrode and the source / drain regions.

Usually, when a conductive pattern is formed on a semiconductor substrate and thereafter the conductive pattern is connected to other places by wiring, the surface is once covered with an insulating film, contact holes are formed, and then a wiring pattern to be connected is formed. To form.

By the way, in the case of a local interconnect which forms a wiring pattern on the field oxide film and connects the wiring pattern and the diffusion region on the substrate surface, an interlayer insulating film is formed and a contact hole is formed. If the step of opening can be omitted, it is extremely desirable in terms of miniaturization of the semiconductor device and simplification of the step.

USP 4,821,085 and 4,87
No. 3,204 discloses an example of forming such a local wiring. USP 4,821,085 discloses a method of depositing a Ti film on a substrate having a conductive region selectively exposed on the surface and heating the Ti film in a nitrogen atmosphere to silicidize the Ti film in contact with Si, A technique for simultaneously converting the surface to TiN is disclosed. Nitriding of the Ti film by nitrogen gas preferentially proceeds on the oxide film rather than on Si. A wiring layer connected to the Ti silicide film on the Si surface can be formed. After that, the TiN film is patterned to obtain a local wiring.

USP 4,873,204 forms a refractory metal film on a Si substrate in which the Si region is partially exposed, and further forms a patterned amorphous Si film thereon. After that, by performing heat treatment, Si
The Ti silicide is formed and the local wiring is formed only in the region and the region in contact with the amorphous Si pattern. According to such a local wiring technique using silicidation, it is possible to form a wiring layer which is self-alignedly connected to the exposed silicon region.

[0024]

In the above-described manufacturing method, the LD is used for the polycrystalline silicide gate electrode.
Even when the D structure is not used, the ion implantation is performed twice. Also in the case of the ion implantation shown in FIG. 6B, it is necessary to separately implant impurity ions in the n-channel MOS transistor and the p-channel MOS transistor, and a mask is required to perform each ion implantation.

If the ion implantation shown in FIG. 6B is omitted and impurities are added to the gate electrode only by the same process as the ion implantation to the source / drain regions, the following problems occur.

With the miniaturization, the depth of the source / drain region becomes about 0.1 μm (100 nm) or less. The polycrystalline silicon gate electrode needs to have a thickness of about 150 nm. If the same ion implantation and heat treatment are performed on these regions, the polycrystalline silicon gate electrode becomes insufficient and the conductivity becomes low.

Further, it is difficult to satisfactorily convert the surface of silicon doped with a high concentration of impurities into a metal silicide. Therefore, if the dose of ion implantation for forming the source / drain regions is set too high, it becomes difficult to form a silicide film on the surface of the source / drain regions thereafter.

Local wiring using the salicide technique is extremely effective for miniaturization of semiconductor devices, but the technique is not yet fully developed. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of simultaneously forming a shallow source / drain region and a polycrystalline silicon electrode (wiring) having sufficiently low conductivity.

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of forming a local wiring having good characteristics by using a salicide technique.

[0030]

According to one aspect of the present invention, a step of forming a silicon gate electrode on a substrate of a silicon semiconductor via a gate insulating film, and an exposed surface of the silicon gate electrode with an insulating film. Covering and exposing the substrate surface on both sides of the gate electrode; forming a first refractory metal film on the substrate surface; heating the substrate to form the first refractory metal film and the substrate; A step of causing a silicide reaction with the surface to form a first refractory metal silicide film; a step of removing the unreacted first refractory metal film; and a step of removing the insulating film on the gate electrode. Exposing the surface of the gate electrode, implanting impurity ions into the surface of the substrate below the gate electrode and the first refractory metal silicide film, and heating the substrate to activate the impurities. including Method of manufacturing a conductor arrangement is provided.

According to another aspect of the present invention, the surface of the silicon semiconductor substrate is selectively oxidized to form a local oxide film, and at least a part defines a silicon surface bounded by the local oxide film. Depositing a cobalt film over the silicon surface and the local oxide film,
Depositing a silicon film on the cobalt film and patterning it to form a silicon film pattern extending from the silicon surface onto the local oxide film; and forming a TiN film on the cobalt film. Heating the substrate,
A method of manufacturing a semiconductor device, comprising: performing a silicide reaction between the cobalt film and the silicon surface and between the cobalt film and the silicon film pattern; and removing a remaining TiN film and an unreacted cobalt film. Provided.

[0032]

When the refractory metal silicide film is formed on the surface of the semiconductor substrate and then the silicon gate electrode and the surface of the semiconductor substrate are ion-implanted, the ion implantation to the surface of the semiconductor substrate is carried out on the surface of the refractory metal silicide. The implantation depth becomes shallow due to the action of the film.

By depositing a cobalt film extending from the surface of the silicon substrate onto the local oxide film, forming a silicon film pattern thereon, covering the surface of the cobalt film with the TiN film, and then performing a silicidation reaction, A good silicide film can be formed on the surface of the substrate and on the local oxide film by using the cobalt film which is easily oxidized.

[0034]

EXAMPLES FIGS. 1A-1C, 2A-2C, 3A-3C and 4
A method of manufacturing a MOS transistor according to an embodiment of the present invention will be described with reference to A and 4B.

A case of forming an n-channel MOS transistor will be described as an example. As shown in FIG. 1A, a buffer oxide film 37 and a silicon nitride film 38 are formed on the surface of the p-type Si substrate 21, and the silicon nitride film 38 is patterned into a desired shape. By heating the Si substrate 21 in an oxidizing atmosphere, local oxidation is performed using the silicon nitride film 38 as a mask. A field oxide film 22 having a thickness of, for example, about 500 nm is formed by local oxidation. After the local oxidation, the silicon nitride film 38 and the buffer oxide film 3
7 is removed.

As shown in FIG. 1B, the exposed Si substrate 2
A gate oxide film 23 having a thickness of, for example, about 10 nm is formed on one surface by thermal oxidation. As shown in FIG. 1C, the field oxide film 22 is formed by chemical vapor deposition (CVD),
An amorphous silicon film 24 having a thickness of about 150 nm and a silicon nitride film 25 having a thickness of about 50 nm are uniformly deposited on the surface of the gate oxide film 23. Then, the silicon nitride film 2
A resist mask for patterning the gate electrode is formed on the layer 5. For example, the amorphous silicon film uses Si ₂ H ₆ as a source gas and has a pressure of 0.3 Torr.
The film is formed by CVD at r and a temperature of 450 ° C. The silicon nitride film uses SiHCl ₃ + NH ₃ as a source gas and has a pressure of 0.
A film is formed by CVD at 4 Torr and a temperature of 720 to 775 ° C.

As shown in FIG. 2A, the silicon nitride film 25, the amorphous silicon film 24, and the gate oxide film 23 are patterned using the resist mask as an etching mask. For example, an insulated gate electrode having a gate length of about 0.3 μm is formed by reactive ion etching using Cl ₂ + O ₂ or HBr as an etching gas.

If necessary, the insulated gate electrodes 23, 24,
Ion implantation is performed using 25 as a mask to form a lightly doped n-type region 19. The n-type region 19
Is for forming the source / drain regions of the LDD structure, and when the LDD structure is not used, this ion implantation step is omitted.

As shown in FIG. 2B, a silicon oxide film 26 having a thickness of about 80 nm is deposited by CVD. The silicon oxide film is subjected to RIE using a mixed gas of CF ₄ + CHF ₃ as an etching gas to remove the silicon oxide film on the flat surface while leaving the sidewalls 26 on the side walls of the gate electrode.

The silicon nitride film 25 on the amorphous gate electrode 24 is exposed by this RIE.
The Si substrate after RIE is treated with a dilute HF aqueous solution to remove a natural oxide film that may be generated on the surface.

As shown in FIG. 2C, a Co film 27 is deposited on the entire surface of the Si substrate 21 by sputtering, for example, with a thickness of about 10 nm. In this sputtering step, for example, Ar gas, which is a sputtering gas, is used
Flowing at 00 sccm, the pressure in the sputtering chamber is set to 0.1
Keeping at about Pa and targeting Co to about 3.7 W / cm
RF power of about ² is applied.

In this state, the surface of the Si substrate 21 is the Co film 27 at the portion which will later become the source / drain regions.
Contact with the gate electrode 24 of amorphous silicon
Are separated from the Co film 27 by the silicon nitride film 25.

As shown in FIG. 3A, the substrate 21 is heated to about 7 ° C.
After heating to 00 ° C and heat treatment for about 30 seconds, C
The silicide reaction of the o film is performed. In the region that is in contact with Si, the silicide reaction of the Co film proceeds and a silicide film is formed. Since the gate electrode 24 is covered with the silicon nitride film 25, the silicide reaction does not proceed.

After that, an aqueous solution of HCl and hydrogen peroxide (H ₂
Then, the unreacted Co film 27 remaining on the field oxide film 22, the side wall 26, and the nitride silicide film 25 is removed by immersing in a mixed solution of O ₂ ) (HCL: H ₂ O ₂ = 3: 1). The cobalt silicide film 28 is formed only on the portions where the source / drain regions of the MOS transistor are to be formed.

As shown in FIG. 3B, the substrate 21 is immersed in a hot phosphoric acid solution.
Is immersed and the silicon nitride film 25 is removed. When the silicon nitride film 25 is removed, the upper surface of the amorphous silicon gate electrode 24 is exposed. In this state, n-type impurities such as phosphorus and arsenic are ion-implanted. For example, As ions are ion-implanted at an acceleration voltage of about 40 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² .

As ions are directly implanted into the gate electrode 24 of amorphous silicon, and As is relatively deep.
Are distributed. Since the upper surfaces of the source region 29 and the drain region 30 are covered with the cobalt silicide film 28, the ion implantation depth becomes smaller accordingly.

After that, heat treatment is performed at a temperature of 850 ° C. for a time of about 30 minutes. By this heat treatment, the ion-implanted impurities are activated and sufficiently diffused in the gate electrode 24. Also, amorphous silicon changes to polycrystalline silicon. Further, the cobalt silicide film 28 is completely changed to CoSi ₂ . In this way, the low resistance polycrystalline gate electrode 24 and the shallow and low resistance source / drain regions 29 and 30 are formed.

As shown in FIG. 3C, the Si substrate 21 is immersed in a dilute hydrofluoric acid solution to remove a natural oxide film that may be formed on the silicon surface. Then, the Si substrate 21 is loaded into the sputtering apparatus, and the Co film 3 having a thickness of about 10 nm is formed.
1 is deposited by sputtering. This Co film 31
Directly contacts silicon at the gate electrode 24 and contacts the cobalt silicide film 28 at the source / drain regions 29 and 30.

As shown in FIG. 4A, the Si substrate 21 is subjected to a heat treatment at a temperature of about 700 ° C. for a time of about 30 seconds to cause the silicide reaction between the Co film 31 and the silicon gate electrode 24. The silicide reaction does not proceed on the silicon oxide films 22 and 26, and the silicide reaction does not proceed much on the silicide film 28.

In this way, the cobalt silicide film 32 is formed on the gate electrode 24. After that, the Si substrate 2
The unreacted Co film 31 is removed by immersing 1 in a mixed solution of HCl + H ₂ O ₂ (3: 1) for about 120 seconds.
The cobalt silicide film 32 changes to CoSi ₂ after the subsequent heat treatment.

As shown in FIG. 4B, a silicon oxide interlayer insulating film 33 having a thickness of about 400 nm is formed on the surface of the Si substrate 21 by CVD. A contact film is formed by applying a resist film on the interlayer insulating film 33 and patterning the resist film. Using this resist mask as an etching mask, a contact hole is opened in the interlayer insulating film 33. This contact hole forming step is performed by using, for example, CF ₄
RI using + CHF ₃ mixed gas as etching gas
It can be done by E.

After exposing the cobalt silicide film 28 in the contact hole, a Ti film having a thickness of about 20 nm and a TiN film having a thickness of about 100 nm are deposited as barrier metals by sputtering, and further, a Ti metal film having a thickness of about 20 nm is deposited thereon. A 500 nm Al film is deposited.

A resist mask is formed on the electrode film thus formed, and the electrode film is patterned by performing RIE using, for example, Cl ₂ gas as an etching gas to form the source electrode 34, the drain electrode 35 and other electrodes. To form. In this way, an n-channel MOS transistor is formed.

By inverting all conductivity types, a p-channel MOS transistor can be manufactured by the same process. In the case of CMOS devices, n
A p-channel MOS transistor and an n-channel MOS transistor may be formed on the well and the p-well, respectively.

In the embodiment described above, in the ion implantation step shown in FIG. 3B, the source / drain regions are ion-implanted through the cobalt silicide film and the gate electrode is directly ion-implanted. Therefore, by the same ion implantation, impurities can be ion-implanted to the gate electrode to a sufficient depth, and shallow ion-implanted regions can be formed in the source / drain regions.

Further, by performing ion implantation after forming cobalt silicide, the silicide reaction is sufficiently performed, and the underlying Si is doped with a sufficiently large amount of impurities.
A diffusion region with cobalt silicide having a sufficiently low resistance can be obtained.

Further, since cobalt silicide is used, impurities such as As, B and P which are ion-implanted thereafter and the silicide film do not form a reaction compound. In addition, as such a silicide, tungsten silicide can also be used.

It is preferable that the heat treatment or the like for causing the silicide reaction is performed by rapid thermal annealing (RTA) using lamp heating. It is possible to carry out a desired silicidation reaction and to suppress undesired impurity diffusion. Further, a through oxide film of silicon oxide may be provided on the ion-implanted region before performing the ion implantation.

Ion implantation is performed after forming a cobalt silicide film on the source / drain regions.
The number of ion implantations can be limited, and the number of masks can be limited. Further, a sufficient amount of impurities can be ion-implanted into the gate electrode, and the impurity-implanted region can be shallowed into the source / drain regions. In this way, a fine and excellent MOS transistor can be manufactured.

Next, an example of forming a local wiring by using a silicide reaction will be described. 9A and 9B show examples of circuit configurations suitable for using local wiring. Figure 9A
FIG. 9B is an equivalent circuit diagram of a part of the ring oscillator, and FIG. 9B is an equivalent circuit diagram of the SRAM cell.

In FIG. 9A, two inverter circuits INV1 and INV2 are connected between a power supply voltage line V _DD and a ground line V _SS (or two power supply lines). In the first inverter circuit INV1, the source S1 of the p-channel MOS transistor Q1 is connected to the power supply line V _DD , and its drain D1 is directly connected to the drain D2 of the n-channel MOS transistor Q2. In addition, n-channel MOS
The source S2 of the transistor Q2 is connected to the ground line V _SS . The gates of the two transistors Q1 and Q2 are commonly connected to the gate electrode G1 to receive an input signal.

In the second inverter circuit INV2, the source S3 of the p-channel MOS transistor Q3 is connected to the power supply line V _DD , and its drain D3 is directly connected to the drain D4 of the n-channel MOS transistor.
The source S4 of the n-channel MOS transistor Q4 is connected to the ground line V _SS . Two transistors Q3,
The gate of Q4 is connected to the common gate electrode G2. The drains D1 and D of the first inverter circuit INV1
The output line connected to 2 is the second inverter circuit INV
It is connected to two gate electrodes G2.

In this way, the plurality of inverter circuits INV connected between the two power supply lines V _DD and V _SS are connected in cascade. Here, the first inverter circuit I
The output line connecting the drains D1 and D2 of NV1 is the second
Is connected to the gate electrode G2 of the inverter circuit INV2 by the local wiring LI1.

In FIG. 9B, two power supply lines V _DD and V
_{During SS} , as in FIG. 9A, two inverter circuits INV
1 and INV2 are connected. The drains D1 and D2 of the first inverter circuit INV1 are connected to the gate electrode G2 of the second inverter circuit INV2 by the local wiring LI1.

In this structure, the output line connecting the drains D3 and D4 of the second inverter circuit INV2 is fed back to the gate electrode G1 of the first inverter circuit INV1 by the local wiring LI2.

Further, the output line of the first inverter circuit is connected to the bit line -BL (B
The output line of the second inverter circuit INV2 is connected to the bit line BL via the transfer transistor Q6.
It is connected to the. Two transfer transistors Q5 and Q6
Is connected to the word line WL.

10A and 10B are schematic views showing the upper surface of the semiconductor device forming a part of the ring oscillator shown in FIG. 9A. FIG. 10A is a plan view of a stage in which a gate electrode is formed on a semiconductor substrate and source / drain regions are formed. In the figure, an n well is formed on the left side and a p well is formed on the right side.

Regions other than the surface regions 43 and 44 of the n-well are covered with a field oxide film. Further, regions other than the surface regions 45 and 46 of the p well are also covered with the field oxide film. The gate electrode G1 is formed through the gate oxide film so as to penetrate the surface regions 43 and 45. The gate electrode G2 has a surface region 44,
It is formed through the gate oxide film so as to penetrate 46.

After forming the gate electrodes G1 and G2 in this manner, the p well region is covered with a resist mask and p-type impurities are ion-implanted to form a p-type impurity in the n-well region.
Type source regions S1, S3 and p-type drain region D1,
D3 is formed.

The n well region is covered with a resist mask, and n type impurities are ion-implanted to form n type source regions S2, S4 and n type drain regions D2, D4 in the p well region. In this way, the four MOS transistors Q1, Q2, Q3, Q shown in FIG.
4 basic structures are created.

FIG. 10B shows a state where the inverters are cascade-connected by forming local wiring LI on the basic structure shown in FIG. 10A. The local wiring LI1 has two drains D1 and D1 of the first inverter circuit INV1.
2 is connected to the gate electrode G2 of the second inverter INV2. The local wiring LI1 is arranged on the field oxide film except for the portion overlapping the two drain regions D1 and D2 and the gate electrode G2, and it is not necessary to provide an interlayer insulating film to insulate the other circuit elements. .

The wiring layer cannot be formed on the field oxide film only by the electrode forming step using the salicide reaction shown in the above-mentioned embodiment. In the following examples, a method of manufacturing a local wiring that extends on the oxide film and connects the circuit elements to each other will be described.

FIG. 11 is a plan view of a semiconductor device showing a configuration example of the SRAM circuit shown in FIG. 9B. In order to realize the cross wiring of FIG. 9B, the arrangement is different from that of FIGS. 10A and 10B.

In FIG. 11, an n well is formed on the upper side and a p well is formed on the lower side. A surface region 41 in the n-well is defined surrounded by a field oxide film, and a surface region 42 in the p-well is similarly defined by a field oxide film. These surface areas 41, 4
The Si surfaces other than 2 are covered with a field oxide film.

The surface region 41 of the n-well has an inverted T-shape, and the surface region 42 of the p-well has an inverted U-shape. Two gate electrodes G1 and G2 are formed so as to penetrate the horizontal portion of the T-shaped surface region 41 and the horizontal portion of the U-shaped surface region 42. In this structure, the gate electrode G3 is further formed in the lower part of the drawing.

Ion implantation is performed by using these gate electrodes G1, G2, and G3 as masks, so that the gate electrodes G1 and G2
A portion of the surface region 41 not covered with G2 is doped with a p-type impurity to be a p-type region, and a portion of the surface region 42 not covered with the gate electrodes G1, G2, G3 is doped with an n-type impurity. It is an n-type region.

In this way, four MOS transistors Q1, Q2, Q3 and Q4 are provided as in FIGS. 10A and 10B.
Is formed, and two other MOS transistors Q5 and Q6 are also formed.

In this configuration, the MOS transistor Q
The source regions of 1 and Q3 are common regions and are shown by S1 in the figure. In addition, two MOS transistors Q2 and Q
The source region of No. 4 is also formed in the common region and is shown by S2 in the figure. Furthermore, two MOS transistors Q5 and Q
The drain region of 6 is formed in common with the drain regions of the two MOS transistors Q2 and Q4.

In such a structure, the gate electrode G
The surfaces of 1, G2 and G3 are covered with an insulating film, and the insulating film is peeled off only in the regions of the contact regions CT1 and CT2. That is, the gate electrode is exposed only in the contact region CT, and the substrate surface is exposed only in the region not covered with the gate electrodes G1, G2, G3 in the surface regions 41, 42.

In such a configuration, the local wiring LI1
Is formed so as to connect the drain regions D1 and D2 and the contact region CT2 of the gate electrode G2, and the local wiring LI2 is formed.
Are formed so as to connect the drain regions D3 and D4 and the contact region CT1 of the gate electrode G1.

These local wirings LI1 and LI2 are in contact with the underlying semiconductor surface at the three ends, but are arranged on the insulating film in the other regions. Therefore, it is not necessary to particularly provide an interlayer insulating film when forming the local wirings LI1 and LI2. Such a local wiring can be created by the manufacturing method of the embodiment described below.

12A to 12D are sectional views for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. In addition, in order to explain the method of manufacturing the local wiring, other portions are simplified and shown.

As shown in FIG. 12A, a MOS transistor having an LDD structure is formed on the surface of the substrate 51 surrounded by the field oxide film 52 by a usual method. In the figure, MOS
The transistor Q is an n-channel MOS transistor and is formed in the p-type silicon region 51. A silicon gate electrode 54 is formed on the gate insulating film 53, and both side surfaces thereof are covered with the oxide film of the sidewall 55.

An n-type source region 56 and a drain region 57 are formed on both sides of the gate electrode. A gate electrode 58 of another transistor is formed on the field oxide film.
Has been extended. An oxide film of the sidewall 59 is also formed on both side walls of the gate electrode 58. Hereinafter, a manufacturing method for forming a local wiring that connects the drain region 57 of the MOS transistor Q to the gate electrode 58 will be described.

In FIG. 12B, a Co film 60 having a thickness of about 10 nm and a Si film 61 having a thickness of about 30 nm are formed on the surface of the substrate 51 by sputtering. S
A resist mask 62 is formed so as to cover the region where the i film 61 is to be left.

Using the resist mask 62 as an etching mask, an ordinary parallel plate type RIE apparatus is used, and SF ₆ gas having a flow rate of about 100 sccm is used as an etching gas.
The pressure is maintained at about 50 mtorr, and RF power of about 200 W is applied to perform RIE etching.

As shown in FIG. 12C, the Si film 61 is etched to form a Si film pattern 61a. After the etching is completed, the resist pattern 62 is stripped by a downflow ashing device using oxygen plasma. The resist film peeling by the downflow ashing device causes little damage, and the damage to the Co film 60 can be suppressed to the minimum.

After that, the substrate is carried into a sputtering apparatus and a TiN film 62 is deposited by sputtering with a thickness of about 30 nm. That is, the patterned Si film 6
A Co film 60 and a TiN film 62 are laminated with the film 1a interposed therebetween.

After that, the substrate is heated to about 1000 ° C. by RTA, for example, to cause the silicide reaction of the Co film 60 to proceed. The silicide reaction proceeds in the portion where the Co film 60 is in contact with the surface of the substrate 51, the portion where it is in contact with the gate electrodes 54 and 58, and the portion where it is in contact with the Si film pattern 61a.

As shown in FIG. 12D, the Si film pattern 6
Local wiring 6 made of silicide in the region where 1a was present
5, the remaining TiN film 62 is removed by NH ₄ OH +
The H ₂ O ₂ mixture is removed, and the unreacted Co film 60 is removed with a HCl + H ₂ O ₂ (1: 1) mixture. In addition,
The unreacted Co film is removed by removing H ₂ SO ₄ + H ₂ O ₂ (3:
It may be removed by 1).

In this way, the silicide layer 64 is formed on the surface of the Si region, and the local wiring 65 extending on the field oxide film 52 can also be formed. An interlayer insulating film is not formed between the local wiring 65 and the gate electrode 58, which is the lower wiring layer, and the alignment accuracy for forming the contact hole is almost unnecessary. Therefore, a fine LSI structure can be easily created.

In the embodiment shown in FIGS. 12A-12D, the Si film pattern was sandwiched between the Co film and the TiN film to carry out the silicidation reaction. Since the surface of the Co film is covered with the TiN film, oxidation of the Co film is prevented and a suitable silicide film can be obtained.

13A to 13D are sectional views showing a method of manufacturing a local wiring according to another embodiment. As shown in FIG. 13A, a MOS transistor structure is formed on the surface of the substrate 51 by a usual method. The structure of FIG. 13A is the same as the structure of FIG. 12A.

As shown in FIG. 13B, a Co film 60 is formed on the surface of the substrate 51 as in the above-mentioned embodiment. continue,
The TiN film 62 is deposited by sputtering. After that, a resist mask 67 is formed on the surface of the substrate 51.
The resist mask 67 has an opening in a region where a local wiring is to be created. For example, Cl ₂ gas (flow rate about 100 sc
cm) as an etching gas and a pressure of about 50 mto
RF power of 200 W is applied by rr, and the TiN film 62 is RI.
Etch with E.

That is, the TiN film 62 is removed only in the region where the local wiring is to be formed. After that, the resist mask 62 is ashed by downflow of oxygen plasma.

As shown in FIG. 13C, a Si film 61 is deposited on the surface of the substrate 51 by sputtering with a thickness of about 30 nm. After depositing the Si film 61, a resist mask 68 is formed on the surface thereof. The resist mask 68 is a mask that covers a region where a local wiring is to be formed, and the resist mask 6
It is an inversion mask of 7.

Using the resist mask 68 as an etching mask, the Si film 61 is etched by RIE using SF ₆ gas. After etching the Si film 61, the resist mask 68 is ashed by a downflow of oxygen plasma.

RIE using SF ₆ gas was performed at about −3
When performed at a low temperature of 0 ° C. or less, the TiN film 62 and the Co film 60 are selectively etched with almost no etching.
The film 61 can be etched. Therefore, the opening portion of the resist mask 67 shown in FIG.
It is not necessary to provide an overlapping portion with the resist mask 68 shown in C. Even if the two masks are slightly misaligned,
The formed Si film pattern and the opening portion of the TiN film 62 are slightly deviated from each other and have no other influence. After the etching of the Si film 61, the resist mask 68 is ashed by downflow of oxygen plasma.

FIG. 13D shows the S thus formed.
The relationship between the i film pattern 61 and the TiN film pattern 62 is schematically shown. The TiN film 62 substantially covers the exposed portion of the Co film 60. The Si film 61 is the Co film 60
The deterioration caused by oxidation does not pose a problem. Therefore, as shown in the figure, by covering the exposed substantial surface of the Co film 60 with the TiN film 62, the subsequent heat treatment can be stably performed.

Thereafter, the substrate is heated to about 1000.degree. C. by RTA, for example, and heat treatment is performed, so that FIG.
A silicide local wiring as shown in 2D can be formed. Note that the formation of the silicide film on the exposed Si surface is the same as in FIG. 12D. Then Ti
The N film and the unreacted Co film are washed out.

By the manufacturing method shown in FIGS. 12A-12D and 13A-13D, local wiring LI as shown in FIG. 10B is formed.
1 can be created. If the upper surface of the Si electrode is exposed, the local wiring cannot be formed over the other Si wiring as shown in FIG. In such a case, the manufacturing method as shown in FIGS. 14A-14D may be used.

In FIG. 14A, the field oxide film 5 is formed.
An amorphous silicon film 66 and a silicon nitride film 67 are laminated on the surface of the Si substrate 51 provided with 2. An opening 68 is formed in a portion of the silicon nitride film 67 which will be a contact region.
Are formed.

As shown in FIG. 14B, the silicon nitride film 6
7. By patterning the amorphous silicon film 66, the gate oxide film 53, the amorphous silicon film 54, the gate electrode formed of the silicon nitride film 63, and the wiring and the surface formed of the amorphous silicon film 58a and the silicon nitride film 63a are exposed. Amorphous silicon film 5
The wiring formed by 8b is obtained. After that, n-type impurities are lightly ion-implanted to form an LDD region.

Next, as shown in FIG. 14C, sidewall insulating films 55, 59a, 59 are formed on the gate electrodes and wirings.
b is formed. Then, n-type impurities are ion-implanted to form source / drain regions 56 and 57. A MOS is formed on the surface of the substrate 51 defined by the field oxide film 52.
The transistor Q is formed, and two silicon wirings / electrodes 58a and 58b are formed on the field oxide film 52. The wirings / electrodes 54 and 58a are covered with SiN films 63 and 63a and sidewalls 55 and 59a of silicon oxide on their upper surfaces and side surfaces, respectively. The upper surface of the wiring / electrode 58b is exposed.

Thus, a state is created in which only the desired region of the wiring / electrode is exposed and the other wiring / electrode is covered with the insulating film. As shown in FIG. 14D, a Co film 60 is deposited by sputtering on the surface of the substrate 51 thus prepared. Then, FIG. 12B-12D or FIG.
As shown in 3B-13D, a Si film and a TiN film are deposited and a silicidation reaction proceeds.

According to this embodiment, the MOS transistor Q
There is another gate electrode 58b between the gate electrode 58b and the gate electrode 58b, but since the surface is covered with the SiN film 63a, the drain region 57 of the MOS transistor Q and the gate electrode 58b are connected by the local wiring of silicide. be able to.

As described above, by forming the local wiring over the other gate electrodes, the local wiring LI as shown in FIG. 11 can be formed.

15A and 15B show an example of making a borderless contact. In FIG. 15A, for example, a gate oxide film 72a is formed on the surface of a p-type Si substrate 71, and silicon gate electrodes 73a and 73b are formed thereon. The surfaces of the gate electrodes 73a and 73b are further covered with an insulating film 76. The sidewalls of the gate electrode are also covered with the insulating films 74a and 74b.
By implanting ions using the gate electrode as a mask,
n-type regions 75a and 75b are formed on the surface of the p-type substrate region 71.
75c has been created. Such a configuration is shown in FIG.
It can be created by a method equivalent to that shown in.

A silicide pad 77 is formed so as to extend from the n-type region 75b onto the insulating film surrounding the gate electrodes on both sides.
Are created by the same method as the above-mentioned embodiment. The pad 77 has a larger area than the exposed surface of the Si substrate 71.

An interlayer insulating film 78 is formed so as to cover the pad 77, and a contact hole is formed. It suffices that this contact hole be aligned with the pad 77, and the n-type region 7
The positional accuracy can be relaxed as compared with the case of aligning with the exposed surface of 5b.

After that, an electrode layer 79 of Al or the like is formed on the surface and patterned to form a wiring 79 electrically connected from the n-type region 75b through the pad 77.

FIG. 15B shows another configuration example of the borderless contact. The field oxide film 83 is formed on the surface of the Si substrate 71, and the MOS transistor Q is formed in the element region defined by the field 83. Like the MOS transistor shown in FIG. 15A, the MOS transistor Q has a structure in which the surface of the gate electrode is covered with the insulating film 76.

That is, a gate insulating film 72, a gate electrode 73, and an insulating film 76 are laminated on the surface of the Si substrate 71 and patterned to form a gate electrode structure whose surface is insulated. Further, the insulating film of the sidewall 74 covers the side wall of this gate electrode structure. N-type regions 75d and 75e are formed on both sides of the gate electrode.

In this state, the silicide pad 80 extending from the surface of the n-type region 75e to the surface of the field oxide film 83 is formed by the same method as in the above-described embodiment. Then, the surface is covered with an interlayer insulating film 78, and the pad 8
An opening exposing 0 is formed.

Thereafter, a wiring layer of Al or the like is formed on the surface and patterned to form wiring 81. Wiring 8
Since the connection between 1 and the n-type region 75e is made through the pad 80 by borderless contact, the alignment accuracy is eased.

By carrying out the silicidation reaction with the Co film surface, at least the part of the Co film surface not covered with the Si film being covered with the TiN film, the surface irregularities after the silicidation reaction are reduced and the surface morphology is improved. To be done. Also,
The surface of the Co film is not oxidized during the heat treatment and prevents the sheet resistance of silicide from increasing. When the wiring width is narrow, the resistivity of the silicide wiring is likely to increase, but by performing silicidation with the Co film covered with the TiN film, the line width dependence is reduced. Further, CoSi can be satisfactorily formed on the Si surface adjacent to the LOCOS oxide film.

In the embodiments described above, the thickness of the Co film was about 10 nm, but it can be arbitrarily selected from the range of 5 to 50 nm. The thickness of the Si film is about 3
Although it was 0 nm, it can be arbitrarily selected from the range of 20 to 200 nm. The patterning of the Si film and the TiN film is not limited to the method of the above-mentioned embodiment. Further, similar silicide electrodes or wirings can be applied to circuits other than the above-mentioned embodiments.

In the embodiment of FIGS. 1-4, the silicide reaction step is performed twice. Local wiring can be performed simultaneously with these silicide reaction steps. In particular, the wiring to the gate can be formed by utilizing the second silicide reaction.

FIG. 16 shows a case where a silicide local wiring is formed in a drain having a silicide layer. For example, by the steps up to FIG. 3B, the drain region 30 is formed on the surface of the silicon substrate 21, and the Co silicide layer 28 is formed on the surface thereof.
To form. A silicon wiring 58 having a sidewall oxide 59 is formed on the field oxide film 22.

A Co film 60 is deposited by sputtering on the entire surface of this substrate, and a Si film 61 is further deposited by sputtering. The Si film 61 is patterned into the shape of the local wiring by using photolithography. Drain region 30
Since the surface is covered with the Co silicide film 28, it is chemically stabilized. Therefore, the TiN film can be omitted. Then, a silicidation reaction is performed similarly to the step shown in FIG. 12D.

Although the Co film 60 is used, it may be replaced with a Ni film capable of silicidation at a lower temperature. For example, the Ni film 60 is deposited by sputtering with a thickness of 10 nm, and the Si film 61 is deposited thereon by sputtering with a thickness of 30 nm. The Si film 61 is patterned into a local wiring shape. For example, the substrate on which the resist mask is formed is loaded into a parallel plate type RIE apparatus, and SF ₆ 150 sccm + N
₂ Flow 30 sccm, pressure 0.1 Torr 200
High frequency power of W is supplied to perform RIE.

After that, heating at 450 ° C. for 30 seconds is performed by RTA to carry out a silicidation reaction. afterwards,
HCl: H ₂ O ₂ = 1: 1 or H ₂ SO ₄ : H ₂ O ₂
Then, the unreacted Ni film is removed. A good silicide wiring can be formed by such a process.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0124]

As described above, according to the present invention,
A suitable silicide electrode or silicide wiring can be formed without complicating the process.

By forming the local wiring made of silicide, miniaturization of the semiconductor device can be promoted.
By using Co silicide, it becomes easy to improve the performance of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 3 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 5 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 6 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional technique.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 9 is an equivalent circuit diagram showing an example of an electronic circuit suitable for using local wiring.

FIG. 10 is a plan view showing the configuration of a semiconductor device that realizes the circuit of FIG. 9A.

FIG. 11 is a plan view showing the configuration of a semiconductor device that realizes the circuit of FIG. 9B.

FIG. 12 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 13 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

[Explanation of symbols]

 21 silicon semiconductor substrate 22 field oxide film 23 gate oxide film 24 amorphous silicon film 25 silicon nitride film 26 sidewall 27 Co film 28 cobalt silicide film 29 source region 30 drain region 31 Co film 32 cobalt silicide film 33 interlayer insulating film 34 source electrode 35 Drain electrode 60 Co film 61 Si film 62 TiN film 64 Silicide layer 65 Silicide wiring 77 Silicide pad

Claims (22)

[Claims] 1. A step of forming a silicon gate electrode on a substrate of a silicon semiconductor via a gate insulating film, a step of covering an exposed surface of the silicon gate electrode with an insulating film, and exposing a substrate surface on both sides of the gate electrode. And a step of forming a first refractory metal film on the surface of the substrate, heating the substrate to cause a silicide reaction between the first refractory metal film and the surface of the substrate, and A step of forming a melting point metal silicide film, a step of removing the unreacted first refractory metal film, a step of removing an insulating film on the gate electrode and exposing a surface of the gate electrode, the gate electrode And a step of implanting impurity ions into the surface of the substrate below the first refractory metal silicide film, and a step of heating the substrate to activate the impurities. 2. After the step of implanting ions, the gate electrode is covered with a second layer.
Forming a refractory metal film, and heating the substrate to cause a silicidation reaction between the silicon gate electrode and the second refractory metal film to form a second refractory metal silicide film. Claim 1 including and
A method for manufacturing a semiconductor device as described above. 3. The second refractory metal film is also formed on the first refractory metal silicide film, and the second refractory metal silicide film is also formed on the first refractory metal silicide film. The method of manufacturing a semiconductor device according to claim 2. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the first refractory metal silicide film includes the step of heating the substrate from the front side with a lamp. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the second refractory metal silicide film includes the step of heating the substrate with a lamp from the front surface side. 6. The step of activating the impurities includes the step of heating the substrate with a lamp from the front surface side.
6. The method for manufacturing a semiconductor device according to any one of 5 above. 7. The step of covering the exposed surface of the silicon electrode with an insulating film includes the step of covering the gate electrode with a first insulating film at the same time as the gate electrode forming step, and then the second insulating film over the entire surface of the substrate. 7. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: depositing an oxide film and performing anisotropic etching to cover the side wall of the gate electrode with a sidewall insulating film. 8. The first insulating film and the second insulating film are formed of insulating films having different etching characteristics.
A method for manufacturing a semiconductor device as described above. 9. The first insulating film is a silicon nitride film, and the second insulating film is a silicon oxide film.
A method for manufacturing a semiconductor device as described above. 10. The method according to claim 1, further comprising the step of forming a through oxide film on the gate electrode and on the first refractory metal silicide film before the step of implanting the impurity ions. A method of manufacturing a semiconductor device according to claim 1. 11. The impurity to be ion-implanted is arsenic,
The method for manufacturing a semiconductor device according to claim 1, which contains phosphorus or boron. 12. A step of selectively oxidizing a surface of a silicon semiconductor substrate to form a local oxide film, and defining a silicon surface bounded at least in part by the local oxide film, and the silicon surface and the local surface. Depositing a cobalt film over the oxide film, depositing a silicon film on the cobalt film, and patterning to form a silicon film pattern extending from the silicon surface to the local oxide film; Forming a TiN film on the cobalt film; heating the substrate to cause a silicide reaction between the cobalt film and the silicon surface and between the cobalt film and the silicon film pattern; and the remaining TiN film And a step of removing an unreacted cobalt film, a method of manufacturing a semiconductor device. 13. The step of forming the TiN film comprises:
13. The method of manufacturing a semiconductor device according to claim 12, comprising a step of depositing an N film and a step of selectively removing the TiN film in a region where the silicon film pattern is formed. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the silicon film pattern is performed after the step of selectively removing the TiN film. 15. The step of forming the TiN film is performed after the step of forming the silicon film pattern, and T is formed on the entire surface of the cobalt film so as to cover the silicon film pattern.
The method of manufacturing a semiconductor device according to claim 12, wherein an iN film is formed. 16. The method further comprises the step of forming a silicon electrode pattern on the local oxide film before the cobalt film depositing step, wherein the step of forming the silicon film pattern comprises performing the local oxidation on the silicon surface. 16. The step of forming a silicon film pattern reaching the silicon electrode pattern through the film and causing the silicidation reaction also causes a silicidation reaction between the cobalt film and the silicon electrode pattern. A method of manufacturing a semiconductor device according to claim 1. 17. The step of forming the silicon electrode pattern includes the steps of depositing a silicon layer, patterning the silicon layer, and forming a silicide wall insulating film on the sidewall of the patterned silicon layer. 17. The method for manufacturing a semiconductor device according to item 16. 18. The step of forming the siliconized electrode pattern includes the step of depositing an upper layer of an insulator different from the sidewall insulating film after the silicon layer depositing step and before the patterning step, and further, the sidewall insulating film. 2. A step of selectively removing a part of the upper layer of the insulator after the forming step is included.
7. The method for manufacturing a semiconductor device according to 7. 19. The step of defining the silicon surface comprises forming at least two n-channel MOS transistor regions and two.
Forming a local oxide film that defines four p-channel MOS transistor regions, and forming a gate insulating film on the four MOS transistor regions before forming the silicon electrode pattern. Corresponding to the step of forming
19. The method of manufacturing a semiconductor device according to claim 17, wherein two gate electrode patterns common to the channel MOS transistor and the p channel MOS transistor are formed. 20. The step of forming the silicon film pattern forms a silicon film pattern for connecting a silicon surface to be a drain of the corresponding two MOS transistors and a gate electrode pattern of the other two MOS transistors. 20. The method for manufacturing a semiconductor device according to item 19. 21. The semiconductor device includes a parallel connection of CMOS inverter circuits having drains directly connected thereto, and the silicon film pattern connects the drain of the CMOS inverter circuit of the preceding stage and the gate of the CMOS inverter circuit of the succeeding stage. Of manufacturing a semiconductor device of. 22. The semiconductor device includes an SRAM cell having a parallel connection of CMOS inverter circuits whose drains are directly connected, wherein the silicon film pattern connects the drain of one CMOS inverter circuit to the gate of the other CMOS inverter circuit, 21. The method of manufacturing a semiconductor device according to claim 20, wherein the drain of the other CMOS inverter circuit is connected to the gate of the one CMOS inverter circuit.