JPH07114236B2 - Wiring structure manufacturing method - Google Patents
Wiring structure manufacturing methodInfo
- Publication number
- JPH07114236B2 JPH07114236B2 JP61243100A JP24310086A JPH07114236B2 JP H07114236 B2 JPH07114236 B2 JP H07114236B2 JP 61243100 A JP61243100 A JP 61243100A JP 24310086 A JP24310086 A JP 24310086A JP H07114236 B2 JPH07114236 B2 JP H07114236B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating layer
- wirings
- film
- wiring structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 46
- 238000000034 method Methods 0.000 description 29
- 239000004065 semiconductor Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000003870 refractory metal Substances 0.000 description 2
- 241000272470 Circus Species 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高密度および高速度化される半導体集積回路に
おけるサブミクロン配線に適用される配線構造の製造方
法に係わり、特に層間絶縁膜の構成の形成方法に関する
ものである。Description: TECHNICAL FIELD The present invention relates to a method of manufacturing a wiring structure applied to submicron wiring in a semiconductor integrated circuit which is to have a high density and a high speed, and particularly to a structure of an interlayer insulating film. The present invention relates to a forming method.
〔従来の技術〕 半導体集積回路において、高密度化および高速度化の進
歩は著しいものがある。[Prior Art] In semiconductor integrated circuits, there have been remarkable advances in high density and high speed.
最近、LSIの性能を制約する問題として、デバイスより
も配線にかかわる問題がクローズアツプされてきた。そ
の問題点は、大きく分けて２つある。第１点は、配線抵
抗と配線容量との積で決定される遅延時間に関する問題
である。A.K.Sinha等（“Speed Limitations due to In
terconnect Time Constants in VLSI Integrated Circu
its."IEEE vol.EDL−3,No.4.Apr.1982.pp90−92.）は、
配線の電気的特性を２次元ラプラス方程式による数値計
算で求め、サブミクロンルールのLSIにおいては、デバ
イスのスピードよりも配線による遅延時間の方が大きい
と報告している。また、K.C.Saraswat等（“Effect of
Scaling of Int−erconnections on the Time Delay of
VLSI Cir−cuits."IEEE vol.ED−29.No.4.Apr.1982.pp
645−650）は、0.5μｍルール以下でのLSIの性能が配線
技術によつて決まるとも報告している。これまで配線に
よる遅延時間を少なくするために低抵抗配線金属材料の
検討と低比誘電率絶縁膜の検討とが進められてきた。配
線に関しては、現在A1（Si）が多く用いられているが、
サブミクロン領域では限界と考えられ、A1中へのTi,Cu
等の不純物の添加、高融点金属層との組み合わせ、さら
にはM0のような高融点金属配線も検討されている。一
方、絶縁膜に関しては、SiO2膜よりも誘電率が低く、か
つ、安定な材料はいまだに開発されていない。第２点
は、漏話に関する問題である。漏話が発生する理由は、
第６図に示すように半導体基板３上に形成された配線構
造において、高密度化が進み、配線２の膜厚d1とその下
の絶縁層１の膜厚d2と配線間膜厚d3が同程度になつた時
に生じやすくなる。その理由は、配線間容量が配線の対
地容量と同程度あるいは大きくなるからである。漏話量
の目安は、良く知られているように次式で与えられる。Recently, as a problem that limits the performance of LSI, the problem of wiring rather than device has been closed up. There are two major problems. The first point is a problem regarding the delay time determined by the product of the wiring resistance and the wiring capacitance. AKSinha etc. (“Speed Limitations due to In
terconnect Time Constants in VLSI Integrated Circu
its. "IEEE vol.EDL-3, No.4.Apr.1982.pp90-92.)
The electrical characteristics of the wiring are obtained by numerical calculation using the two-dimensional Laplace equation, and it is reported that the delay time due to the wiring is greater than the device speed in the submicron rule LSI. In addition, KCSaraswat etc. (“Effect of
Scaling of Int-erconnections on the Time Delay of
VLSI Cir−cuits. ”IEEE vol.ED−29.No.4.Apr.1982.pp
645-650) also reported that the wiring technology determines the performance of LSIs under the 0.5 μm rule. In order to reduce the delay time due to wiring, studies have been conducted on low-resistance wiring metal materials and low dielectric constant insulating films. Regarding wiring, A1 (Si) is currently widely used,
It is considered to be the limit in the submicron region, and Ti and Cu in A1
Addition of impurities such as, a combination with a refractory metal layer, and a refractory metal wiring such as M 0 are also under study. On the other hand, regarding the insulating film, a material having a lower dielectric constant than that of the SiO 2 film and a stable material has not yet been developed. The second point is the problem of crosstalk. The reason why crosstalk occurs is
6 in the wiring structure formed on the semiconductor substrate 3 as shown in FIG proceeds higher density, wiring 2 having a thickness d 1 and the thickness d 2 of the insulating layer 1 below the wire between the film thickness d It tends to occur when 3 is almost the same. The reason is that the inter-wiring capacitance becomes equal to or larger than the ground capacitance of the wiring. A measure of the amount of crosstalk is given by the following equation, as is well known.
CM／（CS＋CM） ここでCSは対地容量，CMは配線間容量である。この式か
ら、CS＝CMとなると、被誘導線に誘導線の電位の1/2の
電位が誘導されることが分かる。C M / (C S + C M ) where C S is the ground capacitance and C M is the inter-wiring capacitance. From this equation, it can be seen that when C S = C M , a potential half that of the induction wire is induced in the induced wire.
このように構成される配線構造において、漏話量を減ら
す一つの手段として、絶縁層１の膜厚ａを減らし、CSを
大きくする方法がある。しかし、この方法は配線遅延を
増加させるため好ましくない。また、もう一つの手段と
して配線２の膜厚d1を薄くするという方法がある。しか
しこの方法は配線抵抗が増加し、配線遅延を増大させる
ため好ましくない。さらにもう一つの漏話量低減の方法
として第７図に示すように配線２を覆つている絶縁膜１
上にグランドプレーン９を設けるというものがある。こ
の方法の最大の特徴は、配線２を多層化した際の異なる
配線層間の漏話が防止できる点にある。しかしこの方法
も配線容量は増加する。したがつて従来の配線構造は、
高密度化に伴つて増加する配線遅延および漏話を抑える
ことができないという欠点があつた。このため、高密度
化に伴い配線の信頼性を低下させることなく、配線遅延
を押さえつつ、同時に漏話量を低減する対応策が必要で
ある。また、高密度化が進むにつれて多層配線の構造が
必須となつてきている。多層構造を実現するには、平坦
化技術が必要である。最近、試料基板にバイアスを印加
しスパツタリングを利用し平坦化する方法があるが、ス
ループツト，ダメージ等の問題がある。In the wiring structure configured as described above, as one means for reducing the amount of crosstalk, there is a method of reducing the film thickness a of the insulating layer 1 and increasing C S. However, this method is not preferable because it increases the wiring delay. Another method is to reduce the film thickness d 1 of the wiring 2. However, this method is not preferable because the wiring resistance increases and the wiring delay increases. As another method for reducing the amount of crosstalk, the insulating film 1 covering the wiring 2 as shown in FIG.
There is one in which a ground plane 9 is provided on the top. The greatest feature of this method is that crosstalk between different wiring layers can be prevented when the wiring 2 is multilayered. However, this method also increases the wiring capacitance. Therefore, the conventional wiring structure is
There is a drawback in that it is not possible to suppress wiring delay and crosstalk that increase with the increase in density. Therefore, it is necessary to take measures to reduce the amount of crosstalk while suppressing the wiring delay without lowering the reliability of the wiring due to the higher density. In addition, as the density is increased, a multilayer wiring structure is becoming essential. A planarization technique is required to realize a multilayer structure. Recently, there has been a method of applying a bias to the sample substrate and flattening it by using sputtering, but there are problems such as sloping and damage.
本発明は、前述した従来の問題に鑑みてなされたもので
あり、その目的は、高密度および高速度化される半導体
集積回路において電気的に大きな問題となる遅延および
漏話量を低減させることができるとともにスルーストツ
プ，ダメージ等に全く影響されることなく絶縁層表面を
平坦化させ多層配線構造を可能とした配線構造の製造方
法を提供することにある。The present invention has been made in view of the above-described conventional problems, and an object thereof is to reduce the amount of delay and the amount of crosstalk, which are electrically large problems in a semiconductor integrated circuit which has a high density and a high speed. It is another object of the present invention to provide a method of manufacturing a wiring structure in which the surface of an insulating layer is flattened and a multilayer wiring structure is possible without being affected by slew stop, damage and the like.
本発明による配線構造の製造方法は、配線を含む第１の
絶縁層上にスパッタリング法により配線相互間の少なく
とも一部に空洞を有する第２の絶縁膜を形成するもので
ある。A method of manufacturing a wiring structure according to the present invention is to form a second insulating film having a cavity in at least a part between wirings on a first insulating layer including wirings by a sputtering method.
本発明における配線構造の製造方法においては、配線上
にスパッタリング法により配線相互間の少なくとも一部
に空洞を有する第２の絶縁膜を形成することにより、配
線相互間のせまい溝内に絶縁膜が堆積されずに空洞絶縁
層が形成されるとともに、その表面が平坦化される。In the method for manufacturing a wiring structure according to the present invention, the second insulating film having a cavity in at least a part between the wirings is formed on the wirings by a sputtering method so that the insulating film is formed in the narrow groove between the wirings. The cavity insulating layer is formed without being deposited, and the surface thereof is planarized.
以下、図面を用いて本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明により達成される配線構造の１例を示す
断面図である。同図において、半導体基板４上にはSiO2
からなる第１の絶縁層５が形成されており、この第１の
絶縁層５上にはAlからなる複数の配線６が形成され、さ
らにこれらの配線６上には、それぞれ配線６相互間に空
洞絶縁層７を有する第２の絶縁層８が形成されている。
この場合、第１の絶縁層５の比誘電率は3.9,空洞絶縁層
７の誘電率は1.0である。FIG. 1 is a sectional view showing an example of a wiring structure achieved by the present invention. In the figure, SiO 2 is deposited on the semiconductor substrate 4.
Is formed on the first insulating layer 5, and a plurality of wirings 6 made of Al are formed on the first insulating layer 5. A second insulating layer 8 having a hollow insulating layer 7 is formed.
In this case, the relative dielectric constant of the first insulating layer 5 is 3.9, and the dielectric constant of the cavity insulating layer 7 is 1.0.
このような構成によれば、配線６の下部の第１の絶縁層
５の膜厚d2と、配線６相互間の膜厚d3とが等しくても、
あるいは配線６相互間の膜厚d3が小さくても配線６の対
地容量よりも配線６相互間の容量を小さくすることがで
きる。したがつて、配線６を高密度に実装しても漏話が
発生し難くなる。また、互いに隣接した配線６上部の第
２の絶縁層８が接触し、配線６相互間に空洞絶縁層７を
形成すると同時にこの第２の絶縁層８の表面が平坦な構
造となるので、サブミクロン配線が可能となるとともに
その多層化が容易に実現可能となる。According to this structure, even if the film thickness d 2 of the first insulating layer 5 below the wiring 6 and the film thickness d 3 between the wirings 6 are equal to each other,
Alternatively, even if the film thickness d 3 between the wirings 6 is small, the capacitance between the wirings 6 can be made smaller than the ground capacitance of the wirings 6. Therefore, crosstalk is less likely to occur even if the wiring 6 is mounted at a high density. Further, since the second insulating layers 8 on the wirings 6 adjacent to each other come into contact with each other to form the cavity insulating layer 7 between the wirings 6 and at the same time, the surface of the second insulating layer 8 has a flat structure. Micron wiring becomes possible and the multilayer structure can be easily realized.
第２図は本発明により達成される配線構造の他の例の断
面図であり、第１図と同一または相当部分には同一符号
を付してある。同図において、第１図と異なる点は、第
２の絶縁層８上には金属材料のグランドプレーン９が形
成されている。この場合も空洞絶縁層７は、誘電率が第
１の絶縁層５および第２の絶縁層８よりも小さい。FIG. 2 is a cross-sectional view of another example of the wiring structure achieved by the present invention, in which the same or corresponding parts as in FIG. 1 are designated by the same reference numerals. In the figure, the difference from FIG. 1 is that a ground plane 9 made of a metal material is formed on the second insulating layer 8. Also in this case, the dielectric constant of the cavity insulating layer 7 is smaller than that of the first insulating layer 5 and the second insulating layer 8.
このような構成によれば、グランドプレーン９を設けた
ことにより、全配線容量が減るとともに配線６相互間容
量の対地容量に対する比率が減少し、配線６相互間の漏
話が大幅に低減される。また、このような構成によれ
ば、配線６を多層化した際、空洞絶縁層７は誘電率1.0,
第１の絶縁層５および第２の絶縁層８としてSiO2を用い
ることにより空洞絶縁層７の誘電率を、第１の絶縁層５
および第２の絶縁層８の比誘電率の1/4と小さくしたこ
とにより、Alのグランドプレーン９を上層に設けたため
に増加した配線容量を低減させるとともに配線６相互間
容量の対地容量に対する比率をさらに小さくさせ、漏話
量をさらに低減させることができる。According to such a configuration, by providing the ground plane 9, the total wiring capacitance is reduced, the ratio of the capacitance between the wirings 6 to the ground capacitance is reduced, and the crosstalk between the wirings 6 is significantly reduced. Further, according to such a configuration, when the wiring 6 is multilayered, the cavity insulating layer 7 has a dielectric constant of 1.0,
By using SiO 2 as the first insulating layer 5 and the second insulating layer 8, the dielectric constant of the cavity insulating layer 7 can be increased.
By reducing the relative permittivity of the second insulating layer 8 to 1/4, the wiring capacitance increased due to the Al ground plane 9 provided in the upper layer is reduced and the ratio of the mutual capacitance of the wiring 6 to the ground capacitance is reduced. Can be further reduced to further reduce the crosstalk amount.
次に本発明の配線構造を実現するための製造方法につい
て説明する。Next, a manufacturing method for realizing the wiring structure of the present invention will be described.
第３図（ａ），（ｂ）は本発明の一実施例による配線構
造の製造方法を説明する工程の断面図である。同図
（ａ）において、半導体基板４上にCVD法によりSiO2を
堆積して膜厚約0.5μｍの第１の絶縁膜５を形成する。
この場合、この第１の絶縁膜５の堆積方法としては、CV
D法以外にスパツタリング法，プラズマCVD法およびスピ
ンオン法などがあり、いずれを採用しても実現できるこ
とは言うまでもない。次にこの第１の絶縁膜５上に比抵
抗2.9×10-6Ω−cmのAlをスパツタリング法により堆積
して膜厚約1.0μｍの金属膜を形成した後にパターニン
グ加工を行なつて配線６を形成する。この場合、金属膜
の堆積法としては、スパツタリング法以外に蒸着法,CVD
法およびプラズマCVD法などがあるが、いずれを採用し
ても実現できることは言うまでもない。また、パターニ
ングは、レジストパターンをリソグラフイ工程により形
成した後、ドライエツチングより金属膜をエツチングし
て形成する。本実施例では微細パターンを形成するレジ
ストとしてはEB2層レジストを用い、リソグラフイがEB
描画法により行ない、パターン形成後、CCl4を用いてAl
金属膜をドタイエツチングした。次にこれらの配線６を
含む第１の絶縁膜５上に誘電率が第１の絶縁層５よりも
小さい空洞絶縁層７を有する第２の絶縁膜８を形成す
る。この第２の絶縁層８を形成する方法としては、スパ
ツタリング法，バイアススパツタリング法があるが本実
施例ではスパツタリング法を用いて形成した。この場合
の形成条件は、ターゲツトパワーが約3.5KW,Ar雰囲気中
のガス圧が2mTorrである。このスパツタリング法で第２
の絶縁膜８を堆積する場合、堆積する粒子は配線６相互
間の狭い溝の中に埋まらない特徴がある。第４図はこの
特性を定量的に説明する図である。同図において、溝の
高さをH,溝幅をS,堆積された平坦面膜厚をa,溝内に堆積
された膜厚をｂとしたとき横軸にアスペクト比（H/
S）、縦軸に埋め込み比（b/a）を示している。スパツタ
リング法による粒子は同図から判るようにアスペクト比
が1.0以上となると、溝に埋り難くなり、約50％程度し
か埋らない。これは、スパツタリング法の特徴で斜め方
向から粒子が飛来することによる。一方、サブミクロン
配線では、配線６の膜厚の減少は抵抗値を増加させるの
で、配線パターンの縮小に伴ないアスペクト比は高くな
り、1.0以上となる。このような形状に対してスパツタ
リング法により、膜堆積を行なうと、配線６相互間には
絶縁膜が堆積されずに空洞絶縁層７を有する層間膜が形
成されるとともにこの層間膜表面が平坦化される。この
空洞絶縁層７は誘電率が1.0であり、LSIプロセスに適用
可能である。また、最近では試料基板にバイアスを印加
したスパツタエツチングを利用して絶縁層表面の平坦化
を実現する方法があるが、この方法ではスループツトが
低く、ダメージが発生する等の問題があるが、本発明で
は、スパツタリングの付着の悪さを積極的に利用したも
のであり、空洞絶縁層７の形成および表面平坦化を同時
に行なうことができる。したがつてスループツト，ダメ
ージの問題がなく、かつプロセスを複雑にすることな
く、LSIの高密度な配線構造が容易に得られる。3 (a) and 3 (b) are sectional views of steps for explaining a method of manufacturing a wiring structure according to an embodiment of the present invention. In FIG. 3A, SiO 2 is deposited on the semiconductor substrate 4 by the CVD method to form the first insulating film 5 having a film thickness of about 0.5 μm.
In this case, the method for depositing the first insulating film 5 is CV
In addition to the D method, there are sputtering method, plasma CVD method, spin-on method, and the like, and it goes without saying that any of them can be realized. Next, Al having a specific resistance of 2.9 × 10 −6 Ω-cm is deposited on the first insulating film 5 by the sputtering method to form a metal film having a thickness of about 1.0 μm, and then patterning is performed to form the wiring 6 To form. In this case, as the deposition method of the metal film, other than the sputtering method, the vapor deposition method and the CVD method are used.
Method and plasma CVD method, but it goes without saying that any of them can be realized. The patterning is performed by forming a resist pattern by a lithographic process and then etching the metal film by dry etching. In this embodiment, an EB two-layer resist is used as the resist for forming the fine pattern, and the lithography is EB.
By drawing method, after pattern formation, use CCl 4 to form Al
The metal film was etched. Next, a second insulating film 8 having a cavity insulating layer 7 having a dielectric constant smaller than that of the first insulating layer 5 is formed on the first insulating film 5 including these wirings 6. As a method for forming the second insulating layer 8, there are a spattering method and a bias spattering method, but in the present embodiment, the spattering method is used. The formation conditions in this case are a target power of about 3.5 KW and a gas pressure of 2 mTorr in an Ar atmosphere. Second with this sputtering method
When the insulating film 8 is deposited, the deposited particles are characterized in that they are not buried in the narrow grooves between the wirings 6. FIG. 4 is a diagram for quantitatively explaining this characteristic. In the figure, when the groove height is H, the groove width is S, the deposited flat surface film thickness is a, and the film thickness deposited in the groove is b, the horizontal axis represents the aspect ratio (H /
S), and the vertical axis shows the embedding ratio (b / a). As can be seen from the figure, when the aspect ratio is 1.0 or more, the particles obtained by the sputtering method are difficult to fill in the groove, and only about 50% is filled. This is due to particles coming in from an oblique direction, which is a feature of the sputtering method. On the other hand, in the submicron wiring, the reduction in the film thickness of the wiring 6 increases the resistance value, so that the aspect ratio increases with the reduction of the wiring pattern and becomes 1.0 or more. When a film is deposited on such a shape by the sputtering method, an insulating film is not deposited between the wirings 6 but an interlayer film having a cavity insulating layer 7 is formed and the surface of the interlayer film is flattened. To be done. The cavity insulating layer 7 has a dielectric constant of 1.0 and is applicable to the LSI process. Further, recently, there is a method of realizing flattening of the insulating layer surface by using a sputtering method in which a bias is applied to the sample substrate, but this method has a problem that the throughput is low and damage occurs, In the present invention, the poor adhesion of the spattering is positively utilized, and the formation of the cavity insulating layer 7 and the surface flattening can be performed at the same time. Therefore, there is no problem of throughput and damage, and a high-density wiring structure of LSI can be easily obtained without complicating the process.
第４図（ａ），（ｂ），（ｃ）は本発明の他の実施例に
よる配線構造の製造方法を説明する工程の断面図であ
り、前述の図と同一または相当する部分には同一符号を
付してある。同図において、まず、同図（ａ）に示すよ
うに半導体基板４上にCVD法によりSiO2を堆積して膜厚
約0.5μｍの第１の絶縁膜５を形成する。次にこの第１
の絶縁膜５上にスパツタリング法によりAlを堆積して膜
厚約1.0umの金属膜を形成した後、前記第１の実施例と
同様にEBレジストによりパターンを形成し、次いでCCl4
を用いてドライエツチングを行ない、その後レジストを
除去して配線６を形成する。次に同図（ｂ）に示すよう
に前記第１の実施例と同様に配線６を含む第１の絶縁層
５上に、配線６相互間に空洞絶縁層７を有する第２の絶
縁層８を形成した後、同図（ｃ）に示すようにこの第２
の絶縁層８上に金属材料であるグランドプレーン９を堆
積する。本実施例ではスパツタリング法によりAlを堆積
して膜厚約0.2μｍのAl膜を形成した。4 (a), (b), and (c) are cross-sectional views of steps for explaining a method of manufacturing a wiring structure according to another embodiment of the present invention, in which the same or corresponding portions as those in the above-mentioned drawings are the same. It is attached with a code. In the figure, first, as shown in FIG. 3A, SiO 2 is deposited on the semiconductor substrate 4 by the CVD method to form a first insulating film 5 having a film thickness of about 0.5 μm. Then this first
Al was deposited on the insulating film 5 by a sputtering method to form a metal film having a thickness of about 1.0 μm, a pattern was formed with an EB resist as in the first embodiment, and then CCl 4 was used.
Is used for dry etching, and then the resist is removed to form the wiring 6. Next, as shown in FIG. 7B, the second insulating layer 8 having the cavity insulating layer 7 between the wirings 6 is formed on the first insulating layer 5 including the wirings 6 as in the first embodiment. After the formation of the second, as shown in FIG.
A ground plane 9 made of a metal material is deposited on the insulating layer 8 of FIG. In this embodiment, Al is deposited by the sputtering method to form an Al film having a thickness of about 0.2 μm.
このような方法によれば、第２の絶縁層８上にグランド
プレーン９を形成したことにより増加する配線容量が低
減され配線６相互間容量の対地容量に対する比率がさら
に小さくなり、漏話量を一層低減させた配線構造を容易
に得ることができる。According to such a method, the wiring capacitance increased by forming the ground plane 9 on the second insulating layer 8 is reduced, the ratio of the capacitance between the wirings 6 to the ground capacitance is further reduced, and the crosstalk amount is further reduced. It is possible to easily obtain a reduced wiring structure.
以上説明したように本発明による配線構造の製造方法に
よれば、配線を含む第１の絶縁膜上にスパッタリング法
により配線相互間の少なくとも一部に空洞を有する第２
の絶縁膜を形成することにより、配線相互間に空洞絶縁
層が形成され、さらにこの空洞絶縁層形成後の第２の絶
縁層の表面が平坦化されるので、サブミクロン配線が容
易に可能となるとともにその多層化が容易に実現可能と
なるなどの極めて優れた効果が得られる。As described above, according to the method for manufacturing a wiring structure according to the present invention, the second insulating film including the wiring has a cavity in at least a part between the wirings formed by the sputtering method.
By forming the above insulating film, a cavity insulating layer is formed between the wirings, and the surface of the second insulating layer after the formation of the cavity insulating layer is flattened, so that submicron wiring can be easily performed. In addition, it is possible to obtain an extremely excellent effect that the multilayer structure can be easily realized.
第１図は本発明により達成される配線構造の１例を示す
断面図、第２図は本発明により達成される配線構造の他
の例を示す断面図、第３図（ａ），（ｂ）は本発明の一
実施例による配線構造の製造方法の一実施例を示す工程
の断面図、第４図はスパツタリング法による埋め込み特
性を示す図、第５図（ａ），（ｂ），（ｃ）は本発明の
他の実施例による配線構造の製造方法を示す工程の断面
図、第６図および第７図は従来の配線構造を示す断面図
である。 ４……半導体基板、５……第１の絶縁層、６……配線、
７……空洞絶縁層、８……第２の絶縁層、９……グラン
ドプレーン。FIG. 1 is a sectional view showing an example of a wiring structure achieved by the present invention, FIG. 2 is a sectional view showing another example of a wiring structure achieved by the present invention, and FIGS. 3 (a) and 3 (b). ) Is a sectional view of a step showing an embodiment of a method for manufacturing a wiring structure according to an embodiment of the present invention, FIG. 4 is a view showing an embedding characteristic by a sputtering method, and FIGS. 5 (a), (b), ( FIG. 6C is a sectional view of a step showing a method of manufacturing a wiring structure according to another embodiment of the present invention, and FIGS. 6 and 7 are sectional views showing a conventional wiring structure. 4 ... Semiconductor substrate, 5 ... First insulating layer, 6 ... Wiring,
7 ... Hollow insulation layer, 8 ... Second insulation layer, 9 ... Ground plane.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小林 敏夫 神奈川県厚木市森の里若宮３番１号 日本 電信電話株式会社厚木電気通信研究所内 (72)発明者 木内 一秀 神奈川県厚木市森の里若宮３番１号 日本 電信電話株式会社厚木電気通信研究所内 (56)参考文献 特開 昭60−85530（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toshio Kobayashi 3-1, Morinosato Wakamiya, Atsugi-shi, Kanagawa, Japan Atsugi Telecommunications Research Laboratories, Nippon Telegraph and Telephone Corporation (72) Inventor Kazuhide Kiuchi 3-1, Wakamiya, Morinosato, Atsugi-shi, Kanagawa Nippon Telegraph and Telephone Corporation, Atsugi Electro-Communications Research Laboratory (56) References JP-A-60-85530 (JP, A)
Claims (1)
前記第１の絶縁層上に金属膜を形成する工程と、前記金
属膜を選択的にエッチングすることで配線を形成する工
程と、前記配線を含む第１の絶縁層上にスパッタリング
法により前記配線相互間の少なくとも一部に空洞を有す
る第２の絶縁膜を形成する工程とを含むことを特徴とす
る配線構造の製造方法。1. A step of forming a first insulating layer on a substrate,
Forming a metal film on the first insulating layer; forming a wiring by selectively etching the metal film; and forming a wiring on the first insulating layer including the wiring by a sputtering method. And a step of forming a second insulating film having cavities in at least a part thereof, the method of manufacturing a wiring structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61243100A JPH07114236B2 (en) | 1986-10-15 | 1986-10-15 | Wiring structure manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61243100A JPH07114236B2 (en) | 1986-10-15 | 1986-10-15 | Wiring structure manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6398134A JPS6398134A (en) | 1988-04-28 |
| JPH07114236B2 true JPH07114236B2 (en) | 1995-12-06 |
Family
ID=17098790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61243100A Expired - Lifetime JPH07114236B2 (en) | 1986-10-15 | 1986-10-15 | Wiring structure manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07114236B2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5407860A (en) * | 1994-05-27 | 1995-04-18 | Texas Instruments Incorporated | Method of forming air gap dielectric spaces between semiconductor leads |
| US5599745A (en) * | 1995-06-07 | 1997-02-04 | Micron Technology, Inc. | Method to provide a void between adjacent conducting lines in a semiconductor device |
| US5641712A (en) * | 1995-08-07 | 1997-06-24 | Motorola, Inc. | Method and structure for reducing capacitance between interconnect lines |
| US5847464A (en) * | 1995-09-27 | 1998-12-08 | Sgs-Thomson Microelectronics, Inc. | Method for forming controlled voids in interlevel dielectric |
| US5728631A (en) * | 1995-09-29 | 1998-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a low capacitance dielectric layer |
| JPH09172079A (en) * | 1995-12-20 | 1997-06-30 | Nec Corp | Semiconductor device and its manufacture |
| US6303464B1 (en) * | 1996-12-30 | 2001-10-16 | Intel Corporation | Method and structure for reducing interconnect system capacitance through enclosed voids in a dielectric layer |
| WO1998032169A1 (en) * | 1997-01-21 | 1998-07-23 | The B.F. Goodrich Company | Fabrication of a semiconductor device with air gaps for ultra-low capacitance interconnections |
| JP3085231B2 (en) | 1997-02-20 | 2000-09-04 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH1117005A (en) * | 1997-06-20 | 1999-01-22 | Nec Corp | Semiconductor device and manufacture thereof |
| US6165897A (en) * | 1998-05-29 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Void forming method for fabricating low dielectric constant dielectric layer |
| US6440839B1 (en) * | 1999-08-18 | 2002-08-27 | Advanced Micro Devices, Inc. | Selective air gap insulation |
| JP2008103610A (en) | 2006-10-20 | 2008-05-01 | Matsushita Electric Ind Co Ltd | Wiring structure of semiconductor integrated circuit and design method and design apparatus thereof |
| JP2008130911A (en) | 2006-11-22 | 2008-06-05 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit design method and program, semiconductor integrated circuit design support method and program, wiring parasitic capacitance calculation method and program |
| JP6856974B2 (en) * | 2015-03-31 | 2021-04-14 | ソニーセミコンダクタソリューションズ株式会社 | Solid-state image sensor and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6085530A (en) * | 1983-10-18 | 1985-05-15 | Seiko Epson Corp | Semiconductor integrated circuit device |
-
1986
- 1986-10-15 JP JP61243100A patent/JPH07114236B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6398134A (en) | 1988-04-28 |
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