JPH07111661A - Head switch phase adjusting device - Google Patents
Head switch phase adjusting deviceInfo
- Publication number
- JPH07111661A JPH07111661A JP5256791A JP25679193A JPH07111661A JP H07111661 A JPH07111661 A JP H07111661A JP 5256791 A JP5256791 A JP 5256791A JP 25679193 A JP25679193 A JP 25679193A JP H07111661 A JPH07111661 A JP H07111661A
- Authority
- JP
- Japan
- Prior art keywords
- pal
- circuit
- phase
- signal
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、複数種のテレビジョン
方式に対応したVTRやNTSC再生(録画)機能付P
AL方式用VTRのヘッド切換パルスの位相調整装置に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PTR with a VTR or NTSC playback (recording) function corresponding to a plurality of types of television systems.
The present invention relates to a phase adjusting device for a head switching pulse of an AL type VTR.
【0002】[0002]
【従来の技術】世界で採用されているテレビジョン方式
には、大きく分けてNTSC方式と、PAL方式の2つ
があり、それぞれに対応して、VTRが作られている。2. Description of the Related Art Television systems adopted in the world are roughly classified into two types, NTSC system and PAL system, and a VTR is made corresponding to each.
【0003】テレビジョン放送の開始当初は、それぞれ
クローズドなシステムとして使用されるため格別の問題
はなかったが、最近のように世界レベルでの情報の交換
が活発になると、双方の方式による情報の交換の必要性
が高まっている。At the beginning of television broadcasting, there were no particular problems because they were used as closed systems, but when the exchange of information at the global level became active recently, information from both systems will be exchanged. The need for replacement is increasing.
【0004】そのため、VTRを、2種の方式で記録さ
れたものを1台のVTRで再生できるものが望まれ、そ
れを可能にしたVTRが既に開発されている。Therefore, it is desired that a VTR recorded by two types of systems can be reproduced by one VTR, and a VTR which enables this has already been developed.
【0005】2つの方式による技術上の差は種々ある
が、2方式に適用可能なVTRを実現する場合に、解決
すべき点の1つとして、ヘッド切換位相を夫々の方式に
合せて調整しなければならないという点がある。Although there are various technical differences between the two systems, one of the points to be solved when realizing a VTR applicable to the two systems is to adjust the head switching phase according to each system. There is a point that must be.
【0006】そのような従来のヘッド切換位相調整装置
を、図3,4,5,6に従って説明する。Such a conventional head switching phase adjusting device will be described with reference to FIGS.
【0007】図3に、ドラムに配置されるドラム位相基
準信号発生器(以下PGという)とビデオヘッドの関係
を示す。又、図4にその時間的関係を示す。PGビデオ
ヘッド間にはθなる角度が存在し、このθが機械的寸法
バラツキを有し、その寸法バラツキを電気的に吸収させ
ようというのが、PG位相調整である。(VHS規格に
あるヘッドスイッチングタイミングと垂直同期位相の調
整。)図5及び図6に、PAL方式とNTSC方式を両
立させたVTRにおける従来のPG位相調整の概略フロ
ーを示す。FIG. 3 shows the relationship between the drum phase reference signal generator (hereinafter referred to as PG) arranged on the drum and the video head. Further, FIG. 4 shows the time relationship. There is an angle θ between the PG video heads, and this θ has a mechanical dimensional variation, and the PG phase adjustment is to electrically absorb the dimensional variation. (Adjustment of head switching timing and vertical sync phase in the VHS standard.) FIGS. 5 and 6 show a general flow of a conventional PG phase adjustment in a VTR that is compatible with the PAL system and the NTSC system.
【0008】図5の(a)〜(f)が、PAL方式PG
位相調整のための作業である。まず、PAL標準テープ
(調整用テープ)をVTRに挿入し、再生する。する
と、このVTRは、PAL方式モードで走行する。PG
調整モードとし、PG位相を調整し、時間TPAL(θの
角度差を時間量へ変換したもの)を求める。時間TPAL
の作り方は、アナログモノマルチ(コンデンサと抵抗を
組み合せた充電時定数利用のもの)と、マイコン利用の
ディジタルモノマルチのいずれでも良い。そして時間T
PALをメモリーする。一方、NTSC時は、VTRをN
TSC方式で走行させ、図6の(g)〜(l)のフロー
にて、(PALと同様の手順で行う。)時間TNTSCを求
め、メモリーする。5A to 5F are PAL system PGs.
This is work for adjusting the phase. First, a PAL standard tape (adjustment tape) is inserted into the VTR and reproduced. Then, this VTR runs in the PAL system mode. PG
The adjustment mode is set, the PG phase is adjusted, and the time T PAL (the angle difference of θ converted into the amount of time) is obtained. Time T PAL
The method of making is either an analog mono-multi (using a charging time constant combining a capacitor and a resistor) or a digital mono-multi using a microcomputer. And time T
Memorize PAL . On the other hand, at the time of NTSC, VTR is set to N
The vehicle is run by the TSC method, and the time T NTSC (performed in the same procedure as PAL) is obtained and stored in the flow of (g) to (l) of FIG.
【0009】[0009]
【発明が解決しようとする課題】以上述べたとおり、従
来は、NTSC用位相値,PAL用位相値を求めるの
に、それぞれ、同様の作業を繰り返し行なわねばならな
かった。そのため、調整作業に時間を要し、コストアッ
プの要因となっていた。As described above, conventionally, in order to obtain the phase value for NTSC and the phase value for PAL, the same work had to be repeated. Therefore, adjustment work takes time, which is a factor of cost increase.
【0010】本発明は、このような点を考慮してなされ
たものであり、1つの方式での調整作業のみを行なうこ
とで、他方の調整作業を必要としない、ヘッド切換位相
調整装置を提供することを目的とする。The present invention has been made in consideration of the above point, and provides a head switching phase adjusting device which does not require the other adjusting operation by performing only one adjusting operation. The purpose is to do.
【0011】[0011]
【課題を解決するための手段】前記目的を達成するため
に、本発明においては、NTSC及びPAL等の2方式
のテレビジョン信号を録画再生するビデオテープレコー
ダにおいて、一方の方式のドラム位相基準信号(PG)
からヘッド切換パルス出力までの位相差をディジタル的
数値で測定・認識する測定・認識手段と、前記ディジタ
ル的数値をメモリーするメモリー手段と、前記メモリー
手段にメモリーされた数値を前記2方式のテレビジョン
信号間の垂直同期周波数の比に応じて演算し他の方式の
位相調整値を得る演算手段と、を有する。ヘッド切換位
相調整装置を設けている。In order to achieve the above object, in the present invention, in a video tape recorder for recording and reproducing two types of television signals such as NTSC and PAL, a drum phase reference signal of one type is used. (PG)
Measuring / recognizing means for measuring / recognizing the phase difference from the output to the head switching pulse by digital numerical values, memory means for storing the digital numerical values, and the numerical values stored in the memory means for the television of the two systems. And a calculating means for calculating a phase adjustment value of another method according to the ratio of the vertical synchronizing frequency between the signals. A head switching phase adjusting device is provided.
【0012】[0012]
【作用】本発明によれば、一方の方式のテレビジョン信
号に合せたヘッド切換位相調整を行ない、他方の方式の
テレビジョン信号に対する位相調整量は計算によって求
めるようにしているので、1回の調整作業を行なうだけ
で、2方式のテレビジョン用の調整が完了する。According to the present invention, the head switching phase adjustment is performed according to the television signal of one system, and the phase adjustment amount for the television signal of the other system is obtained by calculation. The adjustment for the two-system television is completed simply by performing the adjustment work.
【0013】[0013]
【実施例】以下、本発明の実施例を図1〜図3に従って
説明する。Embodiments of the present invention will be described below with reference to FIGS.
【0014】まず、図1に従ってブロック図を説明す
る。1は複合同期信号から垂直同期信号を抜き取る積分
・波形整形回路であり、2は目標位相値がメモリーされ
たROMであり、3は位相比較及び誤差検出を行う位相
比較・誤差検出回路である。また、41はPG信号の増
幅及び波形整形を行う増幅・波形整形回路であり、5は
遅延パルス作成遅延値出力回路であり、6はPALモー
ド時の遅延値がメモリーされたPAL遅延値メモリーで
あり、7はPALとNTSCとの回転比率25/30に
応じた演算を行なうPAL遅延値×5÷6計算回路であ
り、8は計算回路7の出力値をメモリーするNTSC遅
延値メモリーである。First, a block diagram will be described with reference to FIG. Reference numeral 1 is an integration / waveform shaping circuit for extracting a vertical sync signal from the composite sync signal, 2 is a ROM in which a target phase value is stored, and 3 is a phase comparison / error detection circuit for performing phase comparison and error detection. Further, 41 is an amplification / waveform shaping circuit for amplifying and shaping the PG signal, 5 is a delay pulse creation delay value output circuit, and 6 is a PAL delay value memory in which the delay value in the PAL mode is stored. Yes, 7 is a PAL delay value × 5 ÷ 6 calculation circuit that performs an operation according to the rotation ratio of PAL and NTSC of 25/30, and 8 is an NTSC delay value memory that stores the output value of the calculation circuit 7.
【0015】次に動作を説明する。まず、PAL調整用
テープを使用し、PG調整モードにて、複合同期信号か
ら、積分波形整形回路1において、垂直同期信号を抜き
取り波形整形し、位相比較・誤差検出回路3に送る。R
OM2にメモリーされた目標位相値(垂直同期とヘッド
スイッチングパルスの位相差)と、測定値の比較を行
い、目標位相値になるように、遅延パルス作成ブロック
を制御する。Next, the operation will be described. First, the PAL adjustment tape is used, and in the PG adjustment mode, the vertical synchronizing signal is extracted from the composite synchronizing signal by the integral waveform shaping circuit 1, and the waveform is shaped and sent to the phase comparison / error detection circuit 3. R
The measured value is compared with the target phase value (the phase difference between the vertical synchronization and the head switching pulse) stored in OM2, and the delay pulse creation block is controlled so that the target phase value is reached.
【0016】5の遅延パルス作成回路には、ドラムの回
転位相を検出するため、PG信号が、増幅・波形整形回
路4により波形整形されて入力され、PGから、遅延パ
ルス(ヘッド・スイッチング・パルスとなるパルス)ま
での遅延値が管理される。In order to detect the rotation phase of the drum, the delay pulse generating circuit 5 receives the PG signal after the waveform is shaped by the amplifying / wave shaping circuit 4, and the delayed pulse (head switching pulse) is input from the PG. Pulse value) is controlled.
【0017】位相比較・誤差検出回路3にて、目標位相
になった事が確認されると、そのときの、PGと遅延パ
ルスの位相すなわち、遅延値が、PAL遅延値として、
PAL遅延値メモリー6にメモリーされる。When it is confirmed by the phase comparison / error detection circuit 3 that the target phase has been reached, the phases of the PG and the delay pulse at that time, that is, the delay value, is regarded as the PAL delay value.
It is stored in the PAL delay value memory 6.
【0018】次に、そのPAL遅延値を基に、PALと
NTSCとの回転数比率25/30に応じた(PAL遅
延値)×5÷6計算回路7にて、約83%の値を算出す
る。その値が、すなわち、NTSC遅延値として、NT
SC遅延値メモリー8にメモリーされる。Next, based on the PAL delay value, a value of about 83% is calculated by the (PAL delay value) × 5 ÷ 6 calculation circuit 7 according to the rotation speed ratio of 25/30 between PAL and NTSC. To do. That value is the NTSC delay value, NT
It is stored in the SC delay value memory 8.
【0019】2種の回転数(この場合PAL 25H
z,NTSC 30Hz)のちがいのある場合でも、機
械的な誤差(図3に示すθ±α)を1回の調整のみで、
2種の調整値を得る事ができる。Two speeds (in this case PAL 25H
z, NTSC 30Hz) even if there is a difference, mechanical error (θ ± α shown in FIG. 3) can be adjusted only once.
Two kinds of adjustment values can be obtained.
【0020】図2に実施例のフローチャートを示す。FIG. 2 shows a flowchart of the embodiment.
【0021】まず、PAL標準テープ(調整値テープ)
をVTRに挿入し、PLAYモードとする。VTR本体
は、PALで走行させる。PAL PG位相調整モード
として、ディジタルモノマルチを利用し、メカ取付誤差
θ±αを吸収すべく、ディジタルモノマルチを調整す
る。その数値TPALをPAL PG位相調整値としてメ
モリーする。First, PAL standard tape (adjustment value tape)
Is inserted into the VTR and the PLAY mode is set. The VTR body is run at PAL. The digital mono-multi is used as the PAL PG phase adjustment mode, and the digital mono-multi is adjusted to absorb the mechanical mounting error θ ± α. The numerical value T PAL is stored as the PAL PG phase adjustment value.
【0022】次に、TPALを元に、回転数の比率分25
/30≒83%の演算を実施する。Next, on the basis of T PAL , 25
Perform a calculation of / 30≈83%.
【0023】TPAL×83%=TNTSCとし、NTSC
PG位相調整値として、メモリーする。T PAL × 83% = T NTSC , NTSC
Memory is stored as the PG phase adjustment value.
【0024】[0024]
【発明の効果】従来、NTSC方式,PAL方式それぞ
れ調整していたものを、本発明によれば1回の調整で、
済む事となり、精度、手数の面で、大幅な改善が図れ
る。According to the present invention, it is possible to adjust the NTSC system and the PAL system each by one adjustment.
As a result, significant improvements can be made in terms of accuracy and labor.
【図1】本発明のブロック図である。FIG. 1 is a block diagram of the present invention.
【図2】本発明のフローチャートである。FIG. 2 is a flowchart of the present invention.
【図3】本発明に係る、ドラム上のヘッド配置図であ
る。FIG. 3 is a head layout diagram on a drum according to the present invention.
【図4】本発明に係る、PGに対するヘッド切換パルス
のタイミング図である。FIG. 4 is a timing diagram of a head switching pulse for a PG according to the present invention.
【図5】従来技術のPAL方式調整時のフローチャート
である。FIG. 5 is a flowchart when adjusting a PAL system according to a conventional technique.
【図6】従来技術のNTSC方式調整時のフローチャー
トである。FIG. 6 is a flowchart at the time of adjusting the NTSC system of the related art.
1 積分波形整形回路 2 ROM 3 位相比較誤差検出回路 4 増幅・波形整形回路 5 遅延パルス作成回路 6 PAL遅延値メモリー 7 PAL遅延値計算回路 8 NTSC遅延値メモリー 1 Integral waveform shaping circuit 2 ROM 3 Phase comparison error detection circuit 4 Amplification / waveform shaping circuit 5 Delay pulse creation circuit 6 PAL delay value memory 7 PAL delay value calculation circuit 8 NTSC delay value memory
Claims (1)
ジョン信号を録画再生するビデオテープレコーダにおい
て、 一方の方式のドラム位相基準信号(PG)からヘッド切
換パルス出力までの位相差をディジタル的数値で測定・
認識する測定・認識手段と、 前記ディジタル的数値をメモリーするメモリー手段と、 前記メモリー手段にメモリーされた数値を前記2方式の
テレビジョン信号間の垂直同期周波数の比に応じて演算
し他の方式の位相調整値を得る演算手段と、を有するヘ
ッド切換位相調整装置。1. A video tape recorder for recording and reproducing television signals of two systems such as NTSC and PAL, the digital phase difference from the drum phase reference signal (PG) of one system to the head switching pulse output. Measurement
Measuring / recognizing means for recognizing, memory means for memorizing the digital numerical value, numerical values memorized in the memory means are calculated according to a ratio of vertical synchronizing frequencies between the two types of television signals, and another method. And a calculation means for obtaining the phase adjustment value of the head switching phase adjustment device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05256791A JP3108570B2 (en) | 1993-10-14 | 1993-10-14 | Head switching phase adjustment device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05256791A JP3108570B2 (en) | 1993-10-14 | 1993-10-14 | Head switching phase adjustment device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07111661A true JPH07111661A (en) | 1995-04-25 |
JP3108570B2 JP3108570B2 (en) | 2000-11-13 |
Family
ID=17297497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP05256791A Expired - Fee Related JP3108570B2 (en) | 1993-10-14 | 1993-10-14 | Head switching phase adjustment device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3108570B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07115663A (en) * | 1993-10-19 | 1995-05-02 | Funai Electric Co Ltd | Rotary head changeover timing adjusting circuit |
JPH08172607A (en) * | 1994-09-29 | 1996-07-02 | Samsung Electron Co Ltd | Head switching automatic adjustment method of multiplex system vtr and its device |
-
1993
- 1993-10-14 JP JP05256791A patent/JP3108570B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07115663A (en) * | 1993-10-19 | 1995-05-02 | Funai Electric Co Ltd | Rotary head changeover timing adjusting circuit |
JPH08172607A (en) * | 1994-09-29 | 1996-07-02 | Samsung Electron Co Ltd | Head switching automatic adjustment method of multiplex system vtr and its device |
Also Published As
Publication number | Publication date |
---|---|
JP3108570B2 (en) | 2000-11-13 |
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