JPH07111476A - Direct spread spectrum communication receiver - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an apparatus suitable for downsizing, which is fast in code synchronization acquisition, inexpensive. A primary demodulation circuit 6 for recovering chip rate data RD 'and a chip rate clock RT' by detecting binary phase shift keying-modulated data after direct spread spectrum modulation, and this serial signal. Serial / parallel conversion circuit 7 for converting the chip rate data RD 'into parallel, a PN code setting circuit 9 for setting the same PN code as the PN code used for spreading in parallel, and a chip rate converted in parallel. The data and the PN code of the PN code setting circuit 9 are compared in parallel and a pulse is output when they match, and the chip rate clock RT 'is divided to divide the data rate clock R.
The secondary demodulation circuit 13 includes a clock reproduction circuit 11 for reproducing T and a data reproduction circuit 12 for reproducing the data RD by latching the output of the comparison circuit 8 with the reproduced data rate clock RT. To do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is provided to provide a direct spread spectrum communication (hereinafter referred to as DSS communication) receiving apparatus, which is suitable for speeding up synchronization of spread codes and being inexpensive and compact. And a receiver for DSS communication.

[0002]

2. Description of the Related Art FIGS. 3A and 3B are connection diagrams showing configurations of an example of a conventional direct spread spectrum communication transmitter and receiver, respectively. In the transmitting apparatus shown in FIG. 3A, 1 is a chip rate clock circuit, 2 is a transmitting side (spreading) PN code generating circuit which inputs a chip rate clock and outputs a PN (Pseudo Noise) signal, 3 is an SD
(Sending Date-Transmission data) A primary (spreading) modulation circuit for inputting a signal and a PN code to obtain a primary modulation output, 4 is a carrier generation circuit, 5 is a secondary input with a carrier output and a primary modulation output (BPSK binary phase shift keying (hereinafter B
PSK)) Modulation circuit, ST is a transmission timing clock. In the receiving device shown in FIG.
Is a reception side (for despreading) PN code generation circuit, 15 is a doubled chip rate clock circuit that outputs a clock twice the chip rate, 16 is a primary (despreading) demodulation circuit, and 17 is a reception side PN code generation circuit. A code synchronization acquisition circuit that controls the sliding (phase update) of the circuit 14, 18 is a code synchronization holding circuit that controls the frequency of the doubled chip rate clock circuit 15, and 19 is a secondary (BPSK) demodulation circuit, which is a binary phase shift circuit. The keying detection circuit (hereinafter referred to as the BPSK detection circuit) 19A and the data reproduction circuit 19B.

The operation of the conventional transmitter and receiver of the above construction will be described with reference to FIG. The chip rate clock output from the chip rate clock circuit 1 (see FIG. 4B) is input to the transmission side PN code generation circuit 2, and the PN code (1101) is output from this at the timing corresponding to the SD1 bit ( (See FIG. 4C). In the primary modulation circuit 3,
Multiply (spread) the SD signal (see FIG. 4 (a)) and the PN code.
If the SD signal is 1, the PN code inverter is output, and if the SD signal is 0, the PN code is output. As a result, the PN code inverter and the PN code are output from the primary modulation circuit 3 in accordance with the 1 and 0 patterns of the SD signal (see FIG. 4D). This primary modulation output is the output of the carrier generation circuit 4
Next modulation circuit 5 performs BPSK modulation. The double chip rate clock output from the double frequency chip rate clock circuit 15 (see FIG. 4E) is the receiving side PN code generation circuit 1.
4 and the reception side PN code is output therefrom (see FIG. 4 (f)). The PN code on the receiving side and the secondary modulation output are input to the primary modulation circuit 16, and a primary demodulation output is obtained from this.

The receiving side PN code does not have code synchronization with the transmitting side PN code in the state where no processing is initially performed (see section (f) in FIG. 4). Therefore, the code synchronization acquisition circuit 17 inputs the primary demodulation output and outputs one pulse of the slide signal to delay the phase of the PN code (reception side) by 1/2 chip to update the phase (section (f) in FIG. 4). reference).
However, since code synchronization has not been established yet, one pulse of the slide signal is output again and the phase of the PN code is updated (see section (f) in FIG. 4). Code synchronization is established here,
When the code synchronization acquisition ends, the code synchronization acquisition signal goes from the L level to the H level (see FIG. 4 (h)). When this code synchronization acquisition signal becomes H level, the code synchronization acquisition circuit 17 stops the output of the slide signal. The code synchronization holding circuit 18 is
The code synchronization acquisition signal from the code synchronization acquisition circuit 17 is monitored and does not operate during the L level (during code synchronization acquisition).
It operates only during the H level (end of code synchronization acquisition) and tries to control the double chip rate clock circuit 15. The BPSK of the secondary demodulation circuit 19 is first provided in the state where the code synchronization is established.
The detection circuit 19A and the data reproduction circuit 19B can reproduce the data and the reception clock (FIG. 4 (i),
(See (j)).

[0005]

However, in the above-described conventional example, the code synchronization is captured by halving the PN code on the receiving side.
Because it is realized by sliding each chip,
Not only does it take a long time to acquire the code synchronization, but the code synchronization acquisition circuit 17 and the code synchronization holding circuit 18 are complicated and the circuit scale tends to be large, so that it is difficult to realize an inexpensive and small device.

[0006]

In order to solve the above-mentioned problems, the apparatus of the present invention, as shown in FIG. 1, performs direct spread spectrum modulation and then binary phase shift keying-modulated data for binary phase shift keying detection. The primary demodulation circuit 6 for regenerating the chip rate data RD 'and the chip rate clock RT', and the serial / parallel conversion circuit 7 for converting the serial chip rate data RD 'into parallel data are used for spreading. A PN code setting circuit 9 in which the same PN code as the PN code is set in parallel, and a comparison circuit 8 which compares the chip rate data converted in parallel with the PN code of the PN code setting circuit 9 in parallel and outputs a pulse when they match. And a clock recovery circuit 11 for reproducing the data rate clock RT by dividing the chip rate clock RT ′, Latched by 8 data rate clock RT reproduced output of which characterized by comprising a secondary demodulation circuit 13 and a data reproducing circuit 12 for reproducing data RD.

[0007]

[Operation] The transmitted BPSK-modulated data is 1
The chip rate data RD 'and the chip rate clock RT' are reproduced by being input to the next demodulation circuit 6 and detected.
This serial chip rate data RD 'is serial /
The parallel chip rate data is input to the parallel conversion circuit 7 and converted into parallel. The parallel chip rate data and the PN code set in advance in the PN code setting circuit 9 are compared in parallel by the comparison circuit 8 and a pulse is output when they match. The chip rate clock RT 'is input to the clock reproduction circuit 11 and divided to reproduce the data rate clock RT. Further, the output of the comparison circuit 8 (pulse at the time of coincidence) is the data reproduction circuit 12
The data RD is reproduced by being latched by the data rate clock RT which is input to the clock reproduction circuit 11 and reproduced by the clock reproduction circuit 11.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1A and 1B are connection diagrams showing the configuration of one embodiment of a transmitter and a receiver for direct spread spectrum communication according to the present invention. The transmitter shown in FIG. 1A has the same configuration as the conventional transmitter shown in FIG. 6 in the receiving device shown in FIG.
Is a primary demodulation circuit composed of a BPSK detection circuit 6A for BPSK-detecting BPSK-modulated data to reproduce chip rate data RD 'and a chip rate clock recovery circuit 6B for reproducing chip rate clock RT', and 7 is a serial chip A serial / parallel conversion circuit for converting the rate data RD 'into parallel, 9 is the P used for spreading
A PN code setting circuit in which the same PN code as that of the N code generating circuit 2 is set in parallel, and 8 compares the chip rate data converted in parallel with the PN code of the PN code setting circuit 9 in parallel, and when they match, A comparison circuit for outputting one pulse, 10 is a reset pulse circuit for producing a reset pulse from the output of the comparison circuit 8, 11 is a clock reproduction circuit for dividing the chip rate clock RT 'under the control of the reset pulse to reproduce the clock, 12 Is a data reproducing circuit for latching the output pulse of the comparing circuit 8 with the reproduced data rate clock RT and reproducing the data RD. Serial / parallel conversion circuit 7, comparison circuit 8, PN code setting circuit 9, reset pulse circuit 10, clock recovery circuit 1
A secondary demodulation circuit 13 is constituted by 1 and the data reproduction circuit 12.

The operation of the transmitting apparatus and the receiving apparatus of the present invention having the above configuration will be described with reference to FIG. Chip rate clock circuit 1
Output chip rate clock (see Figure 2 (b))
Is input to the PN code generation circuit 2, and the PN code (1101) is output from this at the timing corresponding to the SD1 bit (see FIG. 2C). In the primary modulation circuit 3, S
The D signal (see FIG. 2A) is multiplied (spread) by the PN code, and if the SD signal is 1, the inverter of the PN code is output,
If it is 0, a PN code is output. As a result, the inverter of the PN code and the PN code are output from the primary modulation circuit 3 corresponding to the pattern of 1 and 0 of the SD signal (see FIG. 2D). This primary modulation output is the output of the carrier generation circuit 4
Next modulation circuit 5 performs BPSK modulation.

The transmitted BPSK-modulated data is input to the BPSK detection circuit 6A and the chip rate clock reproduction circuit 6B of the primary demodulation circuit 6 and detected to reproduce the chip rate data RD 'and the chip rate clock RT'. (See FIGS. 2C and 2H). The serial chip rate data RD 'is input to the serial / parallel conversion circuit 7 and converted into parallel, and the parallel chip rate data (see FIG. 2 (f)) and the PN code set in the PN code setting circuit 9 in advance. Are compared in parallel by the comparison circuit 8, and if they match, the output of the comparison circuit 8 changes from H level to L level (see FIG. 2 (g)). The L level output of the comparison circuit 8 is input to the reset pulse circuit 10 to create a reset pulse (see FIG. 2 (i)). The chip rate clock RT '(see FIG. 2 (h)) is input to the clock regeneration circuit 11 and divided according to the reset pulse to regenerate the data rate clock RT (see FIG. 2 (j)). Further, the L level output of the comparison circuit 8 is input to the data reproduction circuit 12 and latched by the data rate clock RT reproduced by the clock reproduction circuit 11 to obtain the data RD.
Will be reproduced (see FIG. 2 (k)).

[0011]

As described above in detail, according to the present invention, since the data is first demodulated to the chip rate stage and then the code correlation is digitally checked collectively, the code synchronization is quickly acquired and the cost is low. Thus, it is possible to provide a device suitable for miniaturization.

[Brief description of drawings]

1A and 1B are connection diagrams showing the configurations of an embodiment of a transmitter and a receiver for direct spread spectrum communication according to the present invention, respectively.

FIG. 2 is an operation explanatory diagram of the transmission device and the reception device of the present invention.

3 (A) and 3 (B) are connection diagrams showing configurations of an example of a conventional direct spread spectrum communication transmitter and receiver, respectively.

FIG. 4 is an operation explanatory diagram of a conventional transmitter and receiver.

[Explanation of symbols]

 1 Chip Rate Clock Circuit 2 (Transmission Side) PN Code Generation Circuit 3 Primary Modulation Circuit 4 Carrier Generation Circuit 5 Secondary Modulation Circuit 6 Primary Demodulation Circuit 6A BPSK Detection Circuit 6B Chip Rate Clock Recovery Circuit 7 Serial / Parallel Conversion Circuit 8 Comparison circuit 9 PN code setting circuit 10 Reset pulse circuit 11 Clock recovery circuit 12 Data recovery circuit 13 Secondary demodulation circuit

Claims (1)

[Claims] 1. A primary demodulation for recovering chip rate data (RD ') and chip rate clock (RT') by binary phase shift keying detection of data which has been subjected to binary phase shift keying modulation after direct spread spectrum modulation. The circuit (6) and this serial chip rate data (R
Serial / parallel conversion circuit (7) for converting D ') to parallel, PN code setting circuit (9) for setting the same PN code as the PN code used at the time of spreading in parallel, and chip converted in parallel A comparison circuit (8) for comparing the rate data and the PN code of the PN code setting circuit (9) in parallel and outputting a pulse when they match, and a chip rate clock (RT ') for dividing the data rate clock (RT).
And a clock recovery circuit (11) for reproducing the data and a data rate clock (R
A receiver for a direct spread spectrum device, comprising a secondary demodulation circuit (13) comprising a data reproduction circuit (12) for latching at (T) and reproducing data (RD).