JPH07111450A - Deep submicron mosfet output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of the buffer circuit, by generating a gate voltage only when a pull-up element is turned on and applying the voltage to the pull-up element to save power consumption of a voltage generating circuit. CONSTITUTION:When a level of an input terminal Ti is at a high level, a pull- down element comprising MOSFETs 21, 22, connected in series is turned on to secure a drain breakdown voltage and a pull-up element comprising MOSFETs 11, 12 is turned off. In this case, the level of the input terminal of a gate voltage generating circuit 50 goes to low level and a low power supply voltage 2V of the MOSFET 12 is applied and a MOSFET 42 is turned off to stop the operation of the voltage generating circuit. Thus, when the pull-up element is turned off, the power consumption of the gate voltage generating circuit is reduced to reduce the power consumption of the output buffer circuit of the deep submicron MOSFET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a channel length of 0.5 μm.
So-called deep submicron MOSFE below m
The present invention relates to a semiconductor output buffer circuit using T.

[0002]

2. Description of the Related Art Due to high integration of MOS LSI, MO
The SFET is miniaturized, the breakdown voltage is lowered by this miniaturization, and the long-term practice of setting the power supply voltage to 5V is breaking down. That is, C having a channel length of 0.5 μm
Power supply voltage is 3.3V or 3V for MOS circuit
It is becoming a policy to In the following description, the power supply voltage will be 3.3 V as a representative.

In the deep submicron region where the channel length is less than 0.5 μm, the breakdown voltage is about 2 V, and the value of the power supply voltage is determined by this.

However, deep submicron MOSL
Even if the SI power supply voltage is 2V, it is necessary to coexist with the conventional LSI having a power supply voltage of 3.3V in the system environment in which the LSI is placed. It is necessary to interface with an LSI whose power supply voltage is 3.3V.

Standards called LVTTL and LVCMOS are being formed as interfaces for a 3.3V power supply voltage. The high level voltage V _OH of the output buffer circuit in the LVTTL and LVCMOS standards is V _OH ≥2.4 V and V _OH , respectively. _OH ≧ 3.2V.

[0006]

There are two problems with the breakdown voltage of the device: the drain breakdown voltage of the MOSFET and the gate breakdown voltage.

The drain breakdown voltage of the MOSFET is MO
This is the breakdown voltage between the drain and the source of the SFET, and if a voltage exceeding this breakdown voltage is applied between the drain and the source, the device performance is deteriorated due to hot carriers. Further, the gate breakdown voltage is a breakdown voltage between the gate and the source or between the gate and the drain, and when a voltage exceeding this breakdown voltage is applied between the gate and the source or between the gate and the drain, TDDB (time-dependent dielectric breakdown). )
This leads to the destruction of the gate oxide film thickness.

If a deep sub-micron MOS LSI is used only with a power supply voltage of 2V, even if a CMOS circuit is used,
Since the maximum value of the output voltage of the output buffer circuit is suppressed to 2V, the standard of the high level voltage V _OH of LVTTL and LVCMOS cannot be satisfied.

Therefore, in order to make the interface compatible with LVTTL and LVCMOS, it is necessary to apply 3.3V to the deep submicron MOSFET output buffer circuit and generate a high level voltage of the output buffer circuit from this power supply voltage. . That is, 2V, 3.3V
It is necessary to use a dual power source.

FIG. 3 is a diagram showing a conventional example of an output buffer circuit using a dual power source.

Although not shown in the figure, the first power supply voltage 2V is connected to the gate of the n-ch MOSFET 82, and the second power supply voltage 3.3V is applied to the circuit constituting the drive stage. . MOSFET 71 connected in series,
A pull-up element is constituted by 72, and a pull-down element is constituted by MOSFETs 81 and 82 connected in series. By thus connecting two MOSFETs in series, the voltage applied to one MOSFET is divided and this divided voltage is divided. The drain withstand voltage is ensured by setting the voltage value below the drain withstand voltage.

In the above conventional example, the following measures are taken to secure the gate breakdown voltage.

Of the MOSFETs connected in series, a logic signal is applied to the MOSFETs 71, 81 near the power supply or ground line side, and the bias voltage is constantly applied to the MOSFETs 72, 82 near the output terminal of the MOSFETs connected in series. . Further, in order to satisfy the breakdown voltage, the gate breakdown voltage (that is, breakdown voltage between the gate and the source or between the gate and the drain) V _{B is set} to 2 V, and the high level voltage V _H of the output buffer circuit is set to the second power supply voltage 3.3 V. They are made equal, and the low level voltage V _L of the output buffer circuit is set to the ground voltage (that is, 0 V).

Further, V _GN is a gate bias voltage of the n-ch MOSFET 82, and V _GP is a p-ch MOSFET.
When the gate bias voltage of 72 is applied, when the output terminal of the output buffer circuit is in the high state or the low state,
If the absolute value of the voltage between the source and the voltage between the gate and the drain is within 2 V, it is within the range of the gate breakdown voltage V _B.
The following relationship holds. | V _H −V _GN | ≦ V _B , | V _L −V _GN | ≦ V _B | V _H −V _GP | ≦ V _B , | V _L −V _GP | ≦ V _B Therefore, 1.3 is calculated. ≤ V _GN ≤ 2, 1.3
V ≦ V _GP ≦ 2.

In the above conventional example, in order to secure the driving force of the pull-up element and the driving force of the pull-down element,
It is preferable that the absolute values of the gate voltages of the MOSFETs 72 and 82 are large. That is, the higher the gate bias voltage V _GN of the n-ch MOSFET 82 is, the better the p-ch MOSF.
Since the lower the gate bias voltage V _GP of the ET72 is, the better, V _GP = 1.3 V and V _GN = 2 V are better.

Here, these bias voltages V _GP , V _GN
How to create is a problem. That is, n-c
2V of gate bias voltage V _GN of hMOSFET 82
Can be used as is because it is the first power supply voltage,
The gate bias voltage V _GP of 1.3 V of the p-ch MOSFET 72 must be generated from the first power supply (2 V) or the second power supply (3.3 V), and therefore,
The gate bias voltage V of this p-ch MOSFET 72
There is a problem that useless power consumption occurs in the gate voltage generation circuit that generates _GP .

On the other hand, in order to save power, p-ch MOS
When 2V is applied as the gate bias voltage V _GP of the FET 72, the driving force of the p-ch MOSFET 72 decreases,
Therefore, there is a problem that the driving force is reduced in the entire pull-up element including the p-ch MOSFETs 71 and 72. That is, in the above conventional example,
There is a trade-off between reducing power consumption and not reducing the driving force of the pull-up element.

The present invention is a deep submicron MOSF.
An object of the present invention is to provide a deep sub-micron MOSFET output buffer circuit that can reduce the power consumption without reducing the driving force of the pull-up element that constitutes the ET output buffer circuit.

[0019]

According to the present invention, the gate voltage generating circuit is operated only when the pull-up element is turned on, and the gate voltage generating circuit generates the voltage, for example, 1.3.
When V is applied to the pull-up element and the pull-up element is off, the gate voltage generating circuit is stopped and a voltage of 2 V, which is the first power supply, is applied to the pull-up element.

[0020]

According to the present invention, the pull-up element is turned off in the output buffer circuit for applying the bias voltage to the gate of the MOSFET close to the output terminal of the two p-ch MOSFETs connected in series in order to secure the drain breakdown voltage. At this time, the gate voltage generating circuit that generates the bias voltage is stopped, and the first power supply, for example, 2V is applied to the pull-up element. Therefore, when the pull-up element is off, the gate voltage generating circuit is turned off. Power consumption is reduced, therefore deep submicron MOS
The power consumption of the FET output buffer circuit can be reduced.

[0021]

1 is a circuit diagram showing a deep submicron MOSFET output buffer circuit according to a first embodiment of the present invention.

In this first embodiment, the voltage of the low voltage power source is 2V.
And a high-voltage power supply voltage of 3.3V are used, and the device withstand voltage is 2V or more and less than 3.3V.
Deep submicron M using 1, 12, 21, 22
OSFET output buffer circuit.

Further, the first p-ch MOSFET 11 and the second p-ch MOSFET 12 are connected in series to each other to form a pull-up element, and the first n-ch MO
The SFET 21 and the second n-ch MOSFET 22 are connected in series with each other to form a pull-down element.
By the pull-up element and the pull-down element,
The drive stage of the deep submicron MOSFET output buffer circuit is constructed.

Specifically, the first p-ch MOSFET
The source of 11 is connected to the high voltage power supply, and the first p-
The drain of the chMOSFET 11 and the second p-ch MO
The second p-chM is connected to the source of the SFET12.
The drain of the OSFET 12 and the second n-ch MOSFE
T22 drain is deep submicron MOSF
It is connected to the output terminal T _o of ET output buffer circuit, the second
Source of the n-ch MOSFET 22 and the first n-ch
The drain of the MOSFET 21 is connected to the first n-
The source of the chMOSFET 21 is connected to the ground line side.

Further, in the first embodiment, the first p-ch MO is connected via the inverters INV1 and INV3.
A logic signal is applied to the gate of the SFET 11, and the first n-ch MO is passed through the inverters INV1 and INV2.
A logic signal is applied to the gate of the SFET 21.

The inverter INV3 is an inverter having a level conversion function and has an output level of 1.3V and 3.3V.
It changes to. That is, the inverter INV3
Signal level of 2V CMOS to the first p-ch MO
It is an inverter having a function of converting to the signal level of the SFET 11, and outputs 3.3V of high level when the input terminal is at low level (0V), and outputs low when the input terminal is at high level (2V). It outputs a level of 1.3V.

The gate voltage generating circuit 50 is a circuit for generating a voltage lower than the voltage 2V of the low voltage power source, for example 1.3V, by using the voltage 3.3V of the high voltage power source and the voltage 2V of the low voltage power source. , P-ch MOSFET 32, and n-
It is composed of chMOSFETs 41 and 42. Then, the first p-ch MOSFET 11 and the second p-ch
When the pull-up element composed of the MOSFET 12 and the MOSFET 12 should be turned on, the gate voltage generation circuit 50 operates and 1.
When 3V is generated and the pull-up element should be turned off, the gate voltage generation circuit 50 stops and outputs 2V.

The gate of the second p-ch MOSFET 12 is connected to the output terminal of the gate voltage generating circuit 50, and the voltage of the low voltage power supply 2V is applied to the gate of the second n-ch MOSFET 22.

Further, the input terminal T _{i of the} output buffer circuit
Through the inverter INV1 and the inverter INV3
, An input terminal of the inverter INV2, and an input terminal of the gate voltage generation circuit 50.

Next, the operation of the first embodiment will be described.

First, when the input terminal T _i of the output buffer circuit is at low level, the first p-chMOSFE is used.
Since the gate of T11 goes low, the first pc
The hMOSFET 11 is turned on, and the first n-ch MOSF
The gate of ET21 also goes low, so the first n-
The chMOSFET 21 is turned off.

At this time, since the output terminal of the inverter INV1 is at the high level, the input terminal of the voltage generating circuit 50 becomes at the high level, and n in the gate voltage generating circuit 50 is reached.
-Ch MOSFET 42 turns on, and p-ch MOSFE
T32 turns off. Further, since the gate voltage of the n-ch MOSFET 41 is the first power supply voltage 2V, the n-ch
MOSFET 41 is always on, which is why the second p
The potential of the gate of the -ch MOSFET 12 is n-chM
The voltage is determined by the ratio of the ON resistances of the OSFETs 41 and 42.

Here, the second p-ch MOSFET 12
N-chMO so that the potential of the gate of
The channel widths of the SFETs 41 and 42 are set. At this time, current flows from the second power supply (3.3 V) through the n-ch MOSFETs 41 and 42, and power consumption is generated.

By doing so, the second p-ch MOS is formed.
Since the gate voltage of the FET 12 becomes 1.3 V, the second p-ch MOSFET 12 is sufficiently turned on, and the p-chM
Pull-up function of the pull-up device that is configured is turned on in OSFET11 12 and pull-down function of the pull-down element in order to be turned off, the output terminal T _o of the output buffer circuit is maintained at a high level.

On the other hand, when the input terminal T _i of the output buffer circuit is at high level, the first n-ch MOSFET 21
Of the first n-ch MOSFET 21 and the gate of the first p-ch MOSFET 11 become high level.
Turns on and the first p-ch MOSFET 11 turns off. That is, the pull-down element composed of the n-ch MOSFETs 21 and 22 is turned on, and the p-ch MOSFET is
The pull-up element composed of 11 and 12 is turned off.

At this time, since the output terminal of the inverter INV1 becomes low level, the input terminal of the gate voltage generating circuit 50 becomes low level and the n-ch MOSFET 4
2 turns off, the p-ch MOSFET 32 turns on, and the second
The gate of the p-ch MOSFET 12 is maintained at the first power supply voltage 2V. At this time, the n-ch MOSFET
The drain and gate of 41 are both 2V with respect to the ground potential.
Therefore, the n-ch MOSFET 41 is turned off. That is, since no current flows in the gate voltage generation circuit 50, power consumption in the gate voltage generation circuit 50 does not occur. Therefore, the power consumption of the entire output buffer circuit can be reduced.

[0037] In this case, the pull-up device is turned off and the pull-down device is turned on, the output terminal T _o of the output buffer circuit becomes low level.

FIG. 2 is a circuit diagram showing a deep submicron MOSFET output buffer circuit according to the second embodiment of the present invention.

The second embodiment is an example of a 3-state (tri-state) output buffer circuit, and is basically the first embodiment.
This is the same as the embodiment, but the inverter INV1 in the first embodiment is deleted and an inverter INV4, a NOR gate 61, and a NAND gate 62 are added.

That is, the inverter INV4 inverts the enable signal of the enable terminal T _e1 and supplies it to the NOR gate 61. The NOR gate 61 inverts the logic signal from the input terminal T _i1 of the output buffer circuit and the inverter INV4. The NAND gate 62 receives the output signal from the input terminal T _i1 and the logic signal from the input terminal T _i1 .
It is supplied to the inverter INV2. The second
The gate voltage generation circuit 50 in the embodiment inputs the output signal of the NOR gate 61.

Next, the operation of the second embodiment will be described.

First, when the signal at the enable terminal T _e1 is at a high level, the gate of the first p-ch MOSFET 11, the input terminal of the gate voltage generating circuit 50, the first n-th channel.
The gate of the -ch MOSFET 21 operates in the same manner as in the first embodiment. That is, the same operation as that of the output buffer circuit of the first embodiment is performed for the signal level of the input terminal T _i1 of the output buffer circuit.

On the other hand, when the enable terminal T _e1 is at the low level, the gate of the first p-ch MOSFET 11 becomes the high level regardless of the level of the input terminal T _i1 of the output buffer circuit, and the first n-ch MOSFET.
The gate of 21 goes low. That is, the first p
-Ch MOSFET 11, first n-ch MOSFET
21 is in the off state, that is, both the pull-up element and the pull-down element are turned off, so that the output terminal _To1 of the output buffer circuit realizes a high impedance state.

At this time, the input terminal of the gate voltage generating circuit 50 becomes low level, and the second p-chMOSFE is turned on.
Since the first power supply voltage 2V is applied to the gate of T12 and no current flows in the gate voltage generation circuit 50, power consumption in the gate voltage generation circuit 50 does not occur. Therefore, the power consumption of the entire output buffer circuit can be reduced.

That is, in the second embodiment, _when the output terminal _To1 of the 3-state output buffer circuit is in the low level state and in the high impedance state,
There is no power consumption in the gate voltage generation circuit 50, and power consumption occurs only when the output terminal _To1 of the three-state output buffer circuit is at a high level, so that it is possible to reduce the power consumption of the entire circuit.

[0046]

According to the present invention, of the two p-ch MOSFETs connected in series in order to secure the drain breakdown voltage, the pull-up is performed in the output buffer circuit for applying the bias voltage to the gate of the MOSFET close to the output terminal. When the element is off, the gate voltage generating circuit for generating the bias voltage is stopped and the first power source, for example, 2V is applied to the pull-up element.
When the pull-up element is off, the power consumption of the gate voltage generation circuit is reduced, and therefore, the power consumption of the deep submicron MOSFET output buffer circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a deep sub-micron MOSFET output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a deep sub-micron MOSFET output buffer circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a conventional example of an output buffer circuit using a dual power supply.

[Explanation of symbols]

11 ... 1st p-ch MOSFET, 12 ... 2nd p-ch MOSFET, 21 ... 1st n-ch MOSFET, 22 ... 2nd n-ch MOSFET, 32 ... p-ch MOSFET, 41, 42 ... n-ch MOSFET, 50 ... Gate voltage generating circuit, 61 ... NOR gate, 62 ... NAND gate, INV1, INV2, INV4 ... Inverter, INV3 ... Inverter with level conversion function, T _i , T _i1 ... Input terminal of deep submicron MOSFET output buffer circuit, T _o, T _o1 ... output terminal of the deep sub-micron MOSFET output buffer circuit, T _e ... enable terminal.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 19/003 E

Claims (1)

[Claims] 1. Two p-chMs connected in series with each other
The OSFET is used as a pull-up element in the driving stage, two n-ch MOSFETs connected in series are used as pull-down elements in the driving stage, and the two p-
Among the chMOSFETs, a gate of a p-chMOSFET provided on the power supply side of a predetermined high voltage and the two n
-In the p-channel MOSFET, the p- provided on the ground line side
A logic signal is applied to the gate of the ch-MOSFET, and the breakdown voltage of the p-ch MOSFET and the n-ch MOSFE
A deep sub-micron MOSFET whose breakdown voltage of T is both lower than the above high voltage and higher than a predetermined low voltage.
In the output buffer circuit, when the pull-up element should be turned on, it operates to generate a voltage below the low voltage, and when the pull-up element should be turned off, the gate is stopped to output the low voltage. A voltage generating circuit is provided, and the output terminal of the gate voltage generating circuit is connected to the gate of the p-ch MOSFET provided on the output terminal side of the deep submicron MOSFET output buffer circuit of the two p-ch MOSFETs, Of the two n-ch MOSFETs, the low voltage is applied to the gate of the n-ch MOSFET provided on the output terminal side of the deep sub-micron MOSFET output buffer circuit, and the deep sub-micron M is characterized in that
OSFET output buffer circuit.