JPH07111093A - Negative voltage generator - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a negative voltage generation circuit in which the negative voltage generation speed does not decrease even in the second and subsequent operations. [Structure] P-channel MOS transistor is continuously connected,
In a negative voltage generation circuit that connects a capacitive element to each connection node and drives a clock signal to one end of the capacitive element to generate a negative voltage, a reset means 92 for resetting the other end of the capacitive element to a predetermined voltage level is provided. Have

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a negative voltage generating circuit. In particular, the present invention relates to a negative voltage generation circuit for driving a word line to a negative potential during erasing in a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Among nonvolatile semiconductor memory devices, EEPROM capable of electrically rewriting and erasing data is an EEPROM.
Are currently classified into NOR type and NAND type. Most NOR type cells use a stack cell in which a floating gate and a control gate are stacked, and writing is performed by injecting electrons into the floating gate by hot carriers.
Erasing is performed by applying, for example, 15 V to the source and 0 V to the control gate, and passing an FN tunnel current between the floating gate and the source to emit electrons.

Recently, a non-volatile semiconductor memory device of a type has been developed in which erasing is performed by driving a word line to a negative potential at the time of erasing, which is called a "gate negative voltage erasing type". In this, by applying, for example, -10 V to the word line connected to the control gate and 5 V to the source, a potential difference similar to that in the above-described example is given between the control gate and the source for erasing. The advantage of this method is that the voltage applied to the source during erase is low,
The junction breakdown voltage on the source side of the memory cell may be low, and optimization such as making the depth of the source side diffusion layer deeper than that of the drain side or lowering the impurity concentration of the source side diffusion layer becomes unnecessary, and the gate of the cell The point is that the length can be shortened. This leads to high integration and large capacity. The example of the gate negative voltage erase type is already ISSCC 89 pp132-133, "A 5V-Onl
y 256K Bit CMOS Flash EEPROM "S.D'Arrigo et al,
It is disclosed in JP-A-5-28784.

In order to operate the gate negative voltage erasing type non-volatile semiconductor memory device with a single power source (for example, 5 V), it is necessary to integrate a negative voltage generating circuit on a chip. Conventionally, a negative voltage generation circuit that continuously connects P-channel MOS transistors, connects a capacitive element to each connection node, and drives a clock signal at one end of the capacitive element to generate a negative voltage is known as a preferable one. Has been.

However, the conventional negative voltage generating circuit has a problem that the negative voltage generating speed is lowered in the second and subsequent operations because an extra charge remains in each connection node after the operation. As a result, when this negative voltage generating circuit is applied to a nonvolatile semiconductor memory device, there arises a problem that the erasing time becomes slightly longer.

[0006]

As described above, the conventional negative voltage generation circuit has a problem that the negative voltage generation speed decreases in the second and subsequent operations because extra charge remains in each connection node after the operation. was there. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the above-mentioned drawbacks and provide a negative voltage generation circuit in which the negative voltage generation speed does not decrease even in the second and subsequent operations.

[0007]

In order to solve the above-mentioned problems, in the present invention, a P-channel MOS transistor is continuously connected, a capacitive element is connected to each connection node, and a clock signal is applied to one end of the capacitive element. Provided is a negative voltage generation circuit which generates a negative voltage by driving, and is provided with reset means for resetting the other end of the capacitive element to a predetermined voltage level.

The reset means includes a common wire, a backflow preventing means connected between the common wire and the other end of the capacitive element, and a switch for charging and discharging the common wire to a predetermined voltage level according to a reset signal. And a common line that is in a floating state when a negative voltage is generated.

[0009]

When the means provided by the present invention is used, since it has a reset means for resetting the other end of the capacitive element to a predetermined voltage level, by charging and discharging extra residual charge after the operation, the second and subsequent operations are performed. In this case, the negative voltage generation can be started from the same state as the first operation, and as a result, it is possible to provide the negative voltage generation circuit in which the negative voltage generation speed does not decrease in the second and subsequent operations. .

Further, by providing the backflow prevention means connected between the common wiring which is in a floating state when a negative voltage is generated and the capacitive element, the reset operation can be performed by one switch means even in the multi-stage charge pump circuit. It is possible to let This contributes to reducing the chip area.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall circuit configuration of a nonvolatile semiconductor memory device using the negative voltage generating circuit of the present invention. That is, the memory cell array 1, the row decoder 2, the source decoder 3, the column decoder 4, the column gate 5, the sense amplifier 6, the address buffer 7, the control circuit 8, the negative voltage generation circuit 9, and the booster circuit. 10 and an input / output buffer 11.

The memory cell array 1 is a floating gate type MOS.
Memory cell transistor M composed of a transistor
C are arranged in a matrix. The control gates of the memory cell transistors belonging to the same row are connected to the word line WL, the sources are connected to the common source line SL, and the drains of the memory cell transistors belonging to the same column are connected to the bit line BL. ing.

The row decoder 2 selects a word line WL designated by a row address in the external addresses A0 to A18 input to the address buffer 7 and drives it to a predetermined potential according to each operation mode. Similarly, the source decoder 3 selects the common source line SL designated by the block address in the external addresses A0 to A18, and drives it to a predetermined potential according to each operation mode.

The column decoder 4 has external addresses A0-A.
The bit line BL designated by the column address in 18 is selected, and the column gate 5 connects the designated bit line to the sense amplifier 6.

The control circuit 8 gives a control signal to each internal circuit block according to a control signal input from the outside, for example, / CE, / WE, etc., and controls each mode such as reading, writing, and erasing.

The negative voltage generating circuit 9 is a circuit for generating a negative voltage for driving the word line at the time of erasing. As will be described later, the charge pump circuit 91 and the reset circuit 9 are provided.
2. The clock generator circuit 93 is provided to supply the negative voltage power supply VBB to the row decoder.

The booster circuit 10 is a circuit for generating a boosted voltage for driving a bit line, a word line, etc. at the time of writing, is composed of a charge pump circuit 101 and a clock generation circuit 102, and has a row decoder having a negative voltage power supply VBB. To supply.

During the read operation, the input / output buffer 11 further amplifies the read signal amplified by the sense amplifier 6 and outputs it to the outside of the chip. In addition, during a write operation, write data input from the outside is input to the inside of the chip.

FIG. 2 is a detailed circuit diagram of the charge pump circuit 91 and the reset circuit 92. The charge pump circuit 91 includes P-channel type MOS transistors Q11, Q12, Q13 and Q14 which are continuously connected, capacitive elements C11, C12, C13 and C14 which are connected to respective connection nodes, and transistors Q11, Q12, Q13 and Q14. P-channel type MOS transistors Q21, Q22, Q23, Q24, whose sources and gates are connected to each other and whose gates are connected to the connection nodes of the capacitive elements C11, C12, C13, C14, and the transistors Q11, Q12,
Capacitance element C2 connected to the gates of Q13 and Q14, respectively
1, C22, C23, C24 and an output transistor Q30 for backflow prevention.

At the other end of each capacitive element, C12 and C14 are clock signals φ1, C21 and C23 are clock signals φ2, and C11 is C11.
The clock signal φ3 is input to C13 and C13, and the clock signal φ4 is input to C22 and C24.
P-channel MOS transistors Q31, Q32, Q33, Q34 connected to one ends of 1, C12, C13, C14 and P-channel MOS transistors Q41, Q42 connected to one ends of capacitive elements C21, C22, C23, C24, Q43, Q44 and each transistor Q31, Q32, Q33, Q34, Q41, Q42, Q4
3, a common wiring 929 connected to the other end of Q44, an N-channel MOS transistor Q51 and a P-channel MOS transistor connected in series between the common wiring 929 and the power supply potential Vcc
It consists of a transistor Q50.

Each of the transistors Q31, Q32, Q33, Q34,
The gates of Q41, Q42, Q43, and Q44 are connected to the connection terminal with the capacitive element, and the gate of the transistor Q51 is at the ground potential V.
The reset signal inverted by the inverter 921 is input to SS at the gate of the transistor Q50.

FIG. 3 (a) is a circuit configuration diagram of the clock generation circuit 93, and FIG. 3 (b) is its output φ1, φ2, φ.
A time chart of 3 and φ4 is shown. Clock generation circuit 9
Reference numeral 3 includes an oscillation circuit 931, a counter circuit 932, and a decoder circuit 933.

Next, the operation of the embodiment will be described.
When an erase signal (or erase command) is input from the outside, the control circuit 8 starts control of the erase operation, and in response to this, the negative voltage generation circuit 9 enters the reset operation. When the Reset signal becomes "H", "L" (0V) is applied to the gate of the transistor Q50 by the inverter 921. As a result, the drain potential of the transistor Q50 rises to 5V. In response to this, the common wiring 929 rises to a negative voltage by the threshold value of the transistor Q51 (it has a negative potential before that). If the threshold value of the transistor Q51 is 1V, the common line 929 becomes -1V. As a result, the connection nodes of the charge pump circuit 91 are connected to the transistors Q31, Q32, Q33, Q34, Q41, Q42,
It is charged and discharged to a predetermined potential via Q43 and Q44. When a predetermined reset time has elapsed, the Reset signal becomes "L", and the source / drain of the transistor Q51 and the common wiring 929 are connected.
Becomes floating.

Subsequently, the clock signal shown in FIG. 3B is applied to the other end of each capacitive element. Then, the negative voltage generating operation starts, and a negative potential is output to the VBB terminal.
Since the negative voltage generating operation is already well known, its explanation is omitted. Since the common wiring 929 is also driven to a negative potential during the negative voltage generating operation, the backflow preventing transistors Q31, Q32, Q33, Q34, Q41, Q42, Q43, Q44.
Are all off. As a result, the reset circuit 92 is disconnected from the charge pump circuit 91 and does not affect the negative voltage generating operation.

This negative potential is input to the row decoder 2,
A drive transistor in a row decoder (not shown) drives the selected word line to a negative potential. In the erase operation, the selected common source line is also simultaneously driven to a positive potential (boosted potential or power supply potential).

When the erase operation is performed in small steps with the verify operation interposed therebetween, the above steps are repeated a plurality of times. As described above, since the reset operation is performed immediately before the negative voltage generation operation, by charging and discharging the extra residual charge after the operation, even in the second and subsequent operations, the same voltage as the first operation is applied to the negative voltage. Generation can be started, and as a result, it is possible to provide a negative voltage generation circuit in which the negative voltage generation speed does not decrease even in the second and subsequent operations.

The effect of the present invention is shown in FIG. this is,
The capacitance of each capacitive element is 2.5 pF, and transistors Q11 and Q1
When the W / L of 2, Q13 and Q14 is set to 200/2 and the W / L of transistors Q21, Q22, Q23 and Q24 is set to 50/2, the speed of negative potential generation after the second time depending on the presence or absence of the reset operation. The results are compared by simulation. Thus, it can be seen that the reset operation improves the negative potential generation speed after the second time.

Next, a modified example of the embodiment of the present invention is shown in FIG. [FIG. 5] (a) shows transistors Q31, Q32, Q33, Q34, Q41, Q42, Q43 as backflow prevention elements,
Diodes D1, D2, D3, D4, D instead of Q44
In this example, 5, D6, D7 and D8 are used. Since the operation is almost the same as that of the above-mentioned embodiment, its explanation is omitted. Since the diode is used, the circuit can be constructed in a small space.

FIG. 5B is an example in which the reset circuit 92 is divided into a plurality of circuit blocks 922, and a switching transistor Q50 and a level shift transistor Q51 are provided in each circuit block 922. Since the operation is almost the same as that of the above-mentioned embodiment, its explanation is omitted. Since it is not necessary to charge and discharge the common wiring 929 during the negative voltage generating operation, the operation speed is increased.

[0030]

By using the present invention, a negative voltage generating circuit is provided in which the negative voltage generating speed does not decrease even in the second and subsequent operations.

[Brief description of drawings]

FIG. 1 is an overall circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a negative voltage generating circuit according to an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a clock generation circuit according to an embodiment of the present invention.

FIG. 4 is a graph showing the effect of the embodiment of the present invention.

FIG. 5 is a circuit configuration diagram showing a modified example of the present invention.

[Explanation of symbols]

 1 Memory Cell Array 2 Row Decoder 3 Source Decoder 4 Column Decoder 5 Column Gate 6 Sense Amplifier 7 Address Buffer 8 Control Circuit 9 Negative Voltage Generation Circuit 10 Booster Circuit 11 Input / Output Buffer

Claims (2)

[Claims] 1. A negative voltage generation circuit for continuously connecting a P-channel MOS transistor, connecting a capacitive element to each connection node, and driving a clock signal to one end of the capacitive element to generate a negative voltage, wherein: A negative voltage generating circuit comprising reset means for resetting the other end of the element to a predetermined voltage level. 2. The reset means charges a common wire, a backflow preventing means connected between the common wire and the other end of the capacitive element, and charges the common wire to a predetermined voltage level in response to a reset signal. A negative voltage generating circuit, comprising: discharging switch means, wherein the common wiring is in a floating state when a negative voltage is generated.