JPH07106962A - High speed analog PLL circuit and temperature compensation method for preset value in high speed analog PLL circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a high-speed analog PLL circuit that can follow the environmental temperature and perform phase lock with a constant and short lock-up time. A PLL synthesizer circuit 1, a voltage controlled oscillator 2, storage means for storing a control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator, a control voltage initial set value F2 read from the storage means, and a circuit 1 A voltage adder 3 for adding the control voltage Ve based on the phase comparison result of
Control voltage of the voltage controlled oscillator stored in the storage device by using the control voltage after phase lock of the PLL circuit −
A high-speed analog PLL circuit provided with means 6 and 4 for updating the oscillation frequency characteristic curve to the control voltage-oscillation frequency characteristic curve corresponding to the actual environmental temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog PLL circuit, and more particularly to a high-speed analog PLL circuit adapted to enable phase lock at high speed. The present invention is a high-speed analog PLL circuit configured to obtain a short lock-up time, such as an analog PLL circuit used in a device such as a mobile communication terminal. -A high-speed analog PLL circuit in which the oscillation frequency characteristic curve is changed so that a constant short lock-up time can always be obtained.

[0002]

2. Description of the Related Art Since a mobile communication service area is composed of a plurality of subdivided wireless zones, in order for a mobile communication terminal to continue a call while moving between adjacent wireless zones, It is necessary to switch channels at high speed, that is, to switch frequencies. From this, analog PLL circuits used in mobile communication terminals, etc.
When the frequency is set, it is required to be pulled in to the set frequency at high speed to perform phase lock, that is, the lockup time is short and the lockup time is performed within a fixed time.
In order to meet this demand, in the conventional mobile communication terminal, the control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator (VCO) is stored in advance in the storage device of the control device that controls the high-speed analog PLL circuit. , The initial value of the VCO control voltage corresponding to the specified oscillation frequency is estimated from the stored contents, and the VCO corresponding to the specified oscillation frequency is estimated.
An initial value voltage in the vicinity of the control voltage is given to the VCO in advance, and then frequency data designated to the PLL synthesizer is given so that the pull-in phase lock can be performed at a designated frequency at high speed. That is, before the frequency data to be set to the PLL synthesizer for channel setting is transferred, the frequency that is expected to be phase-locked as the control voltage Vc to be given to the voltage controlled oscillator (VCO) forming the PLL circuit. The voltage close to the control voltage corresponding to is preset and supplied as an initial value, the oscillation frequency of the VCO is changed in advance to a frequency close to the required frequency, and then,
A high-speed analog PLL circuit system is adopted in which frequency data is transferred to a PLL synthesizer and a lock-up operation is performed from the preset frequency to perform phase lock at a high speed with a short and constant lock-up time.

[0003]

However, in the above-described high-speed analog PLL circuit, the control voltage-oscillation frequency characteristic of the voltage controlled oscillator (VCO) has a slope of the characteristic curve or the like accompanying a change in the ambient temperature, that is, the environmental temperature. Therefore, even if a predetermined voltage is supplied to the VCO in advance when the environmental temperature changes, the oscillation frequency cannot follow the environmental temperature, and the initially set frequency changes.
There is a problem in that the lock-up time varies and it becomes impossible to provide a constant lock-up time, making it impossible to perform high-speed lock-up in a constant time. To achieve phase lock at a set frequency with a constant and short lock-up time is always solved by monitoring and measuring the environmental temperature and correcting the control voltage-oscillation frequency characteristic curve of the VCO with the measured temperature. However, on the other hand, it is inevitable that an error occurs due to the difference in individual temperature characteristics and the software processing is complicated. A first object of the present invention is to provide a high-speed analog PLL circuit that can easily realize phase lock with a constant short lock-up time without being affected by changes in the ambient temperature (ambient temperature). A second object of the present invention is to configure a PLL without requiring software for monitoring the environmental temperature (ambient temperature) and correcting the control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator (VCO). The purpose of the present invention is to obtain a temperature compensation method for a high-speed analog PLL circuit that can easily achieve phase lock with a fixed short lock-up time without considering the inherent temperature characteristics of each element.

[0004]

[Means for Solving the Problems] The first object is to use PL
L synthesizer circuit, voltage controlled oscillator, storage means storing control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator, control voltage initial set value read from the storage means, and control voltage based on phase comparison result from the synthesizer circuit In a high-speed PLL circuit including a voltage adder for adding and, a control voltage-oscillation frequency characteristic curve of the voltage-controlled oscillator stored in the storage device is obtained by using a control voltage after phase locking of the PLL circuit. This is achieved by providing means for updating the control voltage-oscillation frequency characteristic curve corresponding to the environmental temperature. In addition, the control voltage −
The oscillation frequency characteristic curve is achieved by interpolating and storing data between two points. The second object comprises a PLL synthesizer, a voltage controlled oscillator, and a storage device that stores a control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator, and the control voltage applied to the voltage controlled oscillator is stored in the storage device. In a temperature compensation method of an initial set value in a high-speed analog PLL circuit that enables high-speed pull-in and high-speed phase lock in which a control voltage corresponding to a desired oscillation frequency is estimated from a control voltage-oscillation frequency characteristic curve and set to an initial value The control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator stored in the storage device is controlled by using the control voltage of the voltage controlled oscillator after the analog PLL circuit is phase locked. This is achieved by updating the frequency characteristic curve.

[0005]

The VCO control voltage of the voltage controlled oscillator when the PLL synthesizer is phase locked is regularly monitored,
The control voltage-oscillation frequency characteristic curve of the VCO that always follows the environmental temperature can be easily and easily updated by updating the previous initial value of the control voltage-oscillation frequency characteristic curve already stored in the storage device using the measurement result. It is definitely obtained. Therefore, by utilizing the updated initial value the next time the frequency is switched to the designated frequency, phase lock can be easily realized with a constant short lock-up time even if the environmental temperature fluctuates.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. The structure of the high-speed analog PLL according to the present invention will be described with reference to FIG. High speed analog PLL according to the invention
Is a PL including a phase comparator and a low-pass filter, etc.
L synthesizer circuit 1 and voltage controlled oscillator (VCO) 2
A voltage adder 3, a control arithmetic unit 4 including a microcomputer and a storage device, an initial value digital-analog converter 5, and a VOC control voltage monitoring analog-digital converter 6.

The microcomputer of the control arithmetic unit 4 outputs the frequency setting data F1 to the PLL synthesizer circuit 1, the initial value setting data F2 to the initial value digital-analog converter 5, and the VCO control voltage. The control voltage measurement data Vcd is input from the monitoring analog-digital converter 6 to the storage device of the control arithmetic unit 4. The output Ve of the PLL synthesizer circuit 1 and the output V'c from the initial value digital-analog converter 5 are input to the voltage adder 3, and the output Vc is the voltage-controlled oscillator 2 and the VCO control voltage monitoring analog-digital. It is input to the converter 6. The output fo of VCO2 is PLL
It is fed back 11 to the synthesizer circuit 1.

In the initial state, the initial value setting data F2 corresponding to the control voltage required to obtain a predetermined frequency is read from the control voltage-frequency characteristic curve data stored in the storage device of the control arithmetic unit 4, It is output to the initial value digital-analog converter 5, and converted into the voltage V'c here. That is, the DC voltage V'c in the vicinity of the control voltage Vc of the requested oscillation frequency fo is applied to the voltage controlled oscillator VCO2. The VCO 2 starts oscillating at the oscillation frequency f'o corresponding to the control voltage V'c. This oscillation frequency f'o is an oscillation frequency extremely close to the target oscillation frequency fo.

After that, the frequency setting data F1 is transferred from the control arithmetic unit 4 to the PLL synthesizer circuit 1, and the PLL is transmitted.
Becomes phase locked and the voltage controlled oscillator 2 sets the frequency f
Output the voltage of o. After the PLL loop is phase locked, the VCO control voltage Vc is controlled by the VCO control voltage monitoring analog-digital converter 6 to measure the control voltage Vc.
The data is transferred to the storage device of the control arithmetic unit 4 as d and the previous initial value setting data stored in the storage device is updated. As a result, the control voltage-oscillation frequency characteristic curve stored in the storage device is updated to a value that follows the current ambient temperature.

The temperature characteristic of the VCO control voltage (Vc) -VCO oscillation frequency (fo) characteristic curve will be described with reference to FIG. As conceptually shown in the figure, the Vc-fo curve A when the environmental temperature is A ° C. is shown by a line connecting a1, a3, and a2. Vc- when the ambient temperature is B ° C
The fo curve B is shown by a line connecting b1, b3, and b2.

Now, in an attempt to oscillate the high speed analog PLL circuit of FIG. 1 at the frequency f3, the VCO control voltage V'c
When the initial value setting data F2 is set to Va3 (V) and the environmental temperature is A ° C., the PLL circuit is rapidly phase-locked to the set frequency f3.
When the environmental temperature is B ° C., the VCO control voltage Va3
Since (V) is the voltage b'3 that oscillates the frequency f4, an extra lock-up time for shifting the frequency from f4 to f3 is required for the phase lock of the PLL circuit as compared with the case of A ° C. Become.

Here, after the phase lock, the actual control voltage Vc of the voltage controlled oscillator 2 is Vb3 (V). When this control voltage is taken into the control arithmetic unit 4, the oscillation frequency fo and the control voltage Vc are changed. A characteristic curve of B ° C. can be selected from the control voltage-oscillation frequency characteristic curve stored in the storage device. After that, when switching channels,
If the initial value setting data is output based on this curve B,
The control voltage V'c can be a value corrected at the ambient temperature B ° C., and the lockup time can be shortened to a constant value.

This embodiment shows an example in which a plurality of control voltage-frequency characteristic curves are stored in correspondence with the ambient temperature and the curves are selected and read out in response to the ambient temperature. Remember at least one curve for setting,
Based on this data, the actual control voltage at a plurality of oscillation frequencies may be detected to rewrite the initial value data corresponding to the environmental temperature.

More specifically, the alternative measure will be described in more detail. In the initial state, the storage device stores the initial value data represented by the VCO control voltage-oscillation frequency characteristic curve A of FIG. That is, the VCO oscillation frequency is f1 (H
z) and f2 (Hz) control voltage Va1 (V),
It is stored as Va2 (V). If the frequency f3
When there is a request to oscillate (Hz), a VCO control voltage Va3 (V) is obtained as an initial value by calculating from a VCO control voltage-oscillation frequency characteristic curve A stored in advance.
This value is transferred to the initial value setting digital-analog converter 5 as the initial value setting data F2, and then the frequency setting data F1 is transferred to the PLL synthesizer circuit 1 and P
LL is frequency-f3 phase locked. However,
When the environmental temperature fluctuates and the VCO control voltage-oscillation frequency characteristic curve fluctuates to B, the oscillation frequency f3 (H
z), the previously stored characteristic curve A
Is used, the initial value setting data is transferred as the control voltage Va3 (V) even though the control voltage Vb3 (V) is actually required. Therefore, the actual oscillation frequency of the VCO is
The frequency becomes f4 (Hz). This prevents a constant lockup time.

Here, the VCO control voltages at the oscillation frequencies f1 and f2 are periodically monitored to obtain the VCO control voltages Vb1 and Vb2 at the actual environmental temperature, and the initial value stored in the storage device is updated as a result. By,
The VCO control voltage-oscillation frequency characteristic curve B of the actual environment temperature B ° C. can be created. Next time, when the oscillation frequency f3 is specified, the initial value setting data F2 is updated by the updated VCO.
Control voltage Vb3 according to control voltage-oscillation frequency characteristic curve B
Since it is set by, the phase can be locked to the frequency f3 with a fixed lock-up time.

FIG. 2 is a high-speed analog PLL shown in FIG.
FIG. 3 is a diagram showing a specific configuration of a phase-locked oscillator circuit using the. The phase-locked oscillator circuit of the present invention comprises a PLL synthesizer circuit 1, a voltage controlled oscillator (VCO) 2, a voltage adder 3, a control arithmetic unit 4, an initial value digital-analog converter 5, and a VCO control voltage. It is composed of a monitoring analog-digital converter 6 and a PLL reference oscillator 21. The PLL synthesizer circuit 1 includes a phase comparator 11 and
It is composed of an integrator 12, a 1 / M frequency divider 13, and a programmable counter 14.

The oscillation frequency setting data F1 is input to the programmable counter 14 which divides the frequency to 1 / N, and determines the frequency division number for dividing the output of the voltage controlled oscillator (VCO) 2. The stable output fs of the PLL reference oscillator 21 is input to the 1 / M frequency divider 13 that divides the input into an arbitrary integer M, and becomes the reference frequency fa of fs / M, which is the phase comparator 11
Entered in. On the other hand, to the other input of the phase comparator 11,
The output fb of the programmable counter 14 that divides the output fo of the voltage controlled oscillator (VCO) 2 into 1 / N is input. The comparison result fe, which is phase-compared by the phase comparator 11, is
It is smoothed by the integrator 12 and output as the output Ve. Initial value data F read from the storage device of the control arithmetic unit 4
2 is input to the initial value digital-analog converter 6, where it is converted to a DC voltage V'c and output to the adder 3. In the adder 3, the output Ve from the integrator 12 and the output V'c from the initial value digital-analog converter 5 are output.
And are added and applied to the voltage controlled oscillator (VCO) 2 as the VCO control voltage Vc. Output Vc of this adder 3
Thus, the PLL is in a phase locked state.

When the PLL is phase-locked, the relationship of fa = fb is established between the two input signal frequencies fa and fb of the phase comparator 11. Since the 1 / N program counter 14 is inserted in the feedback loop, fb = fo1 / N, and fo = Nfb = Nfa, where fa = fs1 / M By substituting the relationship, fo = N · fa = fs · N / M is obtained, and a stable output signal fo obtained by multiplying the stable output fs of the PLL reference oscillator 21 by N / M is obtained.

After the PLL circuit is phase locked, the VCO control voltage Vc applied to the voltage controlled oscillator 2 is changed to V
The CO control voltage monitoring analog-to-digital converter 6 converts the digital value to obtain a control voltage measurement data Vcd, and the data Vcd is used to store the control voltage-frequency characteristic stored in the storage device in the control arithmetic unit 4. Rewrite the curve with the actual environmental temperature as a parameter.

[0020]

As described above, when the PLL synthesizer is phase locked at the oscillation frequencies of f1 and f2, the control voltage applied to the voltage controlled oscillator is periodically acquired and stored in the VCO control. By updating the voltage-oscillation frequency characteristic curve, the control voltage corresponding to the actual environmental temperature can be preset, and the frequency close to the desired oscillation frequency can be immediately oscillated, and the lock-up time can be kept constant. At the same time, the phase can be locked to a predetermined oscillation frequency with a short lock-up time. Therefore, the lock-up time can be temperature-compensated without taking the method of temperature compensation using the temperature monitoring result and without considering the complicated processing by software and the unique temperature characteristic of each circuit component. . That is, since the PLL circuit regularly monitors the control voltage in the phase locked state at the desired oscillation frequency,
VC at the ambient temperature where the PLL circuit is actually operating
The O control voltage can be acquired, and the initial value data already stored in the storage device is updated with the latest acquired data to more accurately set the next initial value following the environmental temperature. Can be easily realized. Therefore, it is possible to follow the environmental temperature and fast phase lock at a desired oscillation frequency with a constant lock-up time.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of essential parts of a high-speed analog PLL according to the present invention.

FIG. 2 is a diagram showing a specific configuration of a high-speed analog PLL synthesizer of the present invention.

FIG. 3 is a diagram showing an example of a VCO control voltage-oscillation frequency characteristic of the present invention.

[Explanation of symbols]

 1 PLL Synthesizer Circuit 2 Voltage Controlled Oscillator (VCO) 3 Voltage Adder 4 Control Arithmetic Device 5 Initial Value Digital-Analog Converter 6 VCO Control Voltage Monitoring Analog-Digital Converter 11 Phase Comparator 12 Integrator 13 1 / M Frequency divider 14 Programmable counter 21 PLL reference oscillator

Continuation of the front page (72) Inventor Yoshitomo Kuwamoto 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture

Claims (4)

[Claims] 1. A PLL synthesizer circuit, a voltage controlled oscillator, a storage means for storing a control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator, a control voltage initial set value read from the storage means, and a phase comparison from the synthesizer circuit. In a high-speed PLL circuit including a voltage adder that adds a control voltage based on the result, a control voltage of the voltage controlled oscillator stored in the storage device using the control voltage after phase locking of the PLL circuit-oscillation frequency A high-speed analog PLL circuit comprising means for updating a characteristic curve to a control voltage-oscillation frequency characteristic curve corresponding to an actual environmental temperature. 2. The high-speed analog PLL circuit according to claim 1, wherein at least two control voltage-oscillation frequency characteristic curves are stored in a storage device. 3. A means for updating the control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator to a control voltage-oscillation frequency characteristic curve corresponding to an actual environmental temperature based on at least one oscillation frequency control voltage. A high-speed analog PLL circuit according to item 1. 4. A control voltage stored in said storage device, comprising a PLL synthesizer, a voltage controlled oscillator, and a storage device storing a control voltage-oscillation frequency characteristic curve of said voltage controlled oscillator. -A temperature compensation method for an initial set value in a high-speed analog PLL circuit that enables high-speed pull-in and high-speed phase lock in which a control voltage corresponding to a desired oscillation frequency is estimated from an oscillation frequency characteristic curve and set to an initial value. The control voltage-oscillation frequency characteristic curve of the voltage controlled oscillator stored in the storage device using the control voltage of the voltage controlled oscillator after the PLL circuit is phase-locked is the control voltage-oscillation frequency characteristic corresponding to the actual environmental temperature. A method for compensating the temperature of the initial set value in a high-speed analog PLL circuit characterized by updating to a curve .