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JPH07105463B2 - Package for ultra high frequency devices - Google Patents

Package for ultra high frequency devices

Info

Publication number
JPH07105463B2
JPH07105463B2 JP61049703A JP4970386A JPH07105463B2 JP H07105463 B2 JPH07105463 B2 JP H07105463B2 JP 61049703 A JP61049703 A JP 61049703A JP 4970386 A JP4970386 A JP 4970386A JP H07105463 B2 JPH07105463 B2 JP H07105463B2
Authority
JP
Japan
Prior art keywords
package
high frequency
laminated ceramic
ultra
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61049703A
Other languages
Japanese (ja)
Other versions
JPS62206860A (en
Inventor
徹 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61049703A priority Critical patent/JPH07105463B2/en
Publication of JPS62206860A publication Critical patent/JPS62206860A/en
Publication of JPH07105463B2 publication Critical patent/JPH07105463B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 キャビティ内に半導体素子が搭載され、半導体素子の電
極が外部リードに電気的に接続されている超高周波素子
用パッケージに関する。Description: TECHNICAL FIELD The present invention relates to a package for an ultra-high frequency element in which a semiconductor element is mounted in a cavity and electrodes of the semiconductor element are electrically connected to external leads.

〔従来の技術〕[Conventional technology]

従来、この種の超高周波素子用パッケージは、第３図に
示すようにキャビティ内に半導体11を内蔵し各電極をボ
ンディング線12で積層セラミック13上のメタライズ配線
パターン14の一端に接続し、他端のメタライズ配線パタ
ーン14の外部リード取付部分15に外部リード16を取付け
キャップシール用金属部材17で被われるようになってい
た。Conventionally, this type of package for an ultra-high frequency device has a semiconductor 11 built in a cavity and each electrode is connected to one end of a metallized wiring pattern 14 on a laminated ceramic 13 by a bonding line 12 as shown in FIG. The external lead 16 is attached to the external lead attaching portion 15 of the end metallized wiring pattern 14 and is covered with the cap sealing metal member 17.

キャビティ内に搭載される半導体素子11として、シリコ
ンより電子の移動度の大きなGaAs結晶を使用したGaAsFE
TやGaAsICといった高速デバイスが実用化されてきてい
るため、第３図に示されるようにパッケージ材料の積層
セラミック13として一般的にアルミナ（εｒ〜10）を使
用し、積層セラミック13の下層部の厚さと配線パターン
14の幅とがほぼ１対１になるように設定されている。し
たがって、この場合特性インビーダンスは約50Ωとな
り、超高周波信号に対する反射損が比較的少ない良好な
特性を持っていることを利用したマイクロストリップラ
イン型のパッケージとなっており、一般的なセラミック
ケースとは異なってGaAs素子のパッケージに要求される
超高周信号の反射損、通過損の最小化、所望高周波領域
における共振の除去、入出力端子間のクロストークの最
小化をも図っている。しかしながら、GaAsICのような多
数の電極をもつ半導体素子が現われてきたため、この従
来のパッケージは、パッケージ外形が必然的に大きくな
り、共振周波数が低周波側にシフトしてしまうようにな
っていた。As a semiconductor element 11 mounted in the cavity, a GaAsFE using a GaAs crystal having a higher electron mobility than silicon.
Since high-speed devices such as T and GaAs ICs have been put to practical use, alumina (εr to 10) is generally used as the laminated ceramic 13 of the package material as shown in FIG. Thickness and wiring pattern
The width of 14 is set to be almost one-to-one. Therefore, in this case, the characteristic impedance is about 50Ω, which is a microstrip line type package that takes advantage of the fact that the reflection loss for ultra-high frequency signals is relatively small. In addition to the above, it also aims to minimize reflection loss and passage loss of ultrahigh frequency signals required for GaAs device packages, eliminate resonance in a desired high frequency region, and minimize crosstalk between input and output terminals. However, since a semiconductor device having a large number of electrodes such as a GaAs IC has appeared, the package size of this conventional package is inevitably large, and the resonance frequency is shifted to the low frequency side.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の超高周波素子用パッケージは、パッケー
ジの外周長をｌ、信号の波長を入、信号の周波数をｆ、
高速をＣとすると、パッケージの外周長ｌが信号の波長
入の1/4程度と等しい周波数で求められるようなパッケ
ージの外寸から比較的低い周波数に規定される共振周波
数をもつため、外部リード数が少ないときはパッケージ
サイズを小さくし高周波化に対応できたが外部リード数
が多くなってくると、パッケージサイズを必然的に大き
くせざるを得ず、共振周波数を低下させ高周波域での使
用を困難にさせる欠点があり、また、この欠点に対処す
るためのリード間ピッチの縮少化が考えられたが、製造
上あるいはデバイスの組付、実装時の取扱いの困難性か
ら縮少化にも限度があるという欠点がある。In the conventional package for ultra-high frequency elements described above, the outer peripheral length of the package is 1, the wavelength of the signal is input, the frequency of the signal is f,
Assuming that the high speed is C, the outer peripheral length l of the package has a resonance frequency defined as a relatively low frequency from the outer dimension of the package, which is obtained at a frequency equal to about 1/4 of the wavelength of the signal. When the number was small, the package size could be reduced to support higher frequencies, but when the number of external leads increased, the package size was inevitably increased, and the resonance frequency was lowered to use in high frequencies. However, it was considered to reduce the lead-to-lead pitch in order to deal with this drawback, but it was reduced due to the difficulty of handling during manufacturing, device assembly, and mounting. There is a drawback that there is a limit.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の超高周波用パッケージは、半導体素子の電極と
外部リードとを電気的に接続する手段として、直方体の
積層セラミック、材料の上面と底面との間に底面に平行
な帯状のメタライズパターンであって、その長手方向か
ら見たとき両端が対向する１組の側面のほゞ左右等分の
位置に位置するメタライズパターンを内蔵し、メタライ
ズパターンが垂直に交わる該１組の側面以外の面に金属
膜を形成し、メタライズパターンの両端を配線のために
露出するべく積層セラミック材料の一部分を切り欠いた
中心導体同軸型の積層セラミック素子を並列に配列し接
合したものを有する。The package for ultra-high frequency of the present invention has a rectangular parallelepiped laminated ceramic as a means for electrically connecting the electrodes of the semiconductor element and the external leads, and a strip-shaped metallization pattern parallel to the bottom surface between the top and bottom surfaces of the material. , A metallization pattern located at approximately equal positions on the left and right sides of the pair of side surfaces facing each other when viewed from the longitudinal direction is built in, and the metallization pattern is formed on a surface other than the pair of side surfaces where the metallization pattern intersects vertically. A film is formed, and a central conductor coaxial type laminated ceramic element in which a part of the laminated ceramic material is cut out to expose both ends of the metallized pattern for wiring is arranged and joined in parallel.

従って、外部リードから見た超高周波用パッケージの特
性は、ほとんど積層セラミック素子のもつ特性で決ま
り、超高周波用パッケージ全体の影響はほとんど受けな
いこととなる。Therefore, the characteristics of the super high frequency package viewed from the external leads are almost determined by the characteristics of the monolithic ceramic element, and are hardly affected by the entire super high frequency package.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の超高周波素子用パッケージの一実施例
を示す平面図、第２図（ａ）は第１図に用いられる積層
セラミック素子３の斜視図、第２図（ｂ）は積層セラミ
ック素子３を製造する一工程例を示す斜視図である。FIG. 1 is a plan view showing an embodiment of a package for an ultra-high frequency device of the present invention, FIG. 2 (a) is a perspective view of a laminated ceramic device 3 used in FIG. 1, and FIG. 2 (b) is a laminated structure. It is a perspective view showing an example of one process of manufacturing ceramic element 3.

本実施例では超高周波素子用パッケージは第１図に示す
ように第２図（ａ）の積層セラミック素子３を並列に３
個Ag−Cuろうで接合したものがパッケージの一面とその
面に対向するもう一面に組付けられており、積層セラミ
ック素子３の下面は外壁金属部材８に、上面はキャップ
シール用金属部材７にAg−Cuろうで接合され、また積層
セラミック３のメタライズ配線パターン４の一端はパッ
ケージのキャビティ内にマウントされた半導体素子１の
電極にボンディング線２で接続され、他端には外部リー
ド６がAgCuろうで接合されている構造となっている。In this embodiment, as shown in FIG. 1, the package for an ultra-high frequency element is made up of three laminated ceramic elements 3 shown in FIG.
The individual Ag-Cu brazing materials are assembled on one surface of the package and the other surface opposite to the surface. The lower surface of the laminated ceramic element 3 is the outer wall metal member 8 and the upper surface is the cap sealing metal member 7. The metallized wiring pattern 4 of the laminated ceramic 3 is joined with an Ag-Cu solder, and one end of the metallized wiring pattern 4 is connected to the electrode of the semiconductor element 1 mounted in the cavity of the package by the bonding wire 2. The structure is such that it is joined by brazing.

本実施例の超高周波素子用パッケージに使用されている
積層セラミック素子３は第２図（ａ）に示されるよう
に、その下層部分、上層部分は形は違うがともに直方体
の形状をしており、下層部分のほゞ中心位置にメタライ
ズ配線パターン４がセラミックの積層技術を用いて形成
されている。この積層セラミック素子３の材料は第２図
（ｂ）に示されるように、後にメタライズ配線パターン
４となるメタライズ層以外に上面および不図示の下面に
メタライズ層10をもち、シート状に焼成されたセラミッ
クをダイシングソー等で、Ｘ、Ｙの二方向に切断して作
られる。このように切断された積層セラミック素子３の
材料のＸ方向の２つの切断面は凸状の形をしているが、
この２つの切断面にさらにメタライズ層11を形成したも
のが積層セラミック素子となるのであって、量産性がよ
く安価に製造することができる。As shown in FIG. 2 (a), the laminated ceramic element 3 used in the package for the ultra-high frequency element of this embodiment has a rectangular parallelepiped shape although the lower layer portion and the upper layer portion have different shapes. The metallized wiring pattern 4 is formed at a substantially central position of the lower layer portion by using a ceramic laminating technique. As shown in FIG. 2 (b), the material of the laminated ceramic element 3 has a metallized layer 10 on the upper surface and a lower surface (not shown) other than the metallized layer to be the metallized wiring pattern 4 later, and is fired in a sheet shape. It is made by cutting ceramic in two directions X and Y with a dicing saw or the like. Two cut surfaces in the X direction of the material of the laminated ceramic element 3 cut in this way have a convex shape,
A metallized layer 11 is further formed on the two cut surfaces to form a monolithic ceramic element, which is suitable for mass production and can be manufactured at low cost.

上述したように、本実施例の超高周波素子用パッケージ
に組付けられた積層セラミック素子３は同軸ラインとし
て働き、共振周波数は第２図（ａ）で示される積層セラ
ミック素子３の幅Ｗで規定され、超高周波用パッケージ
全体のサイズとは無関係となる。積層セラミック素子３
の幅Ｗを任意に小さくすることにより半導体素子の一層
の高周化および多ピン化に対応できる。As described above, the monolithic ceramic element 3 assembled in the super high frequency element package of this embodiment functions as a coaxial line, and the resonance frequency is defined by the width W of the monolithic ceramic element 3 shown in FIG. 2 (a). Therefore, it has nothing to do with the size of the entire package for ultra high frequencies. Multilayer ceramic element 3
By making the width W of the semiconductor device arbitrarily small, it is possible to cope with a further increase in the frequency and the number of pins of the semiconductor element.

一例として、積層セラミック素子３の幅Ｗを1.3mmと
し、並列に３個並べたパッケージにおける実験結果で
は、20GHZまで共振はなかった。また、特性インビーダ
ンスを50Ωにすることは、マイクロストリップライン型
パッケージと同様程度に可能で、高周波のリターンロス
も17GHZで約18dBと良好であった。As an example, the width W of the monolithic ceramic element 3 is 1.3 mm, and the experimental result in a package in which three pieces are arranged in parallel has no resonance up to 20 GHz. Also, the characteristic impedance can be set to 50Ω as much as that of the microstrip line type package, and the high frequency return loss was about 18 dB at 17 GHz.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、直方体の形状をした中心
導体同軸型の積層セラミック素子と外部リードとキャビ
ティ内の半導体素子の電極との接続に使用することによ
り、外部リードから見た特性は超高周波素子用パッケー
ジ全体の影響は受けず積層セラミック素子特性のみによ
って決定できる効果があり、多数の電極を持つ半導体素
子に対しても積層セラモック素子を並列に直接接合して
使用することにより容易に対応できる効果がある。INDUSTRIAL APPLICABILITY As described above, the present invention is used for connecting a rectangular parallelepiped-shaped central conductor coaxial type laminated ceramic element and an external lead to an electrode of a semiconductor element in a cavity. It has the effect that it can be determined only by the laminated ceramic element characteristics without being affected by the entire high frequency element package, and it can be easily applied to semiconductor elements with multiple electrodes by directly connecting the laminated ceramic elements in parallel. There is an effect that can be done.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の超高周波素子用のパッケージの一実施
例を示す平面図、第２図（ａ）は第１図に用いられる積
層セラミック素子３の斜視図、第２図（ｂ）は積層セラ
ミック素子３を製造する一工程例を示す斜視図であり、
第３図は従来の超高周波素子用のパツケージを示す平面
図である。 １……半導体素子、 ２……ボンディング線、 ３……積層セラミック素子、 ４……メタライズ配線パターン、 ５……メタライズパターン４のリード取付部分 ６……外部リード、 ７……キャップシール用金属部材、 ８……外壁金属部材、 10,11……メタライズ層。FIG. 1 is a plan view showing an embodiment of a package for an ultra-high frequency element of the present invention, FIG. 2 (a) is a perspective view of a laminated ceramic element 3 used in FIG. 1, and FIG. 2 (b) is FIG. 6 is a perspective view showing an example of a process of manufacturing the laminated ceramic element 3.
FIG. 3 is a plan view showing a conventional package for an ultra-high frequency element. 1 ... Semiconductor element, 2 ... Bonding wire, 3 ... Multilayer ceramic element, 4 ... Metallized wiring pattern, 5 ... Lead mounting portion of metallized pattern 6 ... External lead, 7 ... Metal member for cap seal , 8 …… Metal member for outer wall, 10,11 …… Metalized layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】キャビティ内に半導体素子が搭載され、半
導体素子の電極が外部リードに電気的に接続されている
超高周波素子用パッケージにおいて、半導体素子の電極
と外部リードとを電気的に接続する手段として、直方体
の積層セラミック材料の上面と底面との間に底面に平行
な帯状のメタライズパターンであって、その長手方向か
ら見たとき両端が対向する１組の側面のほぼ左右等分の
位置に位置するメタライズパターンを内蔵し、メタライ
ズパターンが垂直に交わる該１組の側面以外の面に金属
膜を形成し、メタライズパターンの両端を配線のために
露出するべく積層セラミック材料の一部を切り欠いた中
心導体同軸型の積層セラミック素子を並列に直接接合し
たものを含むことを特徴とする超高周波素子用パッケー
ジ。1. A package for an ultra-high frequency element in which a semiconductor element is mounted in a cavity and electrodes of the semiconductor element are electrically connected to external leads, wherein the electrodes of the semiconductor element are electrically connected to the external leads. As a means, there is a strip-shaped metallization pattern parallel to the bottom surface between the top surface and the bottom surface of the rectangular parallelepiped laminated ceramic material, and when viewed in the longitudinal direction, a pair of side surfaces, which are opposed to each other, have substantially equal positions. A metal film is formed on a surface other than the pair of side surfaces where the metallization pattern vertically intersects, and a part of the laminated ceramic material is cut to expose both ends of the metallization pattern for wiring. A package for an ultra-high frequency element, which includes what is formed by directly joining parallel lacking central conductor coaxial type laminated ceramic elements.
JP61049703A 1986-03-06 1986-03-06 Package for ultra high frequency devices Expired - Lifetime JPH07105463B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61049703A JPH07105463B2 (en) 1986-03-06 1986-03-06 Package for ultra high frequency devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61049703A JPH07105463B2 (en) 1986-03-06 1986-03-06 Package for ultra high frequency devices

Publications (2)

Publication Number Publication Date
JPS62206860A JPS62206860A (en) 1987-09-11
JPH07105463B2 true JPH07105463B2 (en) 1995-11-13

Family

ID=12838545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61049703A Expired - Lifetime JPH07105463B2 (en) 1986-03-06 1986-03-06 Package for ultra high frequency devices

Country Status (1)

Country Link
JP (1) JPH07105463B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4502543B2 (en) * 2001-04-24 2010-07-14 京セラ株式会社 Ceramic terminal and semiconductor device storage package
US9041208B2 (en) 2011-11-02 2015-05-26 Avago Technologies General Ip (Singapore) Pte. Ltd. Laminate interconnect having a coaxial via structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58190046A (en) * 1982-04-30 1983-11-05 Fujitsu Ltd Semiconductor device
JPS6189651A (en) * 1984-10-08 1986-05-07 Fujitsu Ltd semiconductor equipment

Also Published As

Publication number Publication date
JPS62206860A (en) 1987-09-11

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