JPH07105150B2 - Nonvolatile semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having an electrically writable non-volatile semiconductor memory element and a write circuit thereof. Regarding the device.

[Conventional technology]

Conventionally, as a nonvolatile semiconductor memory element capable of electrically writing information, there is a MOS field effect transistor (hereinafter referred to as a memory transistor) having a two-layer gate structure of a floating gate and a control gate. FIG. 7 (a) is a sectional view of this memory transistor, FIG. 7 (b) is its symbolic view, and FIG. 7 (c) is its characteristic view. This memory transistor is provided with a source 72 and a drain 73 formed of an N type diffusion layer on a P type substrate 71, and further has a P type substrate.
A floating gate 74, which is electrically insulated from the outside by an insulating layer, and a control gate 75 for switching this memory transistor are provided on 71. This memory transistor is said to be in a non-writing state when the floating gate 74 is in an electrically neutral state, and becomes conductive at a low control gate voltage V _G , for example 2 V, as shown by the solid line 76 in FIG. 7 (c). But,
When a high voltage, for example, 12.5V is applied to the control gate 75 and the drain 73, electrons are injected into the floating gate 74, the threshold voltage of the memory transistor seen from the control gate 75 becomes high, and it is called a write state. As shown by the solid line 77, unless a high control gate voltage V _G , for example, 7 V is applied, the conductive state is not established. Information can be stored by utilizing this change in threshold voltage.

FIG. 5 is a circuit diagram showing a conventional write circuit for the memory transistor of FIG. The memory transistor MC _{51 has} a source connected to the ground potential V _SS and a drain connected to the write voltage V _PP via an N-type field effect transistor (hereinafter referred to as MOSFET) M ₅₃ . N-type depletion MOSFET M ₅₁ and N-type MOS
Inverter circuit INV ₅₁ is configured with FETM _52, and write data D ₅₁ is connected to the input terminal and output Is connected to the gate of N-type MOSFET M ₅₃ . When writing information, set write data D ₅₁ to low level to output inverter circuit INV ₅₁ . That write voltage V _PP is applied to the gate of the N-type MOSFET M _53, N-type MOSFET M ₅₃ is turned on. At this time, since the high voltage is also applied to the gate X ₅₁ of the memory transistor MC _51, the high voltage is applied to the gate and the drain of the memory transistor MC ₅₁ , and electrons are injected into the floating gate, so that information Writing is performed.

Next, the writing characteristics of this memory transistor will be described.

FIG. 6 (a) shows the memory transistor MC ₅₁ shown in FIG.
FIG. 5 is a voltage-current characteristic diagram at the time of writing, in which the horizontal axis represents the voltage Va ₅ of the drain a ₅ of the memory transistor MC _{51 in} FIG.
The vertical axis is the current I ₅ flowing in the memory transistor MC ₅₁ . If the load characteristic of the N-type MOSFET M ₅₃ is set as shown by the solid line 60a, V _PP is applied to the gate of the N-type MOSFET M ₅₃ , so that no current flows in the memory transistor MC ₅₁ (I ₅ = 0), the voltage Va ₅ (I ₅ = 0) of the drain a ₅ of the memory transistor MC ₅₁ is V _TN53 which is a threshold voltage considering the back bias characteristic of the N-type MOSFET M ₅₃ , and is given by the following equation (1). Shown.

Va ₅ (I ₅ = 0) = V _PP −V _TN53 (1) _Assuming that the voltage-current characteristic of the memory transistor MC _{51 in} the non-written state is the solid line 61a, the initial _stage when writing to the memory transistor MC ₅₁ is performed. Memory transistor MC in state
The voltage Va _{5 at} the drain of ₅₁ is the voltage V _W61a indicated by the intersection of the solid line 60a and the solid line 61a.
A current I _W61a flows through C ₅₁ , and electrons are injected into the floating gate. When the memory transistor MC ₅₁ enters the write state, its voltage-current characteristic changes to the dotted line 63a, and the drain voltage of the memory transistor MC ₅₁ also changes to V _W63a . However, in an actual nonvolatile semiconductor memory device, memory transistors are arranged in a matrix, and a plurality of row lines that serve as common gate electrodes of memory transistors arranged in rows and drains of memory transistors arranged in columns are arranged. By selecting one row line and one column line from the plurality of column lines connected to each other, the memory transistor arranged at the intersection is selected and writing is performed. Therefore, the memory transistor shown in FIG. The drain a _{5 of the} MC ₅₁ is connected to the drains of a plurality of unselected memory transistors not shown in the figure, and the gates of these unselected memory transistors are at the same level as V _SS . If there is a write-in memory transistor among the unselected memory transistors connected to the drain a ₅ of the memory transistor MC ₅₁ , the floating gate of the write-in memory transistor is charged to a negative potential. And
When a high voltage is applied to the drain, a high electric field is generated in the depletion layer at the end of the drain and avalanche breakdown occurs. The drain voltage V _{BD at} this time is the voltage V shown in FIG. 6 (a).
_When lower than _PP- V _TN53 and lower than V _W63a ,
The holes generated by this avalanche breakdown are injected into the floating gate of the written memory transistor, neutralize the electrons already injected into the floating gate, and lower the threshold voltage of the written memory transistor. Therefore, generally, the load characteristic of the N-type MOSFET M ₅₃ is set as shown by the solid line 60b as shown in FIG. 6 (b), and the voltage-current characteristic of the memory transistor in the written state is set.
The intersection of 63b and load characteristic 60b is prevented from becoming a voltage higher than V _BD .

[Problems to be Solved by the Invention]

In order to prevent the occurrence of avalanche breakdown in the conventional write circuit described above, the load resistance of the N-type MOSFET M ₅₃ shown in FIG. 5 is set to a large value, so that the memory in the non-write state as shown in FIG. If the current-voltage characteristics of the transistor change as shown by the solid line 62b due to variations in the manufacturing stage, when writing information to this memory transistor, only a low voltage V _W62b is applied to the drain. Therefore, the writing speed deteriorates, and in the worst case, writing becomes impossible. Also,
Even if the load resistance of the N-type MOSFET M ₅₃ is set to a large value (V
_{Since PP} −V _TN53 )> V _BD , there is a drawback that the circuit becomes complicated because it requires timing adjustment such as applying a voltage to the drain after the gate of the selected memory transistor is always set to a high voltage.

An object of the present invention is to provide a constant voltage generating circuit for generating a constant voltage lower than the write voltage, and by setting the drain voltage of the memory transistor at the time of writing by the output voltage of this constant voltage generating circuit, non-selection at the time of writing operation is performed. It is an object of the present invention to provide a non-volatile semiconductor memory device that prevents avalanche breakdown of a memory transistor in the written state, does not deteriorate the writing speed, and does not require timing adjustment during writing.

[Means for Solving the Problems]

A nonvolatile semiconductor memory device of the present invention uses a nonvolatile semiconductor memory element capable of electrically writing information as a storage medium, and a first write voltage is applied to the first resistor via a load resistor formed by a MOS transistor. Second lower than the write voltage of
Is supplied to the drain of the storage medium as a write voltage for the load resistance MOS so that the second write voltage supply operation is selectively performed in response to predetermined write information.
In a non-volatile semiconductor memory device including write voltage control means for controlling conduction / non-conduction of a transistor, the write voltage control means generates a constant voltage lower than the first write voltage and higher than a power supply voltage. And a write control circuit for selectively supplying the constant voltage to the gate of the load resistance MOS transistor in response to the write information, the constant voltage generating circuit having a potential of the first write voltage. The constant voltage is the voltage at the series connection point of a plurality of MOS transistors of the same conductivity type that are inserted in series connection with the power supply potential, each substrate potential is connected to the same potential as the source, and the gate is connected to the drain. The write control circuit is configured to output the write information, and the write control circuit serves as an inverter that receives the write information as an input. Is a storage device in which the storage medium is arranged in an array and the array is divided into a plurality of blocks to enable simultaneous writing and reading of a plurality of bits of data. It is characterized by comprising the constant voltage generating circuit, the load resistance MOS transistors for the plurality of bits, and the write control circuit for the plurality of bits.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The source of the memory transistor MC ₁₁ is connected to the ground potential V _SS and the drain is connected to the write voltage V _PP via the N-type MOSFET M ₁₁ .
The constant voltage generator V _CON11 generates a constant voltage V _R11 lower than the write voltage V _PP , and the write control circuit WR ₁₁ outputs the write information D ₁₁
Thus, the constant voltage V _R11 is selectively applied to the gate of the N-type MOSFET M ₁₁ .

Next, the write characteristics of the write circuit of the present invention will be described. Second
Figure voltage during the writing of the memory transistors MC ₁₁ shown in FIG. 1 - a current characteristic diagram, the voltage Va ₁ of the drain a ₁ of the memory transistor MC ₁₁ of FIG. 1 on the horizontal axis, flows through the memory transistor MC ₁₁ The current I ₁ is plotted on the vertical axis. If the load characteristic of the N-type MOSFET M ₁₁ is set as shown by the solid line 20, a constant voltage V _R11 is applied to the gate of the N-type MOSFET M ₁₁ , so that no current flows in the memory transistor MC ₁₁ (I ₁ = 0), the drain of the memory transistor MC ₁₁
Voltage Va ₁ of a ₁ (I ₁ = 0) is shown when a threshold voltage in consideration of the back-bias characteristics of the N-type MOSFET M ₁₁ and V _TN11 by the following formula (2).

Va ₁ (I ₁ = 0) = V _R11 −V _TN11 (2) _Assuming that the voltage-current characteristics of the memory transistor MC _{11 in} the non-written state is a solid line 21, the initial state when writing to the memory transistor MC ₁₁ is performed. Memory transistor MC _{11 in}
The drain voltage Va ₁ is a voltage V _W21 indicated by the intersection of the solid line 20 and the solid line 21. At this time, the current I _W21 flows through the memory transistor MC ₁₁ and electrons are injected into the floating gate. When the memory transistor MC ₁₁ enters the write state, its voltage-current characteristic changes to the dotted line 23, and the drain voltage of the memory transistor MC ₁₁ also changes to V _W23 . Furthermore, in an actual nonvolatile semiconductor memory device, memory transistors are arranged in a matrix, and a plurality of row lines that serve as common gate electrodes of the memory transistors arranged in the row direction and drains of the memory transistors arranged in the column direction are arranged. By selecting one row line and one column line from the plurality of column lines connected to each other, the memory transistor arranged at the intersection is selected and writing is performed. Therefore, the memory shown in FIG. The drain a ₁ of the transistor MC ₁₁ is connected to the drains of a plurality of unselected memory transistors, which are not shown in the figure, and the levels of the gates of these unselected memory transistors are V _SS . Here, there is a write-in memory transistor among a plurality of unselected memory transistors connected to the drain a ₁ of the memory transistor MC ₁₁ , and a high voltage is applied to the drain of this write-in memory transistor. Let V _BD be the voltage at which avalanche breakdown occurs due to (V
_R11 −V _TN11 ) <V _BD constant voltage generator V
Avalanche breakdown does not occur if the output voltage V _{R11 of CON11} is set.

FIG. 3 is a circuit diagram showing the embodiment of FIG. 1 in detail.
A plurality of memory transistors MC ₃₁₁ and MC _{312 to} MC _3mn are arranged in a matrix, and a plurality of row lines X ₃₁ and X that serve as common gate electrodes of the memory transistors arranged in the row direction.
_{32 to} X _3m, and a plurality of column lines D ₃₁ and D _{32 to} D _3n connecting the drains of the memory transistors arranged in the column direction,
The row lines control switching of the memory transistors by the row selection signal from the row decoder XD ₃ , and the column lines the column decoder.
Column select N-type MOSFET MY ₃₁ that are switching-controlled by a column selection signal SY ₃₂ to SY _3n from YD _3, MY ₃₂ selected by ~MY _3n, the drain of the column select N-type MOSFETMY _31, MY ₃₂ ~MY _3n common Connected to the sense amplifier circuit SA ₃
It is also connected to the write voltage V _PP via the N-type MOSFET M ₃₅ . Furthermore, P-type MOSFETs M ₃₁ and M ₃₂ are connected in series, and P-type M
The source of the OSFETM ₃₁ is connected to the write voltage V _PP , and the drain and gate of the P-type MOSFET M ₃₂ are connected to the power supply voltage V _CC to form a constant voltage generation circuit V _CON31 . The P-type MOSFET M ₃₃ and the N-type MOSFET M
A write control circuit WR ₃₁ which is an inverter circuit is configured with _34, and a constant voltage generation circuit V _CON31 is used as the source of the P-type MOSFET M _33.
Of the output voltage V _R31 , the write information D ₃₁ is connected to the input of the write control circuit WR ₃₁ , and the gate of the N-type MOSFET M ₃₅ is connected to the output.

Here, for example, when writing to the memory transistor MC ₃₁₁ , the row decoder XD ₃ selects the row line X ₃₁ , and the column decoder YD ₃ selects the column selection N-type MOSFET MY ₃₁ to select the row line X ₃₁ and the column line. The memory transistor MC ₃₁₁ arranged at the intersection with D ₃₁ is selected. Next, by setting the write information D ₃₁ to the low level, the P-type M is applied to the gate of the N-type MOSFET M _35.
Output voltage of constant voltage generator V _CON31 via OSFETM ₃₃ V _R31
Is applied and the N-type MOSFET M ₃₅ becomes conductive,
Writing is performed by applying a high voltage to the gate and drain of the memory transistor MC ₃₁₁ . Here, _assuming that the threshold voltages of the P-type MOSFETs M ₃₁ and M ₃₂ are V _TP31 and V _TP32 , respectively, the output voltage V _R31 of the constant voltage generating circuit V _CON31 can be changed by changing the gate length and the gate width as is known. It can be set within the voltage range of Expression (3).

(V _PP − | V _TP31 |)> V _R31 > (V _CC + | V _TP32 |)…
(3) Therefore, write voltage V is applied to the gate of the column selection N-type MOSFET MY _31.
PP is applied, the voltage V _D31 (I _D31 = 0) of the column lines D ₃₁ when no current flows column lines D ₃₁ is selected and the column lines D ₃₁ is, N-type M
When the threshold voltage considering the back bias characteristic of OSFETM ₃₅ is V _TN35 , the voltage range of the following formula (4) is obtained.

(V _PP − | V _TP31 | −V _TN35 )> V _D31 (I _D31 = 0)> (V _CC
+ | V _TP | -V _TN35 ) (4) where V _PP = 12V, V _CC = 5V, V _TP31 = V _TP32 −1V, V _TN35 = 1
_Assuming V, the voltage range of V _D31 (I _D31 = 0) is
Becomes

10V> V _D31 (I _D31 = 0)> 5V (5) That is, V _R11 -V _TN11 shown in FIG. 2 can be set to any voltage within the range of 10V to 5V, so a high voltage is applied to the drain, V _D31 than the voltage V _BD avalanche breakdown occurs (I
_D31 = 0) can be set low. Therefore, to prevent avalanche breakdown, N-type MO
Since it is not necessary to set the load resistances of the SFETM ₃₅ and the column selection N-type MOSFETs MY ₃₁ , MY _{32 to} MY _3n to be large, for example, the voltage-current characteristic of the memory transistor in the non-written state is changed from the solid line 21 to the solid line 22 in FIG. Even if there is a change, the drain voltage of the memory transistor in the initial state at the time of the write operation is V _W22 , which is a small change, and therefore the write speed is not _{significantly} deteriorated.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

In order to realize a non-volatile semiconductor memory device having an 1-bit configuration, the memory transistors arranged in a matrix are divided _into 1 blocks MA ₄₁ , MA _{42 to} MA _4l , and column selection N-type MOSFET MY ₄₁₁ , MY _{412 to} MY _4ln , sense amplifier circuits SA ₄₁ , SA _{42 to} SA _4l , N-type MOSF provided between the write voltage V _PP and the drain of the column selection N-type MOSFET.
ETMs ₄₁ , M _{42 to} M _4l and write control circuits W _{R41 to} W _R4l are provided. Further, one constant voltage generation circuit V _CON41 is provided, and its output voltage V _R41 is _supplied to each write control circuit.
By connecting to W _R41 , W _{R42 to} W _R4l ,
The same effect as the embodiment shown in the figure can be obtained. Further, since only one constant voltage generating circuit needs to be provided, it is possible to suppress an increase in space due to providing the constant voltage generating circuit when the circuit is realized on the semiconductor substrate.

〔The invention's effect〕

As described above, the present invention has a power supply terminal to which a write voltage is supplied to write information in a memory transistor,
Provided between the memory transistor and this power supply terminal
By providing a MOSFET, a constant voltage generation circuit that generates a constant voltage lower than the write voltage, and a write control circuit that selectively applies the output voltage of the constant voltage generation circuit according to write information to the gate of the MOSFET. Even if a high voltage is applied to the drain of a memory transistor in the non-selected write state during a write operation, the drain voltage of the memory transistor can be set lower than the voltage at which avalanche breakdown occurs, so the write voltage and the memory transistor The load resistance formed by the MOSFET provided between and does not need to be set so large, and even if the voltage-current characteristics of the memory transistor in the non-written state changes due to variations in the manufacturing stage, the drain voltage during writing remains Since it does not change much, the writing speed does not deteriorate much, and the memory Timing adjustment such a high voltage is applied to the gate to the drain from the high voltage of Njisuta is unnecessary, there is an effect that the circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a characteristic diagram showing write characteristics of the present invention, FIG. 3 is a circuit diagram showing in detail the block diagram shown in FIG. 1, and FIG. FIG. 6 is a circuit diagram of another embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional write circuit, and FIGS. 6A and 6B are characteristic diagrams of the write circuit of FIG. 5 and FIG. (A), (b) and (c) are a cross-sectional view, a symbol view and a characteristic view of a MOS type field effect transistor having a two-layer gate structure used in a nonvolatile semiconductor memory device, respectively. V _CON11 , V _CON31 , V _CON41 ...... Constant voltage generator, W _R11 , W _R31 ,
W _{R41 to} W _R4l ... write control circuit, SA ₃ , SA _{41 to} SA _4l ... sense amplifier circuit, MC ₁₁ , MC _{311 to} MC _3mn , MC ₅₁ ... memory transistor.

Claims (1)

[Claims] 1. A nonvolatile semiconductor memory element capable of electrically writing information is used as a storage medium, and the first write voltage is MO.
The first through the load resistor formed by the S transistor
Is supplied to the drain of the storage medium as a second write voltage lower than the write voltage of the load resistance MOS, and the second write voltage supply operation is selectively performed in response to predetermined write information. In a non-volatile semiconductor memory device including a write voltage control unit for controlling conduction / non-conduction of a transistor, the write voltage control unit is the first
A constant voltage generation circuit for generating a constant voltage lower than the write voltage of and higher than the power supply voltage, and a write control circuit for selectively supplying the constant voltage to the gate of the load resistance MOS transistor in response to the write information. The constant voltage generating circuit is inserted in series between the potential of the first write voltage and the power source potential, each substrate potential is connected to the same potential as the source, and the gate is connected to the drain. The write control circuit is configured to output a voltage at a series connection point of a plurality of MOS transistors of the same conductivity type as the constant voltage, and the write control circuit serves as an inverter that receives the write information, and has a level of either the constant voltage or the ground voltage. Are arranged so that the storage mediums are arranged in an array and the array is divided into a plurality of blocks so that a plurality of bits of data are A memory device capable of simultaneously writing and reading data, comprising one constant voltage generating circuit, the load resistance MOS transistors for the plurality of bits, and the write control circuit for the plurality of bits. A characteristic non-volatile semiconductor memory device.