JPH07101559B2 - Nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a nonvolatile semiconductor memory device such as EPROM, EEPROM, etc., and particularly to a sense amplifier thereof.

[Conventional technology]

FIG. 4 shows a sense amplifier section of a conventional EEPROM. A 1-bit memory cell is composed of a selection transistor 2 connected to a gate word line 1 and a memory transistor 3 having a floating gate. The gate (control gate) of the memory transistor 3 is connected to the control gate line 5 via the selection transistor 4 whose gate is connected to the word line 1, and the drain of the selection transistor 2 is connected to the bit line 6. The bit line 6 and the control gate line 5 are connected to the I / O line 10 and the CG line 11, respectively, through the transistors 8 and 9 whose gates receive the Y gate signal 7. The sense amplifier comprises a current-voltage conversion circuit 12 and first and second inverters 13 and 14.

Next, the operation will be described. The EEPROM memory transistor 3 stores binary information depending on whether or not electrons are stored in the floating gate. When electrons are stored, the threshold value of the memory transistor becomes high, and it turns off during reading. In this state, "1" is stored.
If electrons are not stored, the threshold value of the memory transistor becomes negative, and it turns on during reading. In this state, "0" is stored. The current-voltage detection circuit 12 detects whether or not a current is passed through the memory transistor 3 of the selected memory cell. When the current does not flow, it outputs a voltage of about the power supply voltage, and when the current flows, it outputs about 1V. This output is amplified by the inverters 13 and 14.

FIG. 6 shows an example of the current-voltage conversion circuit. It is composed of P-channel MOS transistors 15, 18 whose gates are grounded and N-channel MOS transistors 16, 17, 19. When the information "0" is read, the potential of the node a becomes approximately 1.0 V in the steady state. This makes the transistor
16 is turned on to some extent, and the potential of the node b becomes, for example, approximately 2V. Therefore, the transistors 17 and 19 are turned on to some extent, but since the on resistance of 18 is set to be larger than that of 19, the potential of the output {circle around ()} is approximately the same as the potential of the node a. That is, it is about 1V.

On the other hand, when "1" is written, the potential of the node a is, for example, about 1.1V. Therefore, the potential of the node b becomes about 1.8V, the gate-source potential of the transistors 17, 19 becomes about 0.7V, and these transistors 17, 19 are turned off. As a result, the potential of the output ▲ ▼ is raised to 5V by the transistor 18.

Further, another conventional example is shown in FIG. A reference circuit is provided, and the characteristics of the current-voltage conversion circuit 12a on the reference side are set so that the intermediate level between "L" and "H" of the current-voltage conversion circuit 12 output on the memory cell side is output. However, such a circuit is used only in EPROM and requires a reference cell, so it is difficult to apply it to EEPROM.

[Problems to be Solved by the Invention]

Since the conventional nonvolatile semiconductor memory device is configured as described above, the state in which the address is switched and the cell in which "0" is stored is read out from the cell in which "1" is stored is read out. When switched to, there is a problem that it takes time to charge the I / O lines and bit lines, and the inversion of the sense amplifier output is delayed. In addition, the method using the differential amplifier is EEPROM
There is a problem that it is difficult to apply to.

The present invention has been made to solve the above problems, and has a sense amplifier capable of high speed access,
An object is to obtain a non-volatile semiconductor memory device that can be applied to EEPROM.

[Means for Solving the Problems]

The nonvolatile semiconductor memory device according to the present invention is a dummy I / O.
A line and a dummy bit line, a reset transistor connected to the bit line and the dummy bit line, respectively, for resetting the bit line and the dummy bit line by an address change, and a current-voltage conversion circuit connected to the bit line. An output and an output of the current-voltage conversion circuit connected to the dummy bit line are input, a differential amplifier activated after a predetermined time has elapsed from the reset operation, and connected to the dummy bit line. The resistance value of the load resistance provided between the output node of the current-voltage conversion circuit and the power supply potential is determined by the resistance value of the load resistance provided between the output node of the current-voltage conversion circuit connected to the bit line and the power supply potential. The characteristic of the current-voltage conversion circuit that is set higher than the resistance value and that is connected to the dummy bit line is the current-voltage conversion circuit connected to the bit line. Those which made different from the characteristics.

[Action]

In the present invention, a dummy I / O line and a dummy bit line, a reset transistor connected to the bit line and the dummy bit line, respectively, for resetting the bit line and the dummy bit line by an address change, and the bit line An output of the connected current-voltage conversion circuit and an output of the current-voltage conversion circuit connected to the dummy bit line are input, and a differential amplifier activated after a predetermined time has elapsed from the reset operation is provided. The resistance value of the load resistance provided between the output node of the current-voltage conversion circuit connected to the dummy bit line and the power supply potential is set to the output node of the current-voltage conversion circuit connected to the bit line and the power supply. The characteristic of the current-voltage conversion circuit connected to the dummy bit line is set to be higher than the resistance value of the load resistance provided between the potentials. Since the configuration differs from the characteristics of the connected current-voltage conversion circuit, the bit line and the dummy bit line are reset when the address changes, and then the output of the current-voltage conversion circuit connected to the bit line and the dummy bit. By differentially amplifying the output of the current-voltage conversion circuit connected to the line, high-speed access becomes possible without requiring a reference cell.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a sense amplifier section of a nonvolatile semiconductor memory device according to an embodiment of the present invention. Dummy I / O line 2
0 is provided, and the reference side current-voltage conversion circuit 21
Connected to. The dummy I / O line 20 is connected to the drain of the transistor 22 whose gate receives the signal YG, and the source of the transistor 22 is connected to the dummy bit line 23.
A reset transistor 24 whose reset signal RST is input to the gates of all the bit lines 6 and dummy bit lines 23,
25 are connected. The outputs of the current-voltage conversion circuits 12 and 21 are
The signal VT is input to the differential amplifier including transistors 28 to 31 via the transistors 26 and 27 whose gates are input. The sources of the P-channel MOS transistors 28, 30 are P-channel MOS whose signals are input to the gates.
It is connected to the power supply through the transistor 32. The sources of the transistors 29 and 31 are grounded via the transistor 33 whose gate receives the signal S ₀ . The two nodes N1 and N2 of the differential amplifier are transistors to which the gate signal RST is input.
Grounded via 34 and 35. Output RD of differential amplifier, ▲
▼ indicates transistors 36 and 37 whose signal SDT is input to the gate
Taken out through.

Next, the operation will be described. FIG. 2 shows a clock timing diagram of the apparatus shown in FIG. 1, and FIG. 3 shows the simulation result. When the input address changes, this is detected and an ATD pulse is output (the circuit is not shown). This signal causes the RST signal to go to "H", and all bit lines 6 and dummy bit lines 23 are grounded. Then signal
YG becomes "H", the selected Y gate signal 7 becomes "H" at the same time, and the current-voltage conversion circuits 12 and 21 are connected to the bit line 6 and the dummy bit line 23. As a result, the bit line 6 and the dummy set line 23 are started to be charged by the current-voltage conversion circuits 12 and 21. If “1” is written in the selected memory cell, the output (node N3) potential of the current-voltage conversion circuit 12 gradually rises after the charging of the bit line 6 is completed. If "0" is written, the potential of the node N3 remains low.

On the other hand, on the reference side, the size of the load transistor (transistor 18 shown in FIG. 6) of the current-voltage conversion circuit 21 is set to be smaller than that of the current-voltage conversion circuit 12 on the memory cell side. The potential of N4 rises more slowly than the node N3 when reading "1". The level of the node N4 is in the middle of the level of the node N3 when "1" is read and when "0" is read. When the potential difference between the node N3 and the node N4 is reached, the differential amplifier is activated by setting ▲ ▼ = "L" (S ₀ = "H"), and the potential difference between the nodes N3 and N4 is amplified.
However, at this time, the signal VT does not become "L", and the current-voltage conversion circuits 12 and 21 and the differential amplifier are disconnected. In addition, dummy I / O
Layout of line 20 and dummy bit line 23, stray capacitance is I / O
The line 10 and the bit line 6 are set to be almost the same.

As described above, the current-voltage conversion circuit on the reference side in this embodiment outputs “L” from the current-voltage conversion circuit on the memory cell side when the address changes and the read data changes.
/ Outputs the intermediate potential of "H". Furthermore, in the device according to the present embodiment, the potential difference is rapidly amplified by activating the differential amplifier after a predetermined time when the address changes. Therefore, even if the address is switched, the inversion of the sense amplifier output is not delayed, and since a reference cell is not required on the reference side, not only EPROM but also EEPRO
It can also be used for M.

〔The invention's effect〕

As described above, according to the nonvolatile semiconductor memory device of the present invention, the dummy I / O line and the dummy bit line are provided on the reference side, all the bit lines and the dummy bit line are reset when the address changes, and the sense output is generated. Since it was configured to amplify rapidly with a differential amplifier after the level difference was attached,
High-speed access is possible, and there is an effect that the one applicable to EEPROM can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a nonvolatile semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a diagram showing a clock timing diagram thereof, FIG. 3 is a diagram showing simulation results thereof, and FIG. 4 is a conventional nonvolatile memory device. FIG. 5 is a diagram showing a conventional semiconductor memory device, FIG. 5 is a diagram showing another conventional nonvolatile semiconductor memory device, and FIG. 6 is a diagram showing an example of a current-voltage conversion circuit. 6 is a bit line, 12 and 21 are current-voltage conversion circuits, 20 is a dummy I / O line, 23 is a dummy bit line, and 24 and 25 are reset transistors. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masanori Hayashikoshi 4-1-1 Mizuhara, Itami City, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Laboratory (72) Inventor Yoshikazu Miyawaki 4-Mizuhara, Itami City, Hyogo Prefecture No. 1 Mitsubishi Electric Corporation LSI Research Center

Claims (1)

[Claims] 1. A dummy I / O line and a dummy bit line, and a bit line and the dummy bit line, respectively,
A reset transistor for resetting the bit line and the dummy bit line by an address change, an output of the current-voltage conversion circuit connected to the bit line and an output of the current-voltage conversion circuit connected to the dummy bit line. A resistance of a load resistor provided between the output node of the current-voltage conversion circuit connected to the dummy bit line and the power supply potential, the differential resistance being an input and activated after a predetermined time has elapsed from the reset operation. The value is set higher than the resistance value of the load resistance provided between the output node of the current-voltage conversion circuit connected to the bit line and the power supply potential, and the current-voltage connected to the dummy bit line. A characteristic of the conversion circuit is different from that of the current-voltage conversion circuit connected to the bit line.