JPH0710050B2 - Interference compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used for digital or analog signal transmission. In particular, it relates to an interference compensation circuit that removes interference signals from other transmission systems.

[Conventional technology]

FIG. 27 is a block diagram of a conventional interference compensation circuit.
This circuit is equivalent to, for example, the circuit disclosed in Japanese Patent Laid-Open No. 62-147818.

The main signal (here, a digital signal) received by the main antenna 1 for receiving the main signal includes an interference signal from another transmission system, for example, a signal of another transmission system. This received signal is supplied to the frequency converter 3 via the bandpass filter 2 and is frequency-converted by the frequency converter 3 into an intermediate frequency band.

On the other hand, the signal that causes interference is received by directing the auxiliary antenna 4 toward the interference source.
The signal received by the auxiliary antenna 4 passes through the band pass filter 2 for improving the signal-to-noise ratio, and then the local oscillator 5
The frequency converter 3 frequency-converts into an intermediate frequency band using a local oscillation signal common to the main signal side supplied from.

The phase and amplitude of this interference signal are adjusted by the variable phase circuit 6 and the variable amplitude circuit 7, and a compensation signal having the opposite phase and the same amplitude as the interference component mixed in the main signal is generated.
By adding this compensation signal by the adder 8, the interference signal component mixed in the main signal can be removed.

To control the variable phase circuit 6 and the variable amplitude circuit 7,
An error signal and an interference signal are obtained for each of the in-phase and quadrature components.

The output of the adder 8 is supplied to the demodulator 100 in order to detect the in-phase and quadrature components of the interference component remaining in the main signal after the compensation signals have been added by the adder 8. The quadrature phase detectors 12 and 13 in the demodulator 100 detect the output of the adder 8 using the reference carrier 10 reproduced from the main signal, and decompose it into an in-phase component and a quadrature component. The signals of these components pass through the harmonic elimination filters 14 and 15 and the error signal generating circuits 101 and 102.
Is supplied to. The error signal generation circuits 101 and 102 detect the residual interference components and generate error signals of the in-phase component and the quadrature component, respectively.

On the other hand, the interference signal that has passed through the variable phase circuit 6 is divided into two by the distributor 9, one of which is output to the variable amplitude circuit 7 and the other is input to the quadrature phase detectors 20 and 21. The quadrature phase detectors 20 and 21 decompose the interference signal into an in-phase component and a quadrature component using the reference carrier wave 10 reproduced by the demodulator 100 on the main signal side. The decomposed interference signal is passed through the harmonic elimination filters 22 and 23 to the identification circuit 24,
Supplied to 25. The identification circuits 24 and 25 are demodulators for the main signal.
The interference signal is binarized using the timing signal obtained at 100.

Since the case where digital processing is performed is described here as an example, the identification circuits 24 and 25 are required for binarization. In the case of analog processing, these are unnecessary.

Further, when the outputs of the error signal generation circuits 101 and 102 are output as digital signals, an analog / digital converter can be used. In that case, for example, the main signal is 16QA
In the case of M signal, the demodulated signal is a four-valued signal, so 3
Sample with an analog-to-digital converter that has more than one bit of output. The digital output at that time is shown in the table. At this time, in the digital output, the upper 2 bits indicate the identification result, and the third bit from the top indicates the error direction. Therefore, the third bit from the top is used as the error signal. At this time, the most significant bit of the upper two bits becomes the polarity signal.

The correlation between the in-phase component and the quadrature component of the error signal and the interference signal thus obtained is obtained.

That is, the exclusive OR circuits 26 and 27 obtain exclusive OR of the orthogonal components and the in-phase components,
The output is supplied to the integrator 30 via the resistors 28 and 29, and the output of the integrator 30 is used as the control signal of the variable amplitude circuit 7. Further, the exclusive OR circuits 31 and 32 obtain the exclusive OR of the in-phase component and the quadrature component, and the output thereof is supplied to the integrator 35 via the resistors 33 and 34, and the output of the integrator 35 is supplied. This is a control signal for the variable phase circuit 6.

[Problems to be solved by the invention]

However, in the conventional interference compensation circuit, in order to obtain the interference signal, it is necessary to receive the signal that causes the interference signal. That is, it is necessary to provide an auxiliary antenna that receives only signals that cause interference. Therefore, when the propagation paths of the main signal and the interference signal are the same, the signal causing the interference cannot be accurately obtained, and the interference signal cannot be removed.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide an interference compensation circuit that can sufficiently remove an interference signal even when a signal that causes interference cannot be directly obtained.

[Means for solving problems]

The interference compensation circuit of the present invention includes a first reception circuit that receives a signal in which an interference signal is mixed with a main signal, and a second reception circuit that is provided in a system separate from the first reception circuit and that receives a signal including the interference signal. A circuit, first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit, and In the interference compensation circuit including first control means for controlling the first adjusting means so that the interference signal included in the output of the subtracting means is sufficiently small, the second receiving circuit is a signal received by the first receiving circuit. And a second adjusting means for adjusting the amplitude and phase of the signal received by the second receiving circuit, and the second adjusting means. From the output of the first receiving circuit And a second control means for controlling the second adjusting means so that the interference signal included in the output of the second subtracting means has a level sufficiently higher than that of the main signal. And

In the present specification, “subtraction” means addition in reverse phase. Therefore, when adjusting the phase to the opposite phase in the first adjusting means or the second adjusting means, the first subtracting means or the second subtracting means respectively add two signals. Moreover, "addition" includes in-phase addition and anti-phase addition.

A variable amplitude circuit and a variable phase circuit are used as the first adjusting means and / or the second adjusting means. A quadrature amplitude modulator may be used instead of these circuits.

The output of the second subtraction means may be connected to the first adjusting means, and the reception signal of the second receiving circuit may be connected thereto. In the former case, the interference signal is removed from the reception signal of the first reception circuit. In the latter case, the two received signals are added so that the interference signal becomes sufficiently small.

Further, a first receiving circuit for receiving a signal in which an interference signal is mixed with a main signal, a second receiving circuit provided in a system separate from the first receiving circuit for receiving a signal including the interference signal, and the first receiving circuit A receiving circuit and a synthesizing circuit for synthesizing the main signals received by the second receiving circuit, a first quadrature detecting means for quadrature detecting the output of the synthesizing circuit and converting it into a digital signal, and an output of the first receiving circuit. Second quadrature detection means for quadrature detection and conversion to a digital signal, third quadrature detection means for quadrature detection of the output of the second receiving circuit and conversion to a digital signal, and third quadrature detection means First to fourth variable couplers for adjusting the amplitude and phase of the output of the above, and first to fourth summation of the outputs of the first to fourth variable couplers and the second quadrature detection means. Four full adders, and the first to the above A variable combiner control circuit for controlling the first to fourth variable combiners so as to minimize the main signal component of the output of the fourth adder; and the amplitudes of the outputs of the first to fourth full adders. And fifth to eighth variable couplers for adjusting the phase, fifth to eighth full adders for adding the output of the first quadrature detection means and the outputs of the fifth to eighth variable couplers. And a variable coupler control circuit for controlling the fifth to eighth variable couplers so as to cancel the interference component in the main signal output from the fifth to eighth adders.

[Action]

The phase difference between the main signal passing through one propagation path and the interference signal is usually different from the phase difference passing through the other propagation paths. Therefore, a signal in which an interference signal is mixed with a main signal is received on each of a plurality of propagation paths. An interference signal with high purity can be obtained by synthesizing these signals with mutually opposite phases and equal amplitudes. Using this interference signal, the interference signal component is removed from the received signal.

When the propagation path is a wireless transmission path, an antenna is provided for each propagation path. However, it is not necessary to point these antennas in different directions. For example, when the interference signal source is in the same direction as the main signal source, the plurality of antennas are oriented in the same direction and each receives the main signal mixed with the interference signal.

〔Example〕

FIG. 1 is a block diagram of an interference compensation circuit according to the first embodiment of the present invention.

This interference compensation circuit includes a main antenna 1 as a first reception circuit for receiving a signal in which an interference signal is mixed with a main signal, and the number of times of output thereof, and is a signal that is provided in a system separate from the first reception circuit and includes the interference signal. An auxiliary antenna 4 and an output circuit thereof as a second receiving circuit for receiving, and a variable amplitude circuit 41 and a variable phase circuit 42 as first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, The adder 40 is provided as a first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit.
A control circuit for controlling the variable amplitude circuit 41 and the variable phase circuit 42 so that the interference signal included in the output of 40 is sufficiently small.
Equipped with 106.

Here, the feature of this embodiment is that the auxiliary antenna 4
However, the second antenna for adjusting the amplitude and the phase of the signal received by the auxiliary antenna 4 is used in the output circuit of the auxiliary antenna 4 in the configuration in which the signal received through the propagation path different from the signal received by the main antenna 1 is received. Variable amplitude circuit as adjusting means
37 and a variable phase circuit 38, an adder 39 is provided as a second subtracting means for subtracting the output signal of the first receiving circuit from the output of the second adjusting means, and the interference signal included in the output of the adder 39 A control circuit for controlling the variable amplitude circuit 37 and the variable phase circuit 38 so that the level is sufficiently higher than the main signal.
With 105.

The main antenna 1 and the auxiliary antenna 4 are oriented toward the main signal transmission source. Here, the main signal is assumed to be a digital signal. In this case, the interference sources are also in the same direction. Therefore, the main antenna 1 and the auxiliary antenna 4 simultaneously receive the interference signal together with the main signal.

The reception signal of the main antenna 1 is distributed and supplied to one input of the adder 39. Further, the reception signal of the auxiliary antenna 4 is supplied to the other input of the adder 39 via the variable amplitude circuit 37 and the variable phase circuit 38.

Here, to extract the interference signal from the output of the adder 39,
It suffices that the main signal included in one input of the adder 39 has an equal amplitude opposite phase to the main signal included in the other input.
Therefore, the control circuit 105 detects the relative amplitude and phase difference between the reception signal received from the auxiliary antenna 4 and the reception signal distributed from the main antenna 1, and outputs the variable amplitude circuit 37 and the variable phase circuit 38 from the output. Control. As a result, the main signal is canceled at the output of the adder 39, and only the interference signal is obtained.

The interference signal mixed in the main signal is removed by using the interference signal extracted as described above. This method will be described.

The interference signal output from the adder 39 is supplied to one input of the adder 40 via the variable phase circuit 42 and the variable amplitude circuit 41. The reception signal of the main antenna 1 is supplied to the other input of the adder 40. Here, in order to remove the interference signal from the output of the adder 40, the interference signals at the two inputs of the adder 40 are made equal in phase and opposite in phase.

Therefore, the control circuit 106 detects the relative amplitude difference and phase difference between the interference signal output from the adder 39 and the interference component in the reception signal of the main antenna 1, and the interference signal and the interference component are equal to each other. The variable phase circuit 42 and the variable amplitude circuit 41 are controlled so as to have opposite phases in amplitude.

In this way, the interference signal can be automatically extracted from the signal mixed with the interference signal, and the interference compensation can be automatically performed by the interference signal.

FIG. 2 is a block diagram of an interference compensation circuit according to the second embodiment of the present invention. This embodiment differs from the first embodiment in that a wired transmission line 1'is used instead of the main antenna 1 and the auxiliary antenna 4. That is, the present invention can be implemented not only for wireless signals but also for wired signals.

In the above embodiments, the circuit configuration is shown in a simplified manner in order to explain the essential points of the present invention. Further specific configurations will be described in the following embodiments.

FIG. 3 is a block diagram of the interference compensation circuit of the third embodiment of the present invention.

The interference compensation circuit includes a main antenna 1, a bandpass filter 2, a frequency converter 3, and a local oscillator 5 as a first reception circuit that receives a signal in which an interference signal is mixed with a main signal. An auxiliary antenna 4, which is provided in a separate system and serves as a second receiving circuit for receiving a signal including an interference signal
The band pass filter 2, the frequency converter 3, and the local oscillator 5 common to the first receiving circuit are provided, and the variable phase circuit 6'and the variable phase circuit 6'are used as the first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit. An amplitude circuit 7'is provided, and an adder 8 is provided as first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit, and the interference signal included in the output of the first subtracting means is sufficient. As the first control means for controlling the variable phase circuit 6'and the variable amplitude circuit 7'to be small, the phase detector 21 and the harmonic elimination filter 2
3, a discrimination circuit 25, a demodulator 100 and a correlation detection circuit 107.

The auxiliary antenna 4 receives a signal that has passed through a propagation path different from the signal received by the main antenna 1.

The second receiving circuit is further provided with a variable phase circuit 6 and a variable amplitude circuit 7 as second adjusting means for adjusting the amplitude and phase of the signal received by the auxiliary antenna 4, and the first receiving means outputs from the output of the second adjusting means. An adder 8'is provided as a second subtraction means for subtracting the output signal of the circuit, and the variable phase circuit 6 and the variable amplitude circuit 6 are provided so that the interference signal included in the output of the adder 8'has a level sufficiently higher than the main signal. A quadrature phase detector 108, a correlation detection circuit 109, and a phase detector 21, which is common to the first control means, as a second control means for controlling 7.
A harmonic elimination filter 23 and a discrimination circuit 25 are provided.

The main antenna 1 and the auxiliary antenna 4 are directed to a transmission source for transmitting a digitally formed main signal. An interference signal leaks into this main signal. The reception signals of the main antenna 1 and the auxiliary antenna 4 are supplied to the frequency converter 3 via the bandpass filter 2 for improving the S / N. The frequency converter 3 uses the local oscillation signal supplied from the common local oscillator 5 to convert each reception signal into an intermediate frequency band.

The signals converted into the intermediate frequency band are respectively distributed by the distributors 9,
Input to 9 '. One output of the distributor 9 is an adder 8 '.
To the variable amplitude circuit 7
And is input to the adder 8'through the variable phase circuit 6. The variable amplitude circuit 7 and the variable phase circuit 6 are feedback-controlled so that the main signal components contained in the two inputs of the adder 8'have the same amplitude and opposite phase. As a result, the main signal component is significantly attenuated at the output of the adder 8 ', and an interference signal leaking into the main signal is obtained.

This feedback control is performed as follows.

The two main signals received by the main antenna 1 and the auxiliary antenna 4 are added by an adder 8'so that they have mutually equal amplitudes in opposite phases. After this addition, correlation detection is performed between the remaining main signal component and the main signal before addition, and the variable amplitude circuit 7 and the variable phase circuit 6 are arranged so that the correlation amount is minimized.
Control and to adjust the amplitude and phase. This allows
The main signal remaining after synthesis can always be minimized.

Regarding the main signal remaining after addition, the main signal is dominant at the time when the interference compensation circuit is started. But,
As the interference compensation operation proceeds to the steady operation, the interference signal component included in the main signal emerges and is output as an interference signal from the adder 8 '.

Specifically, the output of the adder 8 ', that is, the interference signal remaining after the main signal is removed, is phase-detected by the phase detector 21 using the reference carrier wave 10 reproduced by the demodulator 100 on the main signal side, The harmonic components are removed by the harmonic elimination filter 23, and the output of the harmonic elimination filter 23 is demodulated by the demodulator 100.
The discrimination circuit 25 binarizes the clock signal 36 regenerated in (1). As a result, a binarized interference signal is obtained.

The other output of the distributor 9'is input to a quadrature detector 108 which decomposes the signal into an in-phase component and a quadrature component. This input is phase-detected by the quadrature phase detectors 20 and 21 using the reference carrier wave 10. This phase detection output is
After the harmonic components are removed by the harmonic elimination filters 22 and 23, they are binarized by the discrimination circuits 24 'and 25'. As a result, binarized main signals of the in-phase component and the quadrature component are obtained. Here, the identification circuits 24 'and 25' are connected to the demodulator 10
Binarization is performed using the clock signal 36 reproduced at 0.

An exclusive OR circuit 27 digitally multiplies the main signal of the in-phase component obtained from the discrimination circuit 25 'and the residual main signal (interference signal) output from the discrimination circuit 25 that is relatively in phase with the main signal. , The result is integrated by the integrator 30. The output of the integrator 30 controls the variable amplitude circuit 7.

Similarly, an exclusive OR circuit 31 is used for the main signal of the quadrature component output from the discriminating circuit 24 'and the residual main signal (interference signal) output from the discriminating circuit 25 which is relatively orthogonal to the main signal.
, And the result is integrated by the integrator 35. The output of the integrator 35 controls the variable phase circuit 6.

The identification circuits 25, 24 ', 25' are for ensuring the operation of the exclusive OR circuit 31 and are not always necessary.

As described above, it is possible to automatically extract the interference signal mixed in the main signal and cancel the interference signal. In this case, a delay circuit is provided in at least one signal path so that the delay times of the two main signals in the adder 8'match.

Next, using this interference signal, the interference component remaining in the received signal of the main antenna 1 is eliminated. That is, by using the interference signal obtained by the above operation, the variable phase circuit 6 '
And the variable amplitude circuit 7 ′ are sequentially controlled, and the adder 8 adds the output of the variable amplitude circuit 7 ′ to the other output of the distributor 9. At this time, the output signal of the variable amplitude circuit 7'is
The interference signal component mixed in the main signal output from the distributor 9 is controlled so as to have almost the opposite phase and the same amplitude. Therefore, the interference signal component is removed from the output of the adder 8.

The control of the variable phase circuit 6'and the variable amplitude circuit 7'will be described below.

The main signal combined by the adder 8 is input to the demodulator 100. In the demodulator 100, the reference carrier 10 regenerated from the main signal is used, the main signal is quadrature detected by the quadrature phase detectors 12 and 13, and the output signals are passed through the harmonic elimination filters 14 and 15, respectively, to obtain the in-phase signal. And a quadrature baseband signal. The obtained baseband signals are input to error signal generation circuits 101 and 102, respectively. The error signal generation circuits 101 and 102 are composed of discrimination circuits 16 and 18, respectively, and subtractors 17 and 19 that take the difference between their input and output, and these subtractors 17 and 19 output error signals.

When a 16QAM signal is used as the main signal, an analog / digital converter of 3 bits or more can be used as the error signal generating circuit. By demodulating the 16QAM signal, a four-valued baseband signal is obtained. An identification circuit (analog
Digital conversion circuit), as shown in the table above, the upper 2 bits of the output are the identification signal, and
Since the bit becomes an error signal, the error signal can be obtained from the third bit onward.

On the other hand, the interference signal output from the adder 8'and passed through the distributor 9 is phase-detected by the phase detector 21 using the reference carrier 10, the harmonic component is removed by the harmonic removal filter 23, and the discrimination circuit Binarized by 25. This allows
A binary interference signal is obtained. The identification circuit 25 uses the clock signal 36 reproduced by the demodulator 100 to execute the binarization operation.

Next, correlation detection is performed between the in-phase and quadrature component error signals obtained by the demodulator 100 and the interference signal binarized by the identification circuit 25. That is, the error signal of the in-phase component and the interference signal are digitally multiplied by the exclusive OR circuit 27,
The output is integrated by the integrator 30, and the output controls the variable amplitude circuit 7 '. On the other hand, the quadrature component error signal and the interference signal are digitally multiplied by the exclusive OR circuit 31, the output thereof is integrated by the integrator 35, and the variable phase circuit 6'is controlled by the output signal.

In this way, interference compensation can be automatically performed. Here, the binary multiplication by the exclusive OR circuits 27 and 31 is shown as an example, but the binarization circuit of the interference signal is not always necessary. In that case, instead of the exclusive OR circuit, analog multiplication is performed. Use a vessel.

FIG. 4 is a block diagram of the interference compensation circuit according to the fourth embodiment of the present invention.

This embodiment differs from the third embodiment in that a quadrature amplitude modulator is used instead of the variable amplitude circuit and the variable phase circuit in order to control the amplitude and phase of the main signal and the amplitude and phase of the interference signal. . That is, the quadrature amplitude modulator 111 is provided as the first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, and the quadrature is provided as the second adjusting means for adjusting the amplitude and phase of the signal received by the second receiving circuit. An amplitude modulator 110 is provided.

The quadrature amplitude modulator 110 includes a distributor 43 that distributes an input signal.
A 90 ° phase shifter 11 that shifts one of the outputs of the divider 43 by 90 degrees, a π / 2 phase bipolar variable attenuator 45 that adjusts the amplitude of the output of the phase shifter 11, and a divider. It is composed of a zero-phase variable polarity attenuator 46 that adjusts the amplitude of the other output of the converter 43, and an adder 44 that combines the outputs of the variable polarity attenuators 45 and 46.

Similarly, the quadrature amplitude modulator 111 has a distributor 43 and a 90 ° phase shifter 1
1, a bipolar variable attenuator 45, 46, and a combiner 44.

The zero-phase bipolar variable attenuator 46 in the quadrature amplitude modulator 110 is
Controlled by the output of the integrator 30 of the correlation detection circuit 109,
The π / 2-phase bipolar variable attenuator 45 is controlled by the output of the integrator 35.

Similarly, the zero-phase bipolar variable attenuator 46 and the π / 2-phase bipolar variable attenuator 45 in the quadrature amplitude modulator 111 are also included in the correlation detection circuit 10.
It is controlled by the outputs of integrator 30 and integrator 35 in 7, respectively.

FIG. 5 is a block diagram of the interference compensation circuit of the fifth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that a control gain is obtained by performing analog multiplication using the multipliers 47 and 48 without using the exclusive OR circuit for correlation detection.

FIG. 6 is a block diagram of an interference compensation circuit according to a sixth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that analog / digital converters 49, 50 51, 52, 53 are used instead of the error signal generating circuits 101, 102 and the discrimination circuits 25, 24 ', 25'. .

When 16QAM is considered as the main signal, as shown in the table above, if an analog-digital converter having an output of 3 bits or more is used, the upper 2 bits of the output show the discrimination result, The third bit from to represents an error signal.
Therefore, the error signal can be obtained using the third and subsequent bits from the top.

The analog-digital converters 49 to 53 are the main signal demodulator 10
Each input signal is sampled using the clock signal 36 reproduced at 0. Then, the first bit (polarity signal) from the output of the analog-digital converter 51 that converts the baseband signal of the interference signal into a digital signal
And the third bit (error signal) from the top of the analog-to-digital converters 49 and 50 are detected, and the correlation signal is used to output the bipolar variable attenuators 45 and 4 of the quadrature amplitude modulator 111.
Control 6 As a result, the interference signal is removed.

On the other hand, the quadrature phase detector 10 connected to the output of the distributor 9 '
The eight analog-digital converters 52 and 53 output the first bit (polarity signal) from the quadrature component and the in-phase component, respectively. Correlation detection is performed between this signal and the first bit of the analog-digital converter 51, and the quadrature amplitude modulator 110 is controlled by the correlation signal to control the bipolar variable attenuators 45 and 46 and mixed in the main signal. Extract the interfering signal.

FIG. 7 is a block diagram of the interference compensation circuit of the seventh embodiment of the present invention.

In this embodiment, in order to binarize the extracted interference signal,
The quadrature phase detector 108 is used instead of the phase detector, and in order to binarize the output of the distributor 9 ', the phase detector 21 and the discrimination circuit 25' are used instead of the quadrature phase detector to detect the respective correlations. Is different from the third embodiment.

Also, although the configuration of the correlation detection circuit 107 is slightly different, this is the same configuration as the control circuit 104 shown in the conventional example.

FIG. 8 is a block diagram of an interference compensation circuit according to an eighth embodiment of the present invention.

This embodiment differs from the third embodiment in that the quadrature phase detectors 20 and 21 are used to binarize the extracted interference signal.
With this configuration, although the circuit scale is larger than that of the third embodiment, the control gain is doubled, and the control response and convergence are improved.

The configuration of the correlation detection circuit 107 is the same as that of the seventh embodiment.

FIG. 9 is a block diagram of the interference compensating circuit according to the ninth embodiment of the present invention.

This embodiment differs from the fourth embodiment in that the auxiliary antenna 4 is replaced by a sub-antenna 55 for receiving space diversity. Thereby, it is not necessary to newly install the auxiliary antenna 4, and the antenna installation can be made efficient and economical. The phase shifter 56 is a phase shifter that adjusts the space diversity combined phase.

FIG. 10 is a block diagram of the interference compensation circuit of the tenth embodiment of the present invention.

This embodiment is different from the ninth embodiment in that the main antenna 1 and the sub antenna 55 are shared by the angle diversity receiving antenna 57. As a result, since one angle diversity receiving antenna 57 is used as compared with the two antenna configurations of the ninth embodiment, the antenna configuration can be significantly downsized.

FIG. 11 is a block diagram of the interference compensation circuit of the eleventh embodiment of the present invention.

This embodiment differs from the fourth embodiment in that the quadrature amplitude modulator 110 is replaced with a transversal filter (an example of a 3-tap configuration) 112. With this configuration, even if the reception signal of the main antenna 1 or the reception signal of the auxiliary antenna 4 has frequency characteristics, it is possible to cancel the main signal and extract the interference signal.

The transversal filter 112, by the following operation,
The interference signal mixed in the main signal is extracted.

The main signal passing through the distributor 9'of the receiving system of the auxiliary antenna 4 is input to the quadrature amplitude modulator including a delay line with a plurality of taps, that is, the transversal filter 112 having a two-dimensional structure, and the main signal having the frequency characteristic Amplitude and phase are controlled. The transversal filter 112 further distributes one signal output from the distributor 9 ′ by the distributor 58 and supplies the one output to the bipolar variable attenuator 59 for controlling the in-phase component, and the other output. The outputs are supplied to the bipolar variable attenuator 60 that controls the quadrature component relatively, and the outputs of the bipolar variable attenuators 59 and 60 are input to the adder 61 and added.

The output of the distributor 58 further passes through a delay circuit 63 which delays the main signal by a clock period T (or an integral multiple thereof, or [1 / integer] multiple thereof) of the data, and is distributed by the distributor 58 equivalent to the above. To be distributed. One of the signals distributed by the distributor 58 is supplied to the bipolar variable attenuator 59 that controls the in-phase component. The other signal is supplied to the bipolar variable attenuator 60 that controls the quadrature component. The outputs of the bipolar variable attenuators 59 and 60 are added by the adder 61 and output.

In addition, the signal delayed by 2T by the two delay circuits 63 is similarly distributed by the distributor 58, and the bipolar variable attenuator is used.
The in-phase component is controlled by 59, the quadrature component is controlled by the bipolar variable attenuator 60, and the control outputs of the bipolar variable attenuators 59 and 60 are added by the adder 61 and output. Adder 61
The respective outputs of 1 are combined and output by the 90 ° combiner 62.

On the other hand, the received signal on the side of the main antenna 1 is distributed by the distributor 9 and input to the adder 8'through the delay circuit 63.
° Added with the output of combiner 62. The delay circuit 63 is for correcting the delay time of the signal to the same delay time T as the center tap of the transversal filter 112.

Since the two main signals input to the adder 8'have opposite phases and equal amplitudes and are converted to have the same frequency characteristic, only the interference signal is extracted by adding the two.

In this way, by using the transversal filter 112, the frequency characteristics of the main signal received from the main antenna 1 and the frequency characteristics of the main signal received from the auxiliary antenna 4 are added in opposite phase and with equal amplitude. , The main signal is greatly attenuated, and the interference component contained in it is largely exposed.

In order to control each weight amount of the transversal filter 112, the main signal remaining after adding the two signals, that is, the interference signal and the correlation detection between one main signal before the addition, The weighting circuits (bipolar variable attenuators 59 and 60) are feedback-controlled so that the amount is minimized, that is, the amount of the main signal after addition is minimized.

This operation will be specifically described.

The output of the adder 8'is distributed by the distributor 9 and input to the phase detector 21. This phase detector 21 is a main signal demodulator.
The signal from the distributor 9 is phase-detected using the reference carrier wave 10 reproduced by 100. This detection output has its harmonic component removed by the harmonic removal filter 23, and is binarized by the discriminator 25 using the clock signal 36 regenerated by the demodulator 100. As a result, a binary interference signal a is obtained.

The received signal of the auxiliary antenna 4 is distributed by the distributor 9 '. One output of the distributor 9'is supplied to the quadrature phase detector 108 via the delay circuit 63 for correcting the same delay time T as the center tap of the transversal filter 112, and further via the delay line τ _2. To be done. This signal is phase-detected by the quadrature phase detectors 20 and 21 using the reference carrier wave 10 reproduced by the demodulator 100.

This detection output has the harmonic components removed by the harmonic removal filters 22 and 23, and the clock signal 3 reproduced by the demodulator 100.
6 is used and binarized by the discrimination circuits 24 'and 25'.
As a result, a binary main signal in-phase component a _I and a main signal quadrature component a _Q are obtained.

The binarized interference signal a, the binarized main signal in-phase component signal a _I, and the main signal quadrature component a _Q are input to the transversal filter control circuit 113. The output of this transversal filter control circuit 113 is C _-1 (= X _-1 + jy _-1 ), C
_The bipolar variable attenuators 59 and 60 of the transversal filter 112 are controlled by ₀ (= X ₀ + jy ₀ ), C ₊₁ (= X ₊₁ + jy ₊₁ ).

FIG. 12 shows a circuit configuration of the transversal filter control circuit 113.

For example, the signal X _-1 which controls the bipolar variable attenuator 59 is generated as follows. The binarized interference signal a is input to one input end of the exclusive OR circuit 64, and the binarized main signal in-phase component a _I is input to the other input end of the delay circuit.
A signal delayed by T is input by 63. Exclusive-OR circuit 64 multiplies these inputs and integrator 65 integrates its output. This detects the correlation and the resulting output
X ₋₁ controls the bipolar variable attenuator 59 associated with the in-phase component of the transversal filter 112.

Similarly, the interference signal a and the binarized main signal orthogonal component a _Q
And a signal delayed by T by a delay circuit 63 are input to an exclusive OR circuit 64 for multiplication and then integrated by an integrator 65, and the output y ₋₁ of the two poles related to the orthogonal component of the transversal filter 112. The variable sex attenuator 60 is controlled.

Similarly, each bipolar variable attenuator 59, 60 is connected to the control signal C
Controlled by _-1 , C ₀ , and C ₊₁ respectively. As a result, 90
The output of the combiner 62 has the same frequency characteristics as the output of the main signal distributor 9 and has the same amplitude and opposite phase. Therefore, even if the received two input signals have different frequency characteristics, by combining the two, the main signal is almost completely erased, and the interference component remaining therein is greatly highlighted. This is output from the adder 8'as an interference signal.

In the present embodiment, it is necessary to adjust the relative timing with the delay lines τ ₁ and τ ₂ so that the compensation effect becomes maximum. In addition, it is necessary to match the relative delay times between the two main signals at the inputs of the adder 8 '.

Although three taps have been shown as an example of the number of taps of the transversal filter, if the number of taps is increased, the accuracy of extracting the interference signal can be further improved.

FIG. 13 shows a block diagram of an interference compensation circuit according to a twelfth embodiment of the present invention.

In this embodiment, the delay time of the delay circuit 63 of the transversal filter 112 is 1/2 of the clock cycle T of the data, and at the same time, the delay time of the delay circuit 63 'of the transversal filter control circuit 113'. Is T / 2, which is different from the eleventh embodiment. With such a configuration, it is possible to prevent deterioration of the compensation effect without matching the relative delay times between the two main signals in the adder 8 '.

In this embodiment, the T / 2 delay circuit 63 'is shown.
The same operation can be performed in the case where it is an integer fraction of

FIG. 14 shows a circuit configuration of a transversal filter control circuit 113 'using a T / 2 delay circuit 63'.

FIG. 15 is a block diagram of the interference compensation circuit of the thirteenth embodiment of the present invention.

In this embodiment, in order to cancel the interference signal mixed in the main signal, the amplitude and phase of the interference signal are not adjusted by the single-tap quadrature amplitude modulator 111, but a transformer consisting of a plurality of tapped delay lines is used. The use of the Versal filter 114 is different from the eleventh embodiment. With this configuration, even when the interference signal is a wideband signal and has frequency characteristics, the interference signal can be sufficiently removed and an interference compensation circuit can be obtained.

In FIG. 15, the interference signal output from the adder 8'is supplied to the adder 8 through the transversal filter 114. The transversal filter 114 and the transversal filter control circuit 115 have the same configurations as the transversal filter 112 and the transversal filter control circuit 113 described above.

FIG. 16 shows a block diagram of an interference compensation circuit according to the 14th embodiment of the present invention, and FIG. 17 shows a circuit configuration of a transversal filter control circuit 115 '.

In this embodiment, instead of the transversal filters 112, 114 and the transversal filter control circuits 113, 115 for controlling the transversal filters 112, 114 in the thirteenth embodiment, the transversal filter 112 'and the transversal filter shown in the twelfth embodiment are used. A difference from the thirteenth embodiment is that a filter control circuit 113 '(the transversal filter 114' has the same configuration as the transversal filter 113 ') is used and further a transversal filter control circuit 115' is used.

Also, instead of the transversal filter 112 of the thirteenth embodiment, the transversal filter 11 of the fourteenth embodiment is used.
It is also possible to use 2'and correspondingly use the transversal filter control circuit 113 '. Alternatively, instead of the transversal filter 114 of the thirteenth embodiment, using the transversal filter 114 'of the fourteenth embodiment,
In response to this, the transversal filter control circuit 11
5'can also be used.

FIG. 18 is a block diagram of the interference compensation circuit of the fifteenth embodiment of the present invention.

This embodiment is different from the first embodiment in that the amplitude and the phase of the interference signal component included in the reception signal of the auxiliary antenna 4 are adjusted to cancel the interference signal included in the reception signal of the main antenna 1.

This interference compensation circuit includes a main antenna 1 and its output circuit as a first reception circuit for receiving a signal in which an interference signal is mixed with a main signal, and a signal including an interference signal is provided in a system separate from the first reception circuit. An auxiliary antenna 4 and an output circuit thereof as a second receiving circuit for receiving, and a variable amplitude circuit 41 and a variable phase circuit 42 as first adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, The adder 40 is provided as a first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit.
The control circuit 106 is provided as a first control means for controlling the variable amplitude circuit 41 and the variable phase circuit 42 so that the interference signal included in the output of 40 is sufficiently small.

Here, the feature of this embodiment is that the output circuit of the auxiliary antenna 4 has a variable amplitude circuit as a second adjusting means for adjusting the amplitude and phase of the signal received by the auxiliary antenna 4.
37 and a variable phase circuit 38, an adder 39 is provided as a second subtracting means for subtracting the output signal of the first receiving circuit from the output of the second adjusting means, and the interference signal included in the output of the adder 39 This is because the control circuit 105 is provided as second control means for controlling the variable amplitude circuit 37 and the variable phase circuit 38 so that the level becomes sufficiently higher than the main signal.

Hereinafter, a method of canceling the interference signal mixed in the main signal will be described.

In order to cancel the interference signal from the output of the combiner 40, the auxiliary antenna 4 is used for the interference signal in the reception signal of the main antenna 1.
The variable amplitude circuit 41 and the variable phase circuit 42 are controlled so that the interference signal in the received signal has equal amplitude and opposite phase.

Therefore, the correlation between the interference signal output from the adder 39 and the interference component included in the output of the adder 40 is controlled by the control circuit 106.
The variable amplitude circuit 41 and the variable phase circuit 42 are controlled so as to eliminate this interference component. The main signal power vs. the interference signal power (D / U) at the output of the adder 40
D / U of the ratio of the main antenna 1 or auxiliary antenna 4 input
In order to increase the ratio, the variable amplitude circuit 41 can be inserted not only on the auxiliary antenna 4 side but also on the main antenna 1 side or both the main antenna 1 side and the auxiliary antenna 4 side.

As described above, the interference signal mixed in the main signal can be automatically compensated.

Specific examples of this example will be shown below.

FIG. 19 is a block diagram of the interference compensation circuit of the sixteenth embodiment of the present invention.

The signals received from the main antenna 1 and the auxiliary antenna 4 pass through the band pass filter 2 for improving the signal-to-noise ratio, and then the frequency converter 3 uses the local oscillation signal from the common local oscillator 5. Each is converted to an intermediate frequency.

The signals converted into the intermediate frequency band are respectively distributed by the distributors 9,
Input to 9 '. One output of the distributor 9 is input to the adder 8. One output of the distributor 9'is input to the adder 8'through the distributor 66, the variable amplitude circuit 7'and the variable phase circuit 6 '. The variable amplitude circuit 7'and the variable phase circuit 6'are feedback-controlled so that one main signal output from the distributor 9'has the same amplitude and opposite phase with respect to the other main signal output from the distributor 9. As a result, the adder 8 '
At the output of, the main signal output is greatly attenuated, and an interference signal mixed in the main signal is obtained.

Next, for the interference signal in the main antenna 1, the auxiliary antenna 4
The control in which the interference signal therein has the same amplitude and the opposite phase, that is, the control of the variable phase circuit 6 and the variable amplitude circuit 7 will be described.

The main signal combined by the adder 8 is input to the demodulator 100. The demodulator 100 uses the reference carrier 10 regenerated from the main signal, quadrature-detects the main signal by the quadrature phase detectors 12 and 13, and outputs the output signal of each of the harmonic elimination filters.
By passing through 14 and 15, in-phase and quadrature baseband signals are obtained. The obtained baseband signals are input to error signal generation circuits 101 and 102, respectively. The error signal generation circuits 101 and 102 are composed of discrimination circuits 16 and 18, respectively, and subtractors 17 and 19 that take the difference between their input and output, and these subtractors 17 and 19 output error signals.

On the other hand, the interference signal output from the adder 8'is phase-detected by the phase detector 21 using the reference carrier 10, and after the harmonic component is removed by the harmonic removal filter 23, the identification circuit 25 outputs the binary signal. Be converted. As a result, a binary interference signal is obtained. The identification circuit 25 is a demodulator 100 for the main signal.
The binarization operation is performed by using the clock signal 36 reproduced in (1).

Next, correlation detection is performed between the in-phase and quadrature component error signals obtained by the demodulator 100 and the binarized interference signal. That is, the in-phase component error signal and the interference signal are digitally multiplied by the exclusive OR circuit 27, the output thereof is integrated by the integrator 30, and the variable amplitude circuit 7 is controlled by the output. On the other hand, the quadrature component error signal and the interference signal are digitally multiplied by the exclusive OR circuit 31, the output thereof is integrated by the integrator 35, and the variable phase circuit 6 is controlled by the output signal.

In this way, interference compensation can be automatically performed.

FIG. 20 is a block diagram of the interference compensation circuit of the seventeenth embodiment of the present invention.

In this embodiment, when controlling the amplitude and phase of the reception signal of the auxiliary antenna 4, the variable amplitude circuit and the variable phase circuit are used in the sixteenth embodiment, respectively, but a quadrature amplitude modulator is provided in that portion. The use is different from the sixteenth embodiment.

That is, in the sixteenth embodiment, the variable amplitude circuits 7, 7'and the variable phase circuits 6, 6'are controlled by the correlation outputs from the integrators 30, 35, respectively. On the other hand, in this embodiment, the quadrature amplitude modulators 110 and 111 are used to perform the same operation.

The quadrature amplitude modulator 110 includes a distributor 43 that distributes an input signal.
And a 90 ° phase shifter 11 that shifts one of the outputs of the distributor 43 by 90 °, and π / 2 that adjusts the amplitude of the output of the 90 ° phase shifter 11.
Bi-phase variable attenuator 45, zero-phase bi-polar variable attenuator 46 for adjusting the amplitude of the other output of distributor 43, and adder 44 for adding the outputs of the bi-polar variable attenuators 45, 46. It consists of and.

Similarly, the quadrature amplitude modulator 111 has a distributor 43 and a 90 ° phase shifter 1
1, a bipolar variable attenuator 45, 46, and an adder 44.

The zero-phase bipolar variable attenuator 46 in the quadrature amplitude modulator 110 is
It is controlled by the output of the integrator 30 of the correlation detection circuit 109. The π / 2-phase bipolar variable attenuator 45 is controlled by the output of the integrator 35.

Zero-phase bipolar variable attenuator 46 in the other quadrature amplitude modulator 111
Similarly, the π / 2-phase bipolar variable attenuator 45 is similarly controlled by the outputs of the integrator 30 and the integrator 35 in the correlation detection circuit 107, respectively.

FIG. 21 is a block diagram of the interference compensation circuit of the eighteenth embodiment of the present invention.

This embodiment is a quadrature amplitude modulator for controlling the amplitude and phase of the reception signal of the auxiliary antenna 4 in the seventeenth embodiment.
Unlike the seventeenth embodiment, the transversal filters 112 and 114 are used in that portion while the 110 and 111 are used. With this configuration, even when the frequency characteristics occur in the received signal of the main antenna 1 or the auxiliary antenna 4, it is possible to eliminate the interference signal mixed in the received signal. The configurations of the transversal filters 112 and 114 and the configurations of the transversal filter control circuits 113 and 115 are equivalent to those shown in FIG. 11, FIG. 12 or FIG.

FIG. 22 is a block diagram of the interference compensation circuit of the nineteenth embodiment of the present invention.

In this embodiment, the transversal filters 112 and 114 in the eighteenth embodiment and the delay circuits 63 of the control circuits 113 and 115 thereof are replaced with the transversal filters 112 ′ and 114 ′ and the same used in the fourteenth embodiment. Control circuit 113 ', 115'
Is different from the eighteenth embodiment.

FIG. 23 is a block diagram of the interference compensation circuit of the twentieth embodiment of the present invention.

This embodiment circuit includes a first quadrature phase detector 12, 13 as a part of the first receiving circuit, and a first quadrature component for digitizing the in-phase component and the quadrature component output from the quadrature phase detector 12, 13, respectively. And a second analog-to-digital converter 4
And a second receiving circuit by adjusting the phase of the local oscillation signal used in the first receiving circuit and supplying the local oscillation signal to the second receiving circuit as part of the first adjusting means. And a phase shifter 56 'for adjusting the phase of the output signal of the first quadrature detector 12, 13 as a part of the first subtraction means. A second quadrature phase detector 20, 21 and an in-phase component and a quadrature component output from the quadrature phase detectors 20 and 21 are further provided as the first reception circuit, the adder 8 synthesizing the reception signals of the two reception circuits. The third and fourth analog
The digital converters 51, 51 'are provided, and as the second receiving circuit, third quadrature phase detectors 20', 21 'and in-phase components and quadrature components output from the quadrature phase detectors 20', 21 'are further provided. Fifth and sixth analog / digital converters 52, 53 for digitizing, respectively, and as the second adjusting means, first through fourth adjusting the phases and amplitudes of the outputs of the analog / digital converters 52, 53. Variable coupler 67 ~
70, and as first subtraction means, first to fourth full adders 71 to 74 for adding the outputs of the variable couplers 67 to 70 to the outputs of the analog-digital converters 51 and 51 '. As control means, analog-digital converters 51, 51 ', 5
A variable coupler control circuit 117 for controlling the variable couplers 67 to 70 by the outputs of 2, 53 is provided, and further as the first adjusting means,
The fifth to eighth variable couplers 75 to 78 for adjusting the phases and amplitudes of the outputs of the analog / digital converters 51 and 51 'are provided, and the outputs of the analog / digital converters 49 and 50 are further provided as the first subtraction means. To the fifth to eighth full adders 79 to 82 for adding the outputs of the variable couplers 75 to 78, and as the first control means, analog-digital converters 49, 50, 51,
A variable coupler control circuit 118 for controlling the variable couplers 75 to 78 by the output of 51 'is provided.

The main signal received by the main antenna 1 for receiving the main signal and the auxiliary antenna 4 is passed through the band pass filter 2 and then converted into an intermediate frequency band by the frequency converter 3 using the local oscillation signal from the local oscillator 5. Frequency converted. The phase shifter 56 'inserted between the local oscillator 5 and the frequency converter 3 is for varying the combined phase of the main signals received by the main antenna 1 and the auxiliary antenna 4, and generally, after combination. Is controlled so that the received power of the signal is maximized.

The received signals of the main antenna 1 and the auxiliary antenna 4 are combined by the adder 8. This composite signal is a quadrature detector
The reference carrier wave 10 inputted to 12 and 13 and reproduced from the main signal is decomposed into in-phase and quadrature components.

The received signal of the main antenna 1 is the quadrature phase detectors 20 and 21.
And is decomposed into an in-phase component and a quadrature component by the reference carrier wave 10. On the other hand, the reception signal of the auxiliary antenna 4 is input to the quadrature phase detectors 20 'and 21' and decomposed into the in-phase and quadrature components by the reference carrier wave 10.

The in-phase and quadrature components thus obtained are respectively fed from the quadrature phase detectors 12, 13, 20, 21, 20 ', 21' to the harmonic elimination filters 14, 15, 22, 23, 22 ', 23'. Via analog-digital converter 4 with sufficient quantization accuracy
It is supplied to 9, 50, 51, 51 ', 52, 53 and digitized. Analog-digital converter 49, 50, 51, 51 ',
As the sampling signals of 52 and 53, a clock signal obtained by multiplying a clock signal reproduced from the main signal by a multiplier 36 'is commonly used.

Analog-digital converter 49, 50, 51, 51 ', 52, 53
The circuit configuration for removing the main signal component from the in-phase component and the quadrature component of the main signal output from to obtain the interference signal will be described.

The output signal of the analog / digital converter 52 is input to the variable couplers 67 and 69. The outputs of these variable couplers 67 and 69 and the outputs of the analog / digital converters 51 and 51 'are added by full adders 71 and 73, respectively.

Similarly, the output signal of the analog-digital converter 53 is
Inputs to variable combiners 68 and 70, and these outputs and full adder
The outputs of 71 and 73 are added by full adders 72 and 74. From the outputs of these full adders 72 and 74, the main signal components of the in-phase and quadrature components are eliminated, and the signals a _I and a _Q having only the interference signal components can be obtained. However, this interference signal
With respect to a _I and a _Q , the main signal component is dominant at the time when the interference compensation control is started, and the interference component increases as the control enters the steady state.

Based on these interference signals a _I and a _Q , the interference component mixed in the main signal is eliminated.

Therefore, the output signal of the full adder 74, that is, the interference signal a _Q of the quadrature component is input to the variable combiners 75 and 77, and the outputs of the variable combiners 75 and 77 and the analog-digital converters 50 and 49.
And the outputs of the above are added by full adders 79 and 80.

On the other hand, the output signal of the full adder 72, that is, the interference signal a _I of the in-phase component is input to the variable couplers 76 and 78. The outputs of the variable combiners 76 and 78 and the outputs of the full adders 79 and 80 are added by the full adders 80 and 82. As a result, a compensation signal having the opposite phase and the same amplitude as the interference component mixed in the main signal system is created, and the interference component can be eliminated by adding the compensation signal to the interference component mixed in the main signal system. it can.

Next, variable couplers 75, 76, 77, 78, 67, 68, 69 and 70.
The control method will be specifically described.

In order to eliminate the main signal and obtain only the interference signal, it is necessary to add the main signal received by the main antenna 1 and the main signal received by the auxiliary antenna 4 in antiphase and equal amplitude.

Therefore, the baseband signals of the in-phase and quadrature components obtained from each of the reception signals described above are converted into variable combiners 67, 68, 69.
And 70 to add. In this case, the in-phase and quadrature component outputs after addition, that is, the outputs a _{I of} the full adders 72 and 74,
a _Q, the main signal component must be controlled so as to minimize.

To this end, correlation detection is performed between the main signal after the addition and the output signal of the auxiliary antenna 4 or the main antenna 1 before the addition, and the variable coupler control circuit 117 is used to minimize the correlation amount. , Feedback control of the variable couplers 67, 68, 69 and 70, respectively. In this example,
Correlation detection is performed using the polarity signals a _Q and a _{I of the} interference signal and the polarity signals a _Qr and a _{Ir of} the main signal received by the sub antenna 4.

The interference components mixed in the main signal are eliminated based on the interference signals of the in-phase and quadrature components obtained in this way. To this end, variable couplers 75, 76, 77 and 78 are controlled.

For this purpose, the error signals e _Q and e _I obtained from the outputs of the full adders 80 and 82, that is, the main signal output after interference compensation, and the outputs of the full adders 72 and 74, that is, the in-phase and quadrature of the interference signals are used. The component and the variable coupler are input to the variable coupler control circuit 118, the correlation between them is detected, and feedback control is performed so that the amount is minimized.

For the error signals e _I and e _Q , for example, in the case of the 16QAM system, as shown in the above table, the error signal can be obtained from the third and subsequent bits from the top. Here, it is assumed that correlation detection is performed using only the polarity signals a _Q and a _I of the interference signal.

The delay adjustment line τ ₁ shown in FIG. 23 is the quadrature detector 1
For time adjustment so that each signal passing through 2 and 13 and each signal passing through quadrature detectors 20 and 21 are added at the same time in full adders 79, 80, 81 and 82 belongs to. Similarly, in the delay adjustment line τ ₂ , the signals passing through the quadrature phase detectors 20 and 21 and the quadrature phase detectors 20 ′ and 21 ′ are the same in the full adders 71, 72, 73 and 74 at the same time. It is for adjusting the time so as to be added.

FIG. 24 is a circuit configuration diagram showing an example of a variable coupler. Here, an example is shown in which the delay circuit has a 3-tap configuration.

The variable coupler is composed of a delay circuit with a tap 63 ′, a bipolar variable attenuator 83 connected to each of these taps, and an adder 84 for adding the outputs of the bipolar variable attenuator 83. The amplitude of the signal input to 63 'is adjusted and output from the adder 84.

25 and 26 are circuit configuration diagrams showing an example of the variable coupler control circuits 117 and 118.

Each error signal e _Q , e _{I of the} main signal and each polarity signal a _Q , a _{I of the} interference signal, or each polarity signal a _Qr , a _Ir , a _Q , a of the main signal received by the auxiliary antenna 4 _I is timed by the delay circuit 63 or the T / 2 delay circuit 63 ', the correlation is taken by the exclusive OR circuit 64, the correlation output is input to the integrator 65 and integrated, and the output is used to control the variable coupler. To do.

In this way, by using a plurality of weighting circuits in the variable coupler, a large compensation effect can be obtained even when the main signal and the interference signal have frequency characteristics.

〔The invention's effect〕

As described above, the interference compensation circuit of the present invention receives signals in which an interference signal is mixed with a main signal for each of a plurality of propagation paths. An interference signal with high purity is obtained by synthesizing these signals with respect to the main signal with mutually opposite phases and equal amplitudes. Therefore, it is not necessary to directly receive the signal that causes the interference signal, and even if the directions of the main signal source and the interference signal source are the same, the signal that causes the interference can be accurately obtained, and There is an effect that the interference signal mixed in the signal can be removed with high accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram of an interference compensation circuit according to the first embodiment of the present invention. FIG. 2 is a block diagram of the interference compensation circuit according to the second embodiment of the present invention. FIG. 3 is a block diagram of the interference compensation circuit according to the third embodiment of the present invention. FIG. 4 is a block diagram of the interference compensation circuit according to the fourth embodiment of the present invention. FIG. 5 is a block diagram of the interference compensation circuit of the fifth embodiment of the present invention. FIG. 6 is a block diagram of an interference compensation circuit according to a sixth embodiment of the present invention. FIG. 7 is a block diagram of the interference compensation circuit of the seventh embodiment of the present invention. FIG. 8 is a block diagram of an interference compensation circuit according to an eighth embodiment of the present invention. FIG. 9 is a block diagram of the interference compensation circuit of the ninth embodiment of the present invention. FIG. 10 is a block diagram of the interference compensation circuit of the tenth embodiment of the present invention. FIG. 11 is a block diagram of the interference compensation circuit of the eleventh embodiment of the present invention. FIG. 12 is a diagram showing a circuit configuration of a transversal filter control circuit. FIG. 13 is a block diagram of the interference compensation circuit of the twelfth embodiment of the present invention. FIG. 14 is a diagram showing a circuit configuration of a transversal filter control circuit. FIG. 15 is a block diagram of the interference compensation circuit of the thirteenth embodiment of the present invention. FIG. 16 is a block diagram of the interference compensation circuit of the fourteenth embodiment of the present invention. FIG. 17 is a diagram showing a circuit configuration of a transversal filter control circuit. FIG. 18 is a block diagram of the interference compensation circuit of the fifteenth embodiment of the present invention. FIG. 19 is a block diagram of the interference compensation circuit of the sixteenth embodiment of the present invention. FIG. 20 is a block diagram of the interference compensation circuit of the seventeenth embodiment of the present invention. FIG. 21 is a block diagram of the interference compensation circuit of the eighteenth embodiment of the present invention. FIG. 22 is a block diagram of the interference compensation circuit of the nineteenth embodiment of the present invention. FIG. 23 is a block diagram of the interference compensation circuit of the 20th embodiment of the present invention. FIG. 24 is a diagram showing a circuit configuration of a variable coupler. FIG. 25 is a diagram showing a circuit configuration of a variable coupler control circuit. FIG. 26 is a diagram showing a circuit configuration of a variable coupler control circuit. FIG. 27 is a block diagram of a conventional interference compensation circuit. 1 ... Main antenna, 1 '... Wired transmission line 1', 2 ... Band pass filter, 3 ... Frequency converter, 4 ... Auxiliary antenna, 5 ...
Local oscillator, 6, 6 ', 38, 42 ... Variable phase circuit, 7,
7 ', 37, 41 ... Variable amplitude circuit, 8, 8'39, 40, 44, 6
1, 84 ... Adder, 9, 9 ', 43, 58 ... Distributor, 11 ... 90 °
Phase shifter, 12, 13, 20, 20 ', 21, 21', 108 ... Quadrature phase detector, 14, 15, 22, 23, 22 ', 23' ... Harmonic elimination filter, 16, 18, 24, 25 ... Identification circuit, 17, 19 ... Subtractor, 2
6, 27, 64, 31, 32, 64 ... Exclusive OR circuit, 28, 29, 3
3, 34 ... Resistance, 30, 35, 65 ... Integrator, 36 '... Multiplier, 4
5, 46, 59, 60, 83 ... Bipolar variable attenuator, 47, 48 ... Multiplier, 49-53 ... Analog / digital converter, 55 ... Sub antenna, 56, 56 '... Phase shifter, 57 ... Angle Diversity receiving antenna, 61, 62 ... 90 ° combiner, 63, 63 '... Delay circuit, 67-70, 75-78, ... Variable combiner, 71-82 ... Full adder, 100 ... Demodulator, 101, 102 ... Error signal generation circuit, 105,
106 ... Control circuit, 107, 109 ... Correlation detection circuit, 110, 111 ...
Quadrature amplitude modulator, 112 ... Transversal filter, 11
3, 113 ', 115, 115' ... Transversal filter control circuit, 117, 118 ... Variable coupler control circuit.

Claims (3)

[Claims] 1. A first receiving circuit for receiving a signal in which an interference signal is mixed with a main signal, and a second receiving circuit provided in a system separate from the first receiving circuit for receiving a signal including the interference signal, First adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit, and the first subtracting means An interference compensation circuit comprising: a first control means for controlling the first adjusting means so that an interference signal included in the output of the means is sufficiently small, wherein the second receiving circuit receives the first receiving circuit. The second receiving circuit is configured to receive a signal that has passed through a propagation path different from the signal, and second adjusting means for adjusting the amplitude and phase of the signal received by the second receiving circuit, and the second adjusting circuit. From the output of the means Second subtracting means for subtracting the output signal of the circuit and outputting to the first adjusting means, and the second adjusting means for setting the interference signal included in the output of the second subtracting means to a level sufficiently larger than the main signal. An interference compensation circuit comprising: a second control means for controlling. 2. A first receiving circuit for receiving a signal in which an interference signal is mixed with a main signal, and a second receiving circuit provided in a system separate from the first receiving circuit for receiving a signal including the interference signal. First adjusting means for adjusting the amplitude and phase of the output signal of the second receiving circuit, first subtracting means for subtracting the output of the first adjusting means from the output signal of the first receiving circuit, and the first subtracting means An interference compensation circuit comprising: a first control means for controlling the first adjusting means so that an interference signal included in the output of the means is sufficiently small, wherein the second receiving circuit receives the first receiving circuit. A signal that has passed through a propagation path different from that of the signal is received and output to the first adjusting means. The second receiving circuit adjusts the amplitude and phase of the signal received by the second receiving circuit. Two adjustment means and this second tone Second subtracting means for subtracting the output signal of the first receiving circuit from the output of the means and outputting it to the first controlling means, and the interference signal included in the output of the second subtracting means becomes a level sufficiently higher than the main signal. And a second control means for controlling the second adjusting means as described above. 3. A first receiving circuit for receiving a signal in which an interference signal is mixed with a main signal, and a second receiving circuit provided in a system different from the first receiving circuit for receiving a signal containing the interference signal. A synthesizing circuit (8) for synthesizing the main signals received by the first receiving circuit and the second receiving circuit, first quadrature detecting means for quadrature detecting the output of the synthesizing circuit and converting it into a digital signal, Second quadrature detecting means for quadrature detecting the output of the first receiving circuit and converting it into a digital signal; third quadrature detecting means for quadrature detecting the output of the second receiving circuit and converting it into a digital signal; First to fourth variable couplers (67, 68, 69, 70) for adjusting the amplitude and phase of the output of the third quadrature detection means.
A first to a fourth full adder (71, 72, 73, 74) for adding the outputs of the first to fourth variable couplers and the output of the second quadrature detection means; A variable coupler control circuit (117) for controlling the first to fourth variable couplers so as to minimize the main signal component of the output of the first to fourth adders; A fifth to an eighth variable coupler (75, 76, 77, which adjusts the amplitude and phase of the output of the adder,
78), a fifth to an eighth full adder (79, 80, 81, 82) for adding the output of the first quadrature detection means and the outputs of the fifth to eighth variable couplers, A variable coupler control circuit (118) for controlling the fifth to eighth variable couplers so as to cancel the interference component in the main signal output from the fifth to eighth adders. Characteristic interference compensation circuit.