JPH0698150A - Image processor - Google Patents

Abstract

PURPOSE:To prevent images from being degraded and to efficiently register pattern images by writing image data and pattern data in one memory, synthesizing the image data and pattern data read from this memory and registering the synthesized data as pattern data. CONSTITUTION:The E terminal output of a pattern area extraction part 308 sets an area for synthesizing the image data and pattern data. Since the E terminal output of the pattern extraction part 308 is passed through registers 315 and 316, the output is inputted to a pattern synthesizing part 319 while being delayed for two picture element clocks. According to a signal inputted from the register 361, this synthesizing part 319 synthesizes the pattern data inputted from a register 313. In this case, the image data and pattern data are synthesized by 0Ring the output of prescribed bits of image data and the pattern data. Then, the synthesized data are registered as pattern data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus applied to a digital copying machine, a printer or the like, and more particularly to an image processing apparatus for adding a pattern image to a designated area of an image.

[0002]

2. Description of the Related Art For example, an image processing apparatus applied to a digital copying machine performs shading correction, MTF correction, and so on on image data of an original image read by a scanner.
Various image processes such as a scaling process are executed. Here, the image processing apparatus generally uses a method of temporarily writing the input image data in a memory, reading the image data from the memory, and performing image processing depending on the relationship between the transfer speed and the processing speed of the input image data. Target.

Among the various types of image processing described above, there is one that adds a pattern (pattern image) of a certain shape to the background of the image and synthesizes it (hereinafter referred to as pattern synthesis processing). This pattern synthesizing process is intended to emphasize a specific part of the image and cultivate a unique aesthetic appearance. The pattern image to be added to the background of the image by the pattern synthesizing process is generally stored in a memory (ROM or the like) in advance. However, in the method of storing the pattern image in the memory in advance, when it is desired to add many kinds of pattern images to the background of the image, many pattern images must be stored in the memory in advance.

As an example of adding various types of pattern images to the background of an image, for example, Japanese Patent Laid-Open No. 17727/1989
There is an "image processing apparatus" disclosed in Japanese Patent No. 4 publication. In the "image processing device" of the publication, a memory in which image data related to a pattern image (hereinafter referred to as pattern data) is stored is readable and writable, and by writing the pattern data in this memory, desired pattern data can be imaged. To be added to. Further, since a counter capable of switching the cycle is used to read the pattern data from the memory, by writing the pattern data of the pattern images of different sizes in the memory, a plurality of pattern images corresponding to the size of each pattern image can be created. It becomes possible to execute the pattern synthesis processing.

[0005]

However, according to the "image processing apparatus" disclosed in Japanese Patent Laid-Open No. 1-177274, pattern data is written in addition to the memory in which input image data is written. Since a dedicated memory is required, the cost ratio of the memory occupied by the device increases, which raises the problem of increasing the cost of the entire device.

Further, the pattern data inputted from the outside of the apparatus is written in the memory so as to have versatility in the pattern synthesizing process. For example, an image in a partial area of an original image read by a scanner or the like as pattern data. When data is input, the seams of each pattern image added to the background of the image become distorted,
There is a problem that the appearance of the image is deteriorated and the image is deteriorated.

That is, when a part of the original image is read as a pattern image by a scanner and used, the pattern image is accurately created on the original in accordance with this area, and the original is placed so that the scanner can read it accurately. It is necessary to place it. If these things are not performed accurately, the seams of the pattern or the like in each pattern image will be distorted, and depending on the pattern of the pattern image, the seams will be conspicuous, the appearance of the image will be degraded, and the original image will be difficult to identify. It causes image deterioration.
In addition, when the pattern image is not properly stored (registered) in the memory, the pattern image must be registered again, which causes a problem of poor workability.

The present invention has been made in view of the above, and it is a first object of the present invention to suppress the cost of a device by storing different data together in one memory and reducing the number of required memories. To aim.

In addition, according to a second aspect of the present invention, it is possible to easily register a desired pattern image in a memory in an appropriate state, thereby avoiding image deterioration and improving work efficiency in registering the pattern image. The purpose of.

[0010]

In order to achieve the above object, the present invention comprises image reading means for reading image data,
Image recording means for recording the image data read by the image reading means, and storage means for storing the image data and pattern data read by the image reading means,
An image including identification and separation means for identifying and separating image data and pattern data output from the storage means, and interpolation means for interpolating the image data read out from the storage means when generating the pattern data A processing device is provided.

Image reading means for reading the image data, image recording means for recording the image data read by the image reading means, storage means for registering the image data read by the image reading means as pattern data, It is an object of the present invention to provide an image processing apparatus comprising display means for displaying the pattern data when registering the pattern data in the storage means, and modifying means for modifying the pattern data displayed on the display means.

Image reading means for reading the image data, image recording means for recording the image data read by the image reading means, storage means for registering the image data read by the image reading means as pattern data, When registering the pattern data in the storage means, there are provided a number-of-times designating means for designating the number of times of repeating the pattern data and an image editing means for enlarging or reducing the pattern data based on the number of times designated by the number of times designating means. An image processing apparatus provided is provided.

[0013]

The image processing apparatus according to the present invention writes the image data and the pattern data in one memory and synthesizes the image data and the pattern data read from the memory. Further, when the read image data is registered as pattern data, the pattern data is displayed and correction is performed based on the display. Further, when the read image data is registered as pattern data, the number of times the pattern data is repeated is designated, and the pattern data is enlarged or reduced based on the designated number of times.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an image forming apparatus to which the image processing apparatus according to the present embodiment is applied. For an image reading unit 101 that reads a document image and image data output from the image reading unit 101. And an image processing unit 1 for executing various image processing by
An image recording unit 103 using an electrophotographic method for driving a laser light source using the image data output from 02 to output an image on a recording sheet; and an operation panel 104 provided with various keys including a display unit 104a. , And a control unit 105 that controls the entire apparatus.

The operation of the above configuration will be described. The image reading unit 101 uses a scanner, a CCD line sensor, and the like to decompose an original image placed on a contact glass into pixels and reads the image, and performs an amplification process on the image data output from the CCD line sensor. Processing such as D conversion is executed. As a result, the image data is output to the image processing unit 102 as image data quantized into 8 bits (that is, 256 gradations). The image processing unit 102
Various types of image processing such as scaling processing, processing / editing processing, and γ correction are performed on the input image data for each unit, and the image data is output to the image recording unit 103. The image recording unit 103
The laser light source is driven using the image data input from the image processing unit 102 to write an image (electrostatic latent image) on a photoconductor (not shown), and the electrostatic latent image on the photoconductor is developed. Processing, transfer processing, fixing processing, etc. are executed to record the reproduced image on the recording paper.

FIG. 2 is a block diagram showing a schematic configuration of the image processing unit 102 shown in FIG. 1, in which a scaling unit 201 for performing scaling processing, a shading, a hollowing (contour), a shadowing, and a mirror are provided. , Italics, rotation, processing and editing unit 202 that performs processing and editing processing such as pattern composition, and γ correction unit 203 that performs γ correction,
Filter unit 20 for smoothing an image or enhancing edges
4, a dither processing unit 205 that performs dither processing, and an area control unit 206 that controls pattern synthesis.

Next, the pattern composition processing according to this embodiment will be described. The pattern synthesizing process is to add a pattern image to a designated area of an image to synthesize an image, and is executed by the working / editing unit 202 shown in FIG. FIG. 3 is a block diagram showing a schematic configuration of a pattern synthesis processing unit 300 that performs pattern synthesis in the processing / editing unit 202 shown in FIG. 2, and a write address counter that counts a pixel clock (CLK) used to transfer image data. 301, a read address counter 302, a counter 303 that counts a line synchronization signal that is a reading cycle of a document image in the sub-scanning direction, two toggle buffers 304 and 305, and an address for reading a pattern image from the toggle buffer 305. Generated pattern address generator 306 and read address counter 30
2. A selector 307 that selects one of the pattern address generation units 306, a pattern region extraction unit 308 that selects a signal to be output to the selector 307 in accordance with a 3-bit region signal output from the toggle buffer 304, and temporarily holds data Selectors 309 to 316, toggle buffer 305, and selector 3 for selecting the output of register 311
17, a pattern expanding unit 318 that serially expands the parallel pattern image data output from the toggle buffer 317, and a pattern combining unit 319 that combines the image data and the pattern image data.

The operation of the above configuration will be described. First, the toggle buffers 304 and 305 will be described. The toggle buffers 304 and 305 have the same configuration, and the toggle buffer 305 will be described as an example.
As shown in FIG. 4, the toggle buffer 305 stores registers 401 and 402 for holding the input image data, buffers 403 and 404 for holding the write address data input from the W terminal, and read address data input from the R terminal. Buffers 405 and 406 to hold and memory 4
07, 408, registers 409, 410 for holding the data read from the memories 407, 408, and a selector 411 for selecting one of the data held in the registers 409, 410.

As shown in FIG. 4, the toggle buffer 305
Consists of two systems, namely a first system having a memory 407 and a second system having a memory 408. The configurations of these two systems are the same, and their operations are alternately switched and used. Specifically, when the image data is written in the memory 407 of the first system, the image data is read from the memory 408 of the second system, and conversely, when the image data is written in the memory 408 of the second system,
It is used to read image data from the memory 407 of the first system.

The writing / reading of image data in the memories 407 and 408 is switched for each line. The image data read from the memory 407 is output to the outside via the registers 409 and 410 and the selector 411. Therefore, when the write address data has the same value as the read address data, the sub-scanning is performed from the input image data. 1 line in the scanning direction and 1 pixel in the main scanning direction.

The memories 407 and 408 are 8K × 8 bits.
It is a line memory having a storage capacity of. A3 size recording paper has a pixel density of 16 dots / mm and has 4752 pixels in the main scanning direction (6720 lines in the sub scanning direction).
If the image data per pixel is 8 bits, the image data per line is 5 Kbyte (1b
yte = 8 bits). If the image data per pixel is 1 bit, 64 × 6 as shown in FIG.
The image data of 4 pixels becomes 512 bytes, and the image data of 128 × 128 pixels as shown in FIG. 5B becomes 2 Kbytes.

Therefore, the memory 407, 4 of 8 Kbytes
As shown in FIG. 6, one line of A3 size image data (5 Kbytes) and two 1
64 × 64 pixel image data (2 × 512 by)
te) and 128 × 128 pixel image data (2 Kb
yte) and can be written. Therefore, if the pattern image is 64 × 64 pixels and 128 × 128 pixels,
Three pattern images can be written in the memories 407 and 408.

The area signal output from the toggle buffer 304 is input to the register 309 and the pattern area extraction unit 308. The pattern area extraction unit 308 extracts the pattern address generation unit 30 from the PS terminal according to the input area signal and the count value of the read address counter 302.
A predetermined signal is output to 6, and a 1-bit signal is output from the S terminal to the register 314 and the selector 307, and the E terminal to the register 315.

The pattern address generation unit 306, according to the signal input from the pattern area extraction unit 308, reads the read address counter 302 and the sub-scanning address counter 303.
The address of the pattern image data stored in the memories 407 and 408 in the toggle buffer 305 is output to the selector 307 based on the count value of. Selector 307
Selects the output of the read address counter 302 when the S terminal output of the pattern area extraction unit 308 is “L”,
On the contrary, when the S terminal output is "H", the output of the pattern address generator 306 is selected. Therefore, the pattern data is output from the toggle buffer 305 with a delay of one pixel clock after the S terminal output of the pattern area extraction unit 308 becomes “H”.

The selector 317 is a toggle buffer 305.
Output of the register 311 and the output of the register 311 are selected. Similarly to the selector 307, the selector 317 also selects the A terminal input when the S terminal input is “L”, that is, the output of the toggle buffer 305, and the B terminal when the S terminal input is “H”.
The terminal input, that is, the output of the register 311 is selected. Therefore, the output of the register 314 is the pattern area extraction unit 30.
Since the S terminal output of 8 is delayed by one pixel clock,
The pattern data output from the toggle buffer 305 is not selected by the selector 317, in other words, the pattern data and the image data are separated by the selector 317.

The pattern expansion unit 318 inputs the output of the toggle buffer 305, the count value of the read address counter 302, and the output of the register 314. The output of the toggle buffer 305 is 8 bits, and the pattern expansion unit 3
18 indicates that when the output of the register 314 becomes “H”, that is,
When the pattern data is input, 1 bit is selected from 8 bits of the pattern data according to the value of the lower 3 bits in the output of the read address counter 302, and only the selected 1 bit pattern data is transferred to the pattern synthesizing unit 319.
Output to.

The E terminal output of the pattern area extraction unit 308 sets an area for combining the image data and the pattern data. In the pattern composition unit 319, the E terminal output of the pattern area extraction unit 308 is registered in the registers 315 and 315. 31
By way of 6, it is input after being delayed by 2 pixel clocks. The pattern synthesis unit 319 synthesizes the image data input from the register 313 and the pattern data input from the pattern expansion unit 318 according to the signal input from the register 316. Here, the combination of the image data of 8 bits and the pattern data of 1 bit is executed by taking the logical sum of the output of a predetermined bit in the image data and the pattern data. FIG. 7 is a timing chart showing an output operation example of each unit in the pattern synthesis processing unit 300.

Thus, even if the image data and the pattern data are stored in one memory, the pattern synthesizing process can be performed in real time. Therefore, a dedicated memory for storing the pattern data is not required, and the cost for the device can be suppressed. This is because it is not necessary to make the image density of the pattern image added to the background of the image in the pattern synthesis processing strict.
This is possible by setting the pattern data per pixel to 1 bit. Here, when changing the image density of the pattern image, it suffices to change the bit at which the pattern data is combined in the 8-bit image data.

Next, the pattern data memories 407, 4
The storage in 08 will be described. In this embodiment, a partial area of the original image read by the image reading unit 101 can be stored as a pattern image in the memories 407 and 408. The 8-bit image data input from the image reading unit 101 to the image processing unit 102 is obtained from the filter unit 204 by 1 bi in the configuration shown in FIG.
The image data of t, that is, binarized, is output to the area control unit 206.

The area control unit 206 temporarily stores the image data of the pattern image input from the filter unit 204 in a memory (not shown), and the control unit 105 reads the image data from the memory to show the pattern image in FIG. It is displayed on the display unit 104a of the operation panel 104. Here, since the storage capacity of the memory 407 is 8 Kbytes, the size of the pattern image is, for example, as shown in FIG. 8, the maximum size is 256 × 256 pixels.

The image data stored in the area control unit 206 can be modified in various ways. For example, when the pattern image as shown in FIG. 9A is stored in the memory, when the points A and B in FIG. 9A are trimmed and rotated, the result becomes as shown in FIG. 9B. Figure 9
Combining 4 of (b) as basic pattern images,
The image shown in FIG. 9C is obtained. The image shown in FIG. 9C is modified, that is, scaled (enlarged or reduced) so that it can be stored in the memories 407 and 408 as a pattern image to be stored in the memories 407 and 408.
The pattern image is stored in 7, 408. These processes are performed by operating the operation panel 104.

As described above, by performing various correction processing of the pattern data, a desired pattern image can be easily and easily obtained. This is because, for example, when a designated area of a document image is used as a pattern image, it is not necessary to accurately create a pattern image in accordance with the designated area or to place the pattern image on the contact glass with high precision. It is possible to improve work efficiency.

FIG. 10 and FIG. 11 are explanatory views showing other correction examples of pattern images. Similar to the case of FIG. 9,
When the points A and B in FIGS. 10A and 11A are trimmed and rotated, the results are as shown in FIGS. 10B and 11B, respectively. Combining the two results in the ones shown in FIGS. 10 (c) and 11 (c).

[0034]

As described above, the image processing apparatus according to the present invention writes the image data and the pattern data in one memory and combines the image data and the pattern data read from the memory. Further, when the read image data is registered as pattern data, the pattern data is displayed and correction is performed based on the display. Further, when the read image data is registered as pattern data, the number of times the pattern data is repeated is specified, and the pattern data is enlarged or reduced based on the specified number of times. Therefore, different data are stored together in one memory. The cost of the device can be suppressed by reducing the number of required memories, and image deterioration can be avoided by easily registering a desired pattern image in the memory in an appropriate state. The work efficiency in registering the pattern image can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image forming apparatus to which an image processing apparatus according to the present invention is applied.

FIG. 2 is a block diagram showing a schematic configuration of an image processing unit shown in FIG.

FIG. 3 is a block diagram showing a schematic configuration of a pattern synthesizing unit according to the present invention.

FIG. 4 is a circuit diagram showing a configuration of a toggle buffer shown in FIG.

5 is image data stored in the memory shown in FIG. 4,
It is explanatory drawing which shows the state of pattern data.

6 is an explanatory diagram showing the size of a pattern image stored in the memory shown in FIG.

7 is a timing chart showing an operation example of the pattern synthesizing unit shown in FIG.

8 is an explanatory diagram showing the maximum size of a pattern image stored in the memory shown in FIG.

FIG. 9 is an explanatory diagram showing various correction processes for a pattern image read by an image reading unit.

FIG. 10 is an explanatory diagram showing various correction processes for a pattern image read by an image reading unit.

FIG. 11 is an explanatory diagram showing various correction processes for a pattern image read by an image reading unit.

[Explanation of symbols]

Reference Signs List 101 image reading unit 102 image processing unit 104 operation panel 104a display unit 105 control unit 201 scaling unit 202 processing / editing unit 203 gamma correction unit 204 filter unit 206 area control unit 301 write address counter 302 read address counter 303 sub-scanning address counter 304 305
Toggle buffer 306 Pattern address generator 307 317
Selector 308 Pattern area extraction unit 309 to 316 401 402 Register 318 Pattern expansion unit 319 Pattern synthesis unit

Claims (3)

[Claims] 1. An image reading means for reading image data,
Image recording means for recording the image data read by the image reading means, and storage means for storing the image data and pattern data read by the image reading means,
The image data output from the storage means and the pattern data are discriminated and separated, and the interpolation means for interpolating the image data read from the storage means when the pattern data is generated. An image processing device characterized by: 2. An image reading means for reading image data,
Image recording means for recording the image data read by the image reading means, storage means for registering the image data read by the image reading means as pattern data, and when registering the pattern data in the storage means,
An image processing apparatus comprising: a display unit that displays the pattern data; and a correction unit that corrects the pattern data displayed on the display unit. 3. Image reading means for reading image data,
Image recording means for recording the image data read by the image reading means, storage means for registering the image data read by the image reading means as pattern data, and when registering the pattern data in the storage means,
An image processing apparatus comprising: a number-of-times designating unit for designating the number of times of repeating the pattern data; and an image editing unit for enlarging or reducing the pattern data based on the number of times designated by the number of times designating unit.