JPH0697791A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To completely prevent the overlapping of plural clocks in plural function modules in the semiconductor integrated circuit having plural function modules which are driven by the plural clocks. CONSTITUTION:A 1st CR delay circuit 14A is connected between the output of a 1st clock overlapping preventing circuit 13A and the input of a 2nd clock overlapping preventing circuit 13B. A 2nd CR delay circuit 14B is connected between the 2nd clock overlapping preventing circuit 13B and the input of the 1st clock overlapping preventing circuit 13A. The delay time of the 1st CR delay circuit 14A is made longer than the longest delay time of the 1st CR delay circuit 14A in plural function modules. The delay time of the 2nd CR delay circuit 14B is made longer than the longest delay time to be generated in the 2nd clock line 3B in the plural function modules.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit provided with an overlap prevention circuit for preventing a plurality of clocks from overlapping each other.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit such as a microcomputer, a plurality of different clocks are used to drive a circuit such as a shift register. These clocks are supplied from a clock generation circuit to a semiconductor substrate. An extended clock line supplies a plurality of functional modules formed on the substrate. In this case, in order to prevent erroneous operation of the circuit such as lasing due to the mutual overlapping of the clocks due to the difference in the delay time between the clocks, FIG.
A clock overlap prevention circuit as shown in FIG. In the figure, (1) is a semiconductor substrate, (2) is a clock generation circuit for generating first and second clocks CL1 and CL2, and (3A) and (3B) are first and second.
Clocks CL1 and CL2 of the first and second clock lines extending on the substrate (1) for supplying the plurality of functional modules (4) and (5) and (6), It is formed of aluminum wiring having a low sheet resistance value in order to reduce signal propagation delay.

And (13A) is the second clock CL2.
Is a first clock overlap prevention circuit for raising the first clock after falling, and (13B) is a second clock overlapping prevention circuit for raising the second clock CL2 after falling of the first clock CL1. Is a clock overlap prevention circuit. Here, the first clock overlap prevention circuit (13
In (A), the inverter (7) to which the output of the second clock overlap prevention circuit (13B) is input and the output of the inverter (7) are input to one side and the clock generating circuit (2) to the other side. 2) is composed of a NAND gate (8) to which the first clock CL1 output from (1) is input and an output inverter (9). In addition, the second clock overlap prevention circuit (13B) includes a first clock overlap prevention circuit (13B).
An inverter (10) to which the output of A) is input, and an output of the inverter (10) to one of the second clocks CL2 output from the clock generation circuit (2) to the other.
Input gate (11) and output inverter
(11).

Next, the operation of this circuit will be described with reference to the timing charts according to the conventional example shown in FIGS. As shown by the solid line in FIG. 4, when the second clock CL2 output from the second clock overlap prevention circuit (13B) is at the high level, the first clock overlap prevention circuit (13
The output of the NAND gate (8) constituting A) is fixed at a high level, and in response to this, the first clock CL1 output from the first clock overlap prevention circuit (13A) is fixed at a low level. The second clock CL2 output from the second clock overlap prevention circuit (13B)
After the signal has fallen to the low level, the high level fixing of the output of the NAND gate (8) is released, and the high level of the first clock CL1 is output from the first clock overlap prevention circuit (13A).

The first clock overlap prevention circuit (13
When the first clock CL1 output from A) is at a high level, the output of the NAND gate (11) constituting the second clock overlap prevention circuit (13B) is fixed at a high level. 2 clock overlap prevention circuit (13
The second clock CL2 output from B) is fixed to the low level. Then, after the first clock CL1 output from the first clock overlap prevention circuit (13A) falls to the low level, the high level fixing of the output of the NAND gate (11) is released, whereby the second clock CL1 is released. From the clock overlap prevention circuit (13B) to the second clock C
The high level of L2 is output. In this way, the overlap between the clocks of the first and second clocks CL1 and CL2 is prevented.

[0006]

However, in a plurality of functional modules (4), (5) and (6) formed on the substrate (1) constituting the semiconductor integrated circuit, the integration density is improved. Is emphasized. Therefore, the first and second
With respect to the clock lines (3A) and (3B), wiring having a high sheet resistance value, for example, polysilicon or the like is often used. Therefore, inside the plurality of function modules (4) and (5) and (6), as shown in FIG. 3, the first and second clock lines (3A) and (3) are provided.
B) is a parasitic resistance (R ₄₁ , R ₄₂ , R) such as polysilicon.
₅₁ , R ₅₂ , R ₆₁ , R ₆₂ ) and load capacity (C ₄₁ , C
₄₂ , C ₅₁ , C ₅₂ , C ₆₁ , C ₆₂ ) is formed, and the first and second clocks CL are formed.
1 and CL2 drive a predetermined circuit (not shown) via this CR delay circuit. Therefore, the first and second clocks CL generated by the above-described first and second clock overlap prevention circuits (13A) and (13B).
The separations of 1 and CL2 are ensured in the vicinity of the clock overlap prevention circuit (indicated by a) and on the first and second clock lines (3A) and (3B) laid with aluminum having a low sheet resistance value. However, inside the plurality of functional modules (4) and (5) and (6) (indicated by b, c and d), the first and second clock lines (3A) and (3B) are formed. As shown by the broken line in FIG. 4, there is a case in which the clocks overlap with each other due to the difference in the delay time determined based on the CR delay circuit that has been created. It had a problem of inviting.

[0007]

The present invention has been made in view of the above-mentioned problems, and in the above-mentioned semiconductor integrated circuit, the first clock overlap prevention circuit (13A) is provided.
Output and second clock overlap prevention circuit (13B)
First CR composed of a resistance and a capacitance between the input and the
A second circuit which is connected to a delay circuit (14A) and has a resistor and a capacitor between the output of the second clock overlap prevention circuit (13B) and the input of the first clock overlap prevention circuit (13A). Of the plurality of functional modules (4) and (5) by connecting the CR delay circuit (14B) of the first CR delay circuit (14A) to the first clock line (3A). And a maximum delay time of the CR delay circuit formed in (6), and the delay time of the second CR delay circuit (14B) is set to the second clock line (3B). Modules (4) and (5)
And (6) by making the delay time larger than the maximum delay time of the CR delay circuit, the first and second functional modules (4) and (5) and (6) are provided in all of the first and second functional modules. The present invention completely solves the overlap between the clocks of the second clocks CL1 and CL2, thereby solving the above-mentioned problem.

[0008]

According to the above-mentioned means, the plurality of functional modules (4) and (5) are connected to the first clock line (3A).
And the second clock C later than the latest falling edge of the first clock CL1 at the location (indicated by b, c, d) via the CR delay circuit formed in (6).
L2 acts to rise.

Further, the second clock line (3B) has a location (b, c, d) via a CR delay circuit formed in the plurality of functional modules (4), (5) and (6). ), The first clock CL1 rises later than the slowest fall of the second clock CL2. This allows the first and second clock lines (3A) and (3B) to be supplied at any location within the plurality of functional modules (4) and (5) and (6). Second clocks CL1 and C
It is possible to completely prevent the overlap between the L2 clocks.

[0010]

FIG. 1 is a circuit diagram showing an embodiment according to the present invention. It should be noted that in FIG. 1, the components designated by the same reference numerals as those in FIG. 3 indicate the same components. The present invention is different from the conventional example in that the first clock overlap prevention circuit (13A)
First CR composed of a resistor R ₁ and a capacitor C ₁ at the output of
A delay circuit (14A) is connected, and the output of the first CR delay circuit (14A) is the second clock overlap prevention circuit (1
3B) and the second CR delay circuit (1) which is input to the inverter (10) and which is composed of the resistor R ₂ and the capacitor C ₂ at the output of the second clock overlap prevention circuit (13B).
4B), and the output of the second CR delay circuit (14B) is input to the inverter (7) which constitutes the first clock overlap prevention circuit (13A).

The resistors R ₁ and R ₂ described above are formed of polysilicon, and the capacitors C ₁ and C ₂ are formed of a gate capacitor of a MOS transistor. Further, the delay time determined by the resistor R ₁ and the capacitor C ₁ which form the first CR delay circuit (14A) is the parasitic that the first clock line (3A) has in the functional module (4). A CR delay circuit formed of a resistor R ₄₁ and a load capacitance C ₄₁ , and a CR delay circuit formed of a parasitic resistance R ₅₁ and a load capacitance C _{51 included} in the functional module (5), and a functional module ( It is set to a value larger than the maximum delay time of the CR delay circuit formed by the parasitic resistance R ₆₁ and the load capacitance C _{61 included} in 6). Also, the second CR delay circuit (14B)
The delay time determined by the resistance R ₂ and the capacitance C ₂ which form the above is formed by the parasitic resistance R ₄₂ and the load capacitance C ₄₂ which the second clock line (3B) has in the functional module (4). CR delay circuit and a CR delay circuit formed by a parasitic resistance R ₅₂ and a load capacitance C ₅₂ in the functional module (5), and a parasitic resistance R ₆₂ and a load in the functional module (6) It is characterized in that it is set to a value larger than the maximum delay time of the CR delay circuit formed by the capacitor C ₆₂ .

Next, the operation of the above-described circuit of the present invention will be described with reference to FIGS. FIG. 2 is a timing diagram according to one practical example of the present invention. In the figure, when the second clock CL2 output from the second clock overlap prevention circuit (13B) is at a high level, the output of the NAND gate (8) constituting the first clock overlap prevention circuit (13A) is high. The level is fixed to the level, and the first clock CL1 output from the first clock overlap prevention circuit (13A) in response to this is fixed to the low level. Then, when the second clock CL2 output from the second clock overlap prevention circuit (13B) falls to the low level, this fall is caused by the second CR delay circuit (14B) as shown by the broken line in FIG. It is delayed and transmitted to the first clock overlap prevention circuit (13A). Therefore, a second clock line at a second location (indicated by b, c, d) via a CR delay circuit formed in a plurality of functional modules (4) and (5) and (6). The high level fixing of the output of the NAND gate (8) is released after the latest falling of the clock CL2, and the first clock overlap prevention circuit (1
3A) outputs the high level of the first clock CL1.

The first clock overlap prevention circuit (13
When the first clock CL1 output from A) is at a high level, the output of the NAND gate (11) constituting the second clock overlap prevention circuit (13B) is fixed at a high level. 2 clock overlap prevention circuit (13
The second clock CL2 output from B) is fixed to the low level. Then, when the first clock CL1 output from the first clock overlap prevention circuit (13A) falls to a low level, this fall is caused by the first CR delay circuit (14A) as shown by the broken line in FIG. It is delayed and transmitted to the second clock overlap prevention circuit (13B). Therefore, the C formed in the plurality of functional modules (4) and (5) and (6) on the first clock line (3A).
First at location (shown as b, c, d) through R delay circuit
The high level fixed output of the NAND gate (11) is released after the latest falling edge of the clock CL1 of the second clock CL1 and the high level of the second clock CL2 is output from the second clock overlap prevention circuit (13B). To be done.

Thus, according to the present invention, the first and second clock lines (3A) and (3B) have a plurality of function modules.
Also at the location (indicated by b, c, d) through the CR delay circuit formed in (4) and (5) and (6).
Also, it is possible to ensure the separation between the clocks of the second clocks CL1 and CL2. still,
First and second CR delay circuits (14A) and (14B)
Other delay circuits may be used instead of. For example, a delay circuit in which a plurality of inverters are connected can be used.

In this embodiment, the case has been described in which the two clocks are completely prevented from overlapping each other.
Without being limited to this, it is apparent that the concept described above can be similarly applied to a semiconductor integrated circuit having two or more clocks.

[0016]

As described above, according to the present invention, the first function module is provided in the plurality of functional modules provided on the semiconductor substrate.
And the provision of the first and second CR delay circuits (14A) and (14B) having a delay time larger than the maximum delay time generated in the second clock lines (3A) and (3B). It is possible to completely prevent the clocks from overlapping with each other in all of the plurality of function modules, so that it is possible to provide a semiconductor integrated circuit in which malfunctions due to lasing and the like are eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram according to an embodiment of the present invention.

FIG. 2 is a timing diagram according to an embodiment of the present invention.

FIG. 3 is a circuit diagram according to a conventional example.

FIG. 4 is a timing diagram according to a conventional example.

[Explanation of symbols]

 1: semiconductor substrate 2: clock generation circuit 3A: first clock line 3B: second clock line 4, 5, 6: functional module 13A: first clock overlap prevention circuit 13B: second clock overlap prevention Circuit 14A: First CR delay circuit 14B: Second CR delay circuit CL1: First clock CL2: Second clock Vss: Ground voltage

Claims (2)

[Claims] 1. A clock generation circuit provided on a semiconductor substrate for generating at least first and second clocks,
A first clock overlap prevention circuit for raising the first clock after the second clock falls; and a first clock overlap prevention circuit for raising the second clock after the first clock falls. Output from the first and second clock overlap prevention circuits for supplying the two clock overlap prevention circuits and the first and second clocks to the plurality of functional modules provided on the substrate. In a semiconductor integrated circuit having first and second clock lines extending on the substrate, a first integrated circuit is provided between an output of the first clock overlap prevention circuit and an input of the second clock overlap prevention circuit. And a second delay circuit connected between the output of the second clock overlap prevention circuit and the input of the first clock overlap prevention circuit.
The delay circuits of the first and second delay circuits are connected to each other, and the delay time of the first delay circuit is set to be larger than the maximum delay time generated in the first clock line in the plurality of function modules. A semiconductor integrated circuit, wherein a delay time of a delay circuit is set to be larger than a maximum delay time generated on the second clock line in the plurality of function modules. 2. The semiconductor integrated circuit according to claim 1, wherein the first and second delay circuits are CR delay circuits each including a resistor and a capacitor.