JPH0697755A - Delay adjusting circuit - Google Patents

Abstract

PURPOSE:To obtain the delay adjusting circuit capable of drastically reducing cost by enabling the rough adjustment and fine adjustment of a delay time of a C system to a Y to execute without using an expensive delay line and an FIFO memory. CONSTITUTION:An analog delay circuit 11 and a digital delay circuit 13 are used jointly, and in the digital delay circuit 13, rough adjustment of a delay time is executed by delaying a C (or PB/PR) signal by a clock unit. On the other hand, in the analog delay circuit 11, fine adjustment of a delay time is executed steplessly in a smaller range than the clock unit of the digital delay circuit 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay adjusting circuit,
In particular, in a video device such as a VTR that component-records a color video signal of a high definition (HD: High Definition) television system, between a Y (luminance) signal and a C (chroma) signal or between a Y signal and two color difference signals (P _{The present} invention relates to a delay adjustment circuit that adjusts a recording / reproducing delay time between _B / P _R ).

[0002]

2. Description of the Related Art When a color video signal is recorded as a component, since a band handling a Y system and a filter handling a C system are different from each other, a time difference occurs between the Y system and the C system which have passed through these filters. The delay time of the C system with respect to the Y system is adjusted so as to eliminate this time difference. FIG. 3 shows a conventional example of a delay adjustment circuit for adjusting the delay time. In FIG. 3, the analog Y signal is
After being digitized by the A / D converter 32 using the clock generated by the PLL circuit 31 as a sampling clock, the FIFO (fir
It is written in the memory 33 of the (st in first out) method.

On the other hand, the analog C (or P _B / P _R ) signal has a delay clock obtained by delaying the clock by the clock delay line 34 as a sampling clock A.
After being digitized by the / D converter 35, a FIFO type memory 36 using the delayed clock as a write clock
Written in. The FIFO memories 33 and 36 are memories that can perform writing and reading separately,
The time can be shifted in clock units. The data written in these memories 33 and 36 are read at the same read clock.

[0004]

As described above, in the conventional delay adjustment circuit, the FIFO memories 33 and 36 are used to provide the C
The delay time is adjusted by performing the writing of the system at a time different from the writing of the Y system and performing the reading at the same time.
Although the FO memories 33 and 36 can be performed in clock units, it is necessary to use an expensive clock delay line 34 in order to perform fine adjustment in a time smaller than the clock units, which is a drawback of high cost.

Therefore, the present invention uses an expensive delay line or FIF.
An object of the present invention is to provide a delay adjustment circuit that enables a significant cost reduction by enabling rough adjustment and fine adjustment of the delay time of the C system with respect to the Y system without using an O memory.

[0006]

A delay adjusting circuit according to the present invention is a delay adjusting circuit for adjusting a delay time of a C signal or a P _B / P _R signal with respect to a Y signal. It comprises an adjustable digital delay circuit and an analog delay circuit capable of adjusting the delay time in units smaller than the clock unit.

[0007]

In the digital delay circuit, the delay time is roughly adjusted by adjusting the delay time in clock units, and in the analog delay circuit, the delay time is adjusted by adjusting the delay time in units smaller than the clock unit of the digital delay circuit. Fine tune. Thus, by using the digital delay circuit and the analog delay circuit together, the delay time of the C system with respect to the Y system can be finely adjusted infinitely.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, for example, a case where the present invention is applied to a recording signal processing system for component recording of a color video signal. In addition,
The same applies to the reproduction signal processing system. In the figure,
The analog C (or P _B / P _R ) signal is first delayed by the analog delay circuit 11 and then digitized by the A / D converter 12.

As is apparent from FIG. 1, the analog delay circuit 11 includes an operational amplifier OP, an input resistance R ₁ on the inverting input terminal side of the operational amplifier OP, an input resistance R ₂ on the non-inverting input terminal side of the operational amplifier OP, and It is constituted by an all-pass filter including a feedback resistor R ₃ , a capacitor C and a coil L connected in series between the non-inverting input terminal of the operational amplifier OP and the ground. In the analog delay circuit 11, the input resistance R ₂ is a variable resistance, and the resistance value is changed to change the time constant determined between the constants of the capacitor C and the coil L, thereby changing the analog C (or,
The delay time of the P _B / P _R ) signal can be adjusted steplessly.

In this embodiment, the analog delay circuit 1
Although the case where the all-pass filter is used as 1 has been described, the present invention is not limited to this, and it is also possible to use, for example, a bi-quad filter having a known circuit configuration. This biquad filter is a type of active filter and is a filter configured by two or more amplifiers and multiple feedback, and can be incorporated in the IC. In the bi-watt filter, the delay time can be adjusted by changing the transconductance g _m .

C digitized by the A / D converter 12
(Or P _B / P _R ) signal is the digital delay circuit 13
Is supplied to. The digital delay circuit 13 includes delay lines 14 _{1 to} 14 such as n flip-flops connected in cascade.
_n , which selects the input digital signal D ₀ and the delayed digital signals D _{1 to} D _n of each stage.
It is designed so that it is selectively derived according to the delay time.

Therefore, the digital C (or P _B /
The P _R) signal, by passing the digital delay circuit 13, as shown in FIG. 2, will be able to delay in clock units. On the other hand, the analog Y signal is sent to the A / D converter 1
It is digitalized in 6 and output as a digital Y signal.

As described above, the analog delay circuit 11 and the digital delay circuit 13 are used together, and the digital delay circuit 13 delays the C (or P _B / P _R ) signal in clock units to roughly adjust the delay time. On the other hand, in the analog delay circuit 11, the fine adjustment of the delay time is performed steplessly in a range smaller than the clock unit of the digital delay circuit 13, thereby making it possible to use the expensive FIFO memories 33 and 36 and the clock delay line as in the conventional case. Even if 34 (see FIG. 3) is not used, Y
The delay time of the C (or P _B / P _R ) signal with respect to the signal can be accurately adjusted. In the case where only the analog delay circuit 11 is configured, if delay is performed for a long time,
There is a problem that the number of stages of the circuit increases and the circuit scale increases.

[0014]

As described above, according to the present invention,
The analog delay circuit and the digital delay circuit are used together, and the digital delay circuit adjusts the delay time in clock units, while the analog delay circuit adjusts the delay time steplessly in a range smaller than the clock unit of the digital delay circuit. By doing so, even if an expensive FIFO memory or a delay line for clock is not used, C
Since the delay time of the (or P _B / P _R ) signal can be adjusted with high precision, it is possible to significantly reduce the cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the principle of delay in a digital delay circuit.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 11 analog delay circuit 12, 16, 32, 35 A / D converter 13 digital delay circuit 31 PLL circuit 33, 36 FIFO type memory 34 clock delay line

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yukie Yoshizawa 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (5)

[Claims] 1. A delay adjusting circuit for adjusting a delay time of a chroma signal or two color difference signals with respect to a luminance signal, wherein the delay time is adjustable in clock units, and the delay time is adjusted by the clock. A delay adjustment circuit comprising an analog delay circuit that can be adjusted in units smaller than the unit. 2. The delay adjusting circuit according to claim 1, wherein the analog delay circuit is configured by an all-pass filter. 3. The analog delay circuit is constituted by a biquad filter.
The described delay adjustment circuit. 4. The delay adjusting circuit according to claim 2, wherein the all-pass filter adjusts the delay time by changing a time constant of the all-pass filter. 5. The delay adjustment circuit according to claim 3, wherein the biquad filter adjusts the delay time by changing a mutual conductance of the biquad filter.