JPH0697447A - Insulated gate semiconductor device - Google Patents
Insulated gate semiconductor deviceInfo
- Publication number
- JPH0697447A JPH0697447A JP24295092A JP24295092A JPH0697447A JP H0697447 A JPH0697447 A JP H0697447A JP 24295092 A JP24295092 A JP 24295092A JP 24295092 A JP24295092 A JP 24295092A JP H0697447 A JPH0697447 A JP H0697447A
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- Japan
- Prior art keywords
- semiconductor
- region
- gate
- semiconductor region
- semiconductor device
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特に
高周波用途に好適な絶縁ゲート半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an insulated gate semiconductor device suitable for high frequency applications.
【０００２】[0002]
【従来の技術】従来、電力用途の絶縁ゲート形電界効果
トランジスタ（ＭＯＳＦＥＴ）においては、１９９０年
電子情報通信学会秋季全国大会Ｃ−４８１及び１９９１
年電子情報通信学会春季全国大会Ｃ−５６９に記載のよ
うに、高周波特性改善のために、ゲート長や低濃度ドレ
イン領域の長さを短くして、遮断周波数の向上やドレイ
ン−基板間の容量の低減の方策が取られていた。2. Description of the Related Art Conventionally, in insulated gate field effect transistors (MOSFETs) for power use, the 1990 National Conference of the Institute of Electronics, Information and Communication Engineers C-481 and 1991.
In order to improve high-frequency characteristics, shorten the gate length and the length of the low-concentration drain region to improve the cut-off frequency and the capacitance between the drain and the substrate, as described in C-569 of the IEICE Spring National Congress, 2016. The measures to reduce
【０００３】[0003]
【発明が解決しようとする課題】前記従来技術には、Ｍ
ＯＳＦＥＴのゲート長が短くなった場合に、高周波特性
がゲート電極の抵抗により制限されて低下する問題や、
しきい電圧が低下したり、安全動作領域が狭くなる問題
があった。従って本発明の目的は、ゲート電極の抵抗を
極力して高周波特性を改善することにある。また本発明
の他の目的は、かつＭＯＳＦＥＴのしきい電圧特性や安
全動作領域を改善することによって、高性能なＭＯＳＦ
ＥＴを提供することにある。本発明の他の目的は、通信
用途に好適な高周波増幅器を提供することにある。SUMMARY OF THE INVENTION In the above-mentioned prior art, M
When the gate length of the OSFET becomes short, the high-frequency characteristics are limited by the resistance of the gate electrode and deteriorate,
There are problems that the threshold voltage is lowered and the safe operation area is narrowed. Therefore, an object of the present invention is to improve the high frequency characteristics by minimizing the resistance of the gate electrode. Another object of the present invention is to improve the threshold voltage characteristics and the safe operating area of the MOSFET, thereby improving the performance of the high-performance MOSF.
To provide ET. Another object of the present invention is to provide a high frequency amplifier suitable for communication applications.
【０００４】[0004]
【課題を解決するための手段】上記目的を達成するため
に、本発明の一実施形態によれば、第１導電型の第１半
導体領域（１）上に第１導電型の第２半導体領域（２）
を設け、半導体主面から前記第１半導体領域（１）に達
するように形成した第１導電型の第３半導体領域（３）
を設け、第２導電型の第４半導体領域（４）をＭＯＳＦ
ＥＴのソース領域とし、前記第２半導体領域（２）内に
形成された第２導電型の低不純物濃度の第５半導体領域
（５）並びに第２導電型の高不純物濃度の第６半導体領
域（６）をドレイン領域とし、上記ソース、ドレイン間
に絶縁膜（８）を介してゲート電極（９）を形成し、そ
のゲート電極（９）の膜厚がゲート長よりも大きくした
こと特徴とするものである（図１参照）。本発明の好適
な実施形態は、前記ソース領域端部に隣接して設けられ
た第１導電型の第７半導体領域（７）を設けたことを特
徴とするものである（図１参照）。本発明の好適な実施
形態によれば、前記第１導電型の第７半導体領域（７）
が前記ゲート電極もしくはそのゲート電極を覆った絶縁
物をマスクとして、半導体主面に対して斜め方向のイオ
ン打ち込み法によって形成されたことを特徴とするもの
である（図３参照）。In order to achieve the above object, according to one embodiment of the present invention, a second semiconductor region of a first conductivity type is formed on a first semiconductor region (1) of a first conductivity type. (2)
And a third semiconductor region (3) of the first conductivity type formed so as to reach the first semiconductor region (1) from the semiconductor main surface.
And a fourth semiconductor region (4) of the second conductivity type is provided with a MOSF.
As a source region of ET, a fifth semiconductor region (5) of the second conductivity type and a low impurity concentration and a sixth semiconductor region of the second conductivity type and a high impurity concentration (which are formed in the second semiconductor region (2) ( 6) is used as a drain region, a gate electrode (9) is formed between the source and the drain via an insulating film (8), and the thickness of the gate electrode (9) is larger than the gate length. (See FIG. 1). A preferred embodiment of the present invention is characterized in that a seventh semiconductor region (7) of the first conductivity type is provided adjacent to the end of the source region (see FIG. 1). According to a preferred embodiment of the present invention, the seventh semiconductor region (7) of the first conductivity type.
Is formed by an ion implantation method in an oblique direction with respect to the semiconductor main surface using the gate electrode or an insulator covering the gate electrode as a mask (see FIG. 3).
【０００５】[0005]
【作用】本発明の代表的な実施形態（図１）では、短チ
ャネルを有するＭＯＳＦＥＴのゲート電極の膜厚をゲー
ト長さより大とされている。これにより、ゲート電極の
抵抗が大幅に低減でき、高周波特性を向上できる（図４
参照）。本発明の好適な実施形態では、ソース領域端部
に隣接してポケット状に高濃度ベース領域を設けたこと
である。これにより、ゲート電極の抵抗が大幅に低減で
き、ＭＯＳＦＥＴの高周波特性を向上させることができ
る（図４参照）とともに、ポケット状の高濃度ベース領
域によって、しきい電圧の低下（図５参照）や安全動作
領域の減少を防止して、高性能ＭＯＳＦＥＴを提供でき
る。本発明のＭＯＳＦＥＴを電力用高周波増幅器として
用いた場合、２０ＧＨｚの動作周波数においても動作さ
せることができ、２．５ＧＨｚでの付加効率の向上が図
れる。In a typical embodiment of the present invention (FIG. 1), the film thickness of the gate electrode of a MOSFET having a short channel is made larger than the gate length. As a result, the resistance of the gate electrode can be significantly reduced and the high frequency characteristics can be improved (see FIG. 4).
reference). In a preferred embodiment of the present invention, the high-concentration base region is provided in a pocket shape adjacent to the end of the source region. As a result, the resistance of the gate electrode can be significantly reduced, the high frequency characteristics of the MOSFET can be improved (see FIG. 4), and the pocket-like high-concentration base region lowers the threshold voltage (see FIG. 5). A high performance MOSFET can be provided by preventing a decrease in the safe operation area. When the MOSFET of the present invention is used as a high frequency power amplifier, it can be operated at an operating frequency of 20 GHz, and the added efficiency at 2.5 GHz can be improved.
【０００６】[0006]
【実施例】以下、本発明の実施例を図面により詳細に説
明する。図１は本発明の第１の実施例の絶縁ゲート半導
体装置の断面図を示してある。本素子はソース接地型の
高周波用ＭＯＳＦＥＴである。本構造は０．０２Ωｃｍ
以下のＰ型半導体基板１上に低濃度Ｐ型半導体層２を厚
さ５μｍのエピタキシャル成長したものを用いる。その
半導体表面より、ベースコンタクト層となるＰ型領域３
をＰ型半導体基板１に達するように５μｍ以上の深さに
形成する。ゲート絶縁膜８は厚さ３０ｎｍで、ゲート電
極９はモリブデン金属を用い、膜厚０．８μｍ、ゲート
長０．４μｍである。ここで、ゲート電極膜厚がゲート
長より大きいことに特徴があり、その結果、ゲート長が
短くなることによるゲート抵抗の増大が防止されてい
る。そして、ゲート電極の端部側壁を絶縁物スペーサ７
１で覆い、その絶縁物７１下方の半導体表面領域に表面
濃度が１×１０18／ｃｍ3以下の低濃度Ｎ型領域６が自
己整合的に配置されている。ここで、スペーサの幅は
０．８μｍであり、ドレイン電極を取り出すドレイン・
コンタクト領域の幅は０．６μｍである。さらに、ソー
ス領域４の端部はポケット状のＰ型半導体領域７で覆わ
れ、その領域はベース領域３に接続されている。なおア
ルミニウム金属のドレイン電極１２及びソース電極１０
は高濃度Ｎ型領域６、４に接続されている。裏面のソー
ス電極１１は前記Ｐ型半導体基板１とＰ型領域３を介し
て前記ソース電極１０に接続されている。Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view of an insulated gate semiconductor device according to the first embodiment of the present invention. This element is a source-grounded high-frequency MOSFET. This structure is 0.02 Ωcm
The following low-concentration P-type semiconductor layer 2 is epitaxially grown to a thickness of 5 μm on the P-type semiconductor substrate 1. From the semiconductor surface, a P-type region 3 to be a base contact layer
Is formed to a depth of 5 μm or more so as to reach the P-type semiconductor substrate 1. The gate insulating film 8 has a thickness of 30 nm, the gate electrode 9 is made of molybdenum metal, and has a film thickness of 0.8 μm and a gate length of 0.4 μm. Here, the gate electrode film thickness is larger than the gate length, and as a result, the increase in gate resistance due to the shortened gate length is prevented. Then, the side wall of the end portion of the gate electrode is covered with the insulator spacer 7
1, a low-concentration N-type region 6 having a surface concentration of 1 × 10 18 / cm 3 or less is arranged in a self-aligned manner in the semiconductor surface region below the insulator 71. Here, the width of the spacer is 0.8 μm, and the drain
The width of the contact region is 0.6 μm. Furthermore, the end of the source region 4 is covered with a pocket-shaped P-type semiconductor region 7, and the region is connected to the base region 3. The drain electrode 12 and the source electrode 10 made of aluminum metal
Are connected to the high-concentration N-type regions 6 and 4. The source electrode 11 on the back surface is connected to the source electrode 10 via the P-type semiconductor substrate 1 and the P-type region 3.
【０００７】図２は本発明のＭＯＳＦＥＴの平面図であ
り、ゲート電極９がストライプ状に形成され、そのスト
ライプの長さは３００μｍである。ゲート取り出し電極
はストライプ電極のバスライン部で接続されてされてい
る。またドレイン電極１２はそのまま取り出し電極とな
り、ソース電極１０はベース３とソース４とを接続する
ショートバーの役目をしている。FIG. 2 is a plan view of the MOSFET of the present invention, in which the gate electrode 9 is formed in a stripe shape, and the stripe length is 300 μm. The gate extraction electrodes are connected by the bus line portion of the stripe electrode. Further, the drain electrode 12 directly serves as an extraction electrode, and the source electrode 10 serves as a short bar connecting the base 3 and the source 4.
【０００８】図３は本発明のＭＯＳＦＥＴの主要製造プ
ロセスを示す断面構造図である。FIG. 3 is a sectional structural view showing the main manufacturing process of the MOSFET of the present invention.
【０００９】（ａ）ゲート絶縁膜８形成後、モリブデン
金属及び絶縁膜７０を被着し、ゲート電極９を形成す
る。 しかる後、（ｂ）ＣＶＤ法により絶縁膜を厚さ０．８μ
ｍ被着し、全面ドライエッチングにより、絶縁膜スペー
サ７１を形成する。次に、硼素イオン７’を図のように
半導体主面に斜めに照射する。加速エネルギは７５ｋｅ
Ｖ、ドーズ量は５×１０13／ｃｍ2である。この場合図
のごとく並置されたゲート電極９および絶縁膜スペーサ
７１がマスクとなって、ポケット上のＰ型領域７はドレ
イン領域にはほとんど形成されないでソース側にのみ形
成される。 （ｃ）前記絶縁膜スペーサ７１をマスクにして、低濃度
ドレイン領域５および高濃度ソース領域４をそれぞれイ
オン打ち込みにより形成する。打ち込み量は、ドレイン
がリン５×１０13／ｃｍ2、ソースが砒素１×１０15／
ｃｍ2である。 （ｄ）ドレイン電極コンタクト用の高濃度ドレイン領域
６を形成する。打ち込み量は、砒素１×１０15／ｃｍ2
である。 以下の工程は通常に行なわれる高周波半導体プロセスを
用いて製作できるので説明は省略する。本構造の特徴
は、ゲート電極膜の厚さがゲート長よりも大きいためゲ
ート長が短くなってもゲート抵抗の増大が抑えられるこ
と、そしてポケット状のベース領域がソース端部を覆っ
て設けられるためゲート長が短くなってもしきい電圧の
低下や安全動作領域の減少が抑えられること、さらには
ポケット状のベース領域がドレイン領域にはほとんど接
しないのでドレイン−ソース間の容量の増大も抑えられ
る。(A) After forming the gate insulating film 8, a molybdenum metal and an insulating film 70 are deposited to form a gate electrode 9. After that, (b) the thickness of the insulating film is 0.8 μm by the CVD method.
Then, the insulating film spacer 71 is formed by dry-etching the entire surface. Next, boron ions 7'are obliquely applied to the semiconductor main surface as shown in the figure. Acceleration energy is 75 ke
The V and dose amounts are 5 × 10 13 / cm 2 . In this case, the gate electrodes 9 and the insulating film spacers 71 juxtaposed as shown in the figure serve as a mask, and the P-type regions 7 on the pockets are scarcely formed in the drain region and are formed only on the source side. (C) Using the insulating film spacer 71 as a mask, the low concentration drain region 5 and the high concentration source region 4 are formed by ion implantation. The implantation amount was phosphorus 5 × 10 13 / cm 2 for the drain and arsenic 1 × 10 15 / cm for the source.
cm 2 . (D) The high-concentration drain region 6 for contacting the drain electrode is formed. The implantation amount is 1 × 10 15 / cm 2 arsenic
Is. Since the following steps can be manufactured by using a high frequency semiconductor process which is usually performed, the description thereof will be omitted. The feature of this structure is that the thickness of the gate electrode film is larger than the gate length, so that the increase of the gate resistance is suppressed even if the gate length is shortened, and that the pocket-shaped base region is provided to cover the source end. Therefore, even if the gate length is shortened, the reduction of the threshold voltage and the reduction of the safe operation region can be suppressed. Furthermore, since the pocket-shaped base region hardly contacts the drain region, the increase of the drain-source capacitance can also be suppressed. .
【００１０】本発明の効果を示す特性説明図を図４、図
５に示す。図４はパワーＭＯＳＦＥＴの遮断周波数ｆt
のチャネル長Ｌc依存性である。ここでゲート電極膜厚
は、従来構造では０．３μｍ一定に対して、本発明の構
造ではＬcが０．５μｍでは０．６μｍ以上、Ｌcが０．
３μｍでは０．６μｍ以上に設定している。ｆtは、Ｌc
の減少と共に向上するが、Ｌcが０．５μｍ以下の場合
には従来構造ではゲート抵抗の増大のために制限されて
しまう。一方、本発明の構造ではＬcが０．５μｍ以下
となっても、ｆtは、図のごとく向上する。また、図５
はＭＯＳＦＥＴのしきい電圧ＶTのチャネル長Ｌc依存性
である。ここで本発明の構造では、ポケット状のベース
領域が設けられている。従来構造ではＬcが１．０μｍ
以下の場合、ＶTが低下すると共にバラツキが増大する
など、性能低下が発生するが、本発明によれば、０．２
μｍ程度まで、性能低下はほとんど発生しない。また、
本発明の構造のパワーＭＯＳＦＥＴは、２次降伏などに
よる安全動作領域の減少も生じない。4 and 5 are characteristic explanatory diagrams showing the effect of the present invention. FIG. 4 shows the cutoff frequency ft of the power MOSFET.
Is dependent on the channel length Lc. Here, the gate electrode film thickness is constant at 0.3 μm in the conventional structure, but in the structure of the present invention, when Lc is 0.5 μm, it is 0.6 μm or more, and Lc is 0.
At 3 μm, it is set to 0.6 μm or more. ft is Lc
However, if Lc is 0.5 μm or less, the conventional structure is limited due to an increase in gate resistance. On the other hand, in the structure of the present invention, ft is improved as shown in the figure even when Lc is 0.5 μm or less. Also, FIG.
Is the channel length Lc dependence of the threshold voltage V T of the MOSFET. Here, in the structure of the present invention, a pocket-shaped base region is provided. Lc is 1.0 μm in the conventional structure
In the following cases, performance deterioration occurs such that V T decreases and variation increases, but according to the present invention, 0.2
There is almost no deterioration in performance up to about μm. Also,
The power MOSFET having the structure of the present invention does not reduce the safe operation area due to secondary breakdown.
【００１１】図６は、本発明の第２の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのドレイン領域６１を低濃度ドレイン領域５上
にＮ型不純物をドープした多結晶シリコンを積み上げる
ことにより形成している。これにより高濃度ドレイン領
域とシリコン基板との接触面積が減少し、ドレイン−ソ
ース間の容量が低減できた。また、低濃度ドレイン領域
５における高濃度ドレイン領域６１の端部からゲート電
極９の端部までの距離、つまり実効オフセット長が増大
してドレイン耐圧が約１０Ｖ向上した。FIG. 6 is a sectional structural view of an insulated gate semiconductor device according to the second embodiment of the present invention. In this embodiment, MO
The drain region 61 of the SFET is formed by stacking polycrystalline silicon doped with N-type impurities on the low concentration drain region 5. As a result, the contact area between the high-concentration drain region and the silicon substrate was reduced, and the drain-source capacitance could be reduced. Further, the distance from the end of the high-concentration drain region 61 to the end of the gate electrode 9 in the low-concentration drain region 5, that is, the effective offset length was increased, and the drain breakdown voltage was improved by about 10V.
【００１２】図７は、本発明の第３の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのドレイン電極を多層化し第２の取り出しドレ
イン電極１３を設け、電流容量の増大と取り出し電極の
配線の自由度を向上している。本構造では１層目のドレ
イン電極の幅が小さいので、その電流容量を増大させる
必要がある。FIG. 7 is a sectional structural view of an insulated gate semiconductor device according to the third embodiment of the present invention. In this embodiment, MO
The drain electrode of the SFET is multi-layered and the second extraction drain electrode 13 is provided to increase the current capacity and the degree of freedom of the wiring of the extraction electrode. In this structure, since the width of the drain electrode of the first layer is small, it is necessary to increase the current capacity.
【００１３】図８は、本発明の第４の実施例の絶縁ゲー
ト半導体装置の断面構造図である。本実施例では、ＭＯ
ＳＦＥＴのソース電極１０を半導体基板の表面より取り
出す構造にしている。複数個並置されたゲート電極９の
膜厚が０．８μｍ、ゲート長が０．４μｍで、そのゲー
ト電極の端部側壁を覆うように形成した絶縁物スペーサ
７１をマスクとして形成し、Ｎ型高濃度ソース領域２、
Ｎ型低濃度ドレイン領域５、ｎ型高濃度ドレイン領域
６、さらにポケット状のベース領域７を形成している。
その結果、ソース領域も低面積化が図れ、集積度が向上
した。FIG. 8 is a sectional structural view of an insulated gate semiconductor device according to the fourth embodiment of the present invention. In this embodiment, MO
The structure is such that the source electrode 10 of the SFET is taken out from the surface of the semiconductor substrate. A plurality of gate electrodes 9 juxtaposed in parallel have a film thickness of 0.8 μm and a gate length of 0.4 μm, and an insulator spacer 71 formed so as to cover the end sidewalls of the gate electrodes is used as a mask to form an N-type high electrode. Concentration source region 2,
An N-type low-concentration drain region 5, an n-type high-concentration drain region 6, and a pocket-shaped base region 7 are formed.
As a result, the area of the source region can be reduced and the degree of integration is improved.
【００１４】図９は、本発明の第５の実施例の通信用高
周波増幅器モジュールの回路配置図である。本実施例で
は、第１の実施例で説明したＭＯＳＦＥＴ（Ｑ１、Ｑ
２、Ｑ３）に加えて、抵抗、容量、インピーダンスなど
の高周波整合回路を図のように配置し、セラミック基板
上でモジュール化した。その結果、電源電圧３Ｖ、動作
周波数２．５ＧＨｚにおいて、出力電力２Ｗ、付加効率
６０％を達成し、従来のものに比べ格段に高性能化が図
れた。FIG. 9 is a circuit layout diagram of a communication high-frequency amplifier module according to a fifth embodiment of the present invention. In this embodiment, the MOSFETs (Q1, Q1) described in the first embodiment are
In addition to 2, Q3), a high-frequency matching circuit for resistance, capacitance, impedance, etc. was arranged as shown in the figure, and modularized on a ceramic substrate. As a result, at a power supply voltage of 3 V and an operating frequency of 2.5 GHz, an output power of 2 W and an additional efficiency of 60% were achieved, and the performance was remarkably improved as compared with the conventional one.
【００１５】[0015]
【発明の効果】本発明によれば、ゲート電極の抵抗が大
幅に低減でき、ＭＯＳＦＥＴの遮断周波数を向上させる
ことができるとともに、ポケット状の高濃度ベース領域
によって、しきい電圧の低下や安全動作領域の減少を防
止して、高性能ＭＯＳＦＥＴを提供できるので、ＭＯＳ
ＦＥＴの高周波特性が格段に向上するという効果があ
る。According to the present invention, the resistance of the gate electrode can be significantly reduced, the cutoff frequency of the MOSFET can be improved, and the pocket-like high-concentration base region can reduce the threshold voltage and ensure safe operation. Since it is possible to provide a high-performance MOSFET by preventing the reduction of the area,
There is an effect that the high frequency characteristics of the FET are significantly improved.
【図１】本発明の第１の実施例の半導体装置である。FIG. 1 is a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例の半導体装置である。FIG. 2 is a semiconductor device according to a first embodiment of the present invention.
【図３】本発明の実施例の製造工程を示す半導体装置で
ある。FIG. 3 is a semiconductor device showing a manufacturing process according to an embodiment of the present invention.
【図４】本発明の第１の実施例の特性説明図である。FIG. 4 is a characteristic explanatory diagram of the first embodiment of the present invention.
【図５】本発明の第１の実施例の特性説明図である。FIG. 5 is a characteristic explanatory diagram of the first embodiment of the present invention.
【図６】本発明の第２の実施例の半導体装置である。FIG. 6 is a semiconductor device according to a second embodiment of the present invention.
【図７】本発明の第３の実施例の半導体装置である。FIG. 7 is a semiconductor device according to a third embodiment of the present invention.
【図８】本発明の第４の実施例の半導体装置である。FIG. 8 is a semiconductor device according to a fourth embodiment of the present invention.
【図９】本発明の第５の実施例の半導体装置である。FIG. 9 is a semiconductor device of a fifth embodiment of the present invention.
１…Ｐ型高濃度半導体基板、２…Ｐ型半導体領域、３…
Ｐ型ベース領域、４…Ｎ型ソース領域、５…Ｎ型低濃度
ドレイン領域、６…Ｎ型高濃度ドレイン領域、６１…Ｎ
型多結晶ドレイン領域、７…Ｐ型ベース領域、７’…硼
素イオンビーム、７０…絶縁膜、７１…絶縁膜スペー
サ、８…ゲート絶縁膜、９…ゲート電極、１０…ソース
電極、１１…ソース裏面電極、１２…ドレイン電極、１
３…取り出しドレイン電極、１４…ベース基板電極。1 ... P-type high-concentration semiconductor substrate, 2 ... P-type semiconductor region, 3 ...
P-type base region, 4 ... N-type source region, 5 ... N-type low-concentration drain region, 6 ... N-type high-concentration drain region, 61 ... N
-Type polycrystalline drain region, 7 ... P-type base region, 7 '... Boron ion beam, 70 ... Insulating film, 71 ... Insulating film spacer, 8 ... Gate insulating film, 9 ... Gate electrode, 10 ... Source electrode, 11 ... Source Back electrode, 12 ... Drain electrode, 1
3 ... Extraction drain electrode, 14 ... Base substrate electrode.
Claims (6)
型の第２半導体領域を設け、半導体主面から前記第１半
導体領域に達するように形成した第１導電型の第３半導
体領域を設け、第２導電型の第４半導体領域をＭＯＳＦ
ＥＴのソースとし、前記第２半導体領域内に形成した第
２導電型の低不純物濃度の第５半導体領域並びに第２導
電型の高不純物濃度の第６半導体領域をＭＯＳＦＥＴの
ドレインとし、上記ソース、ドレイン間に絶縁膜を介し
て、ゲート電極を有するＭＯＳＦＥＴにおいて、そのゲ
ート電極の膜厚がゲート長さより大きいことを特徴とす
る絶縁ゲート半導体装置。1. A first-conductivity-type third semiconductor formed so that a first-conductivity-type second semiconductor region is provided on a first-conductivity-type first semiconductor region and reaches the first semiconductor region from the semiconductor main surface. A semiconductor region is provided, and a fourth semiconductor region of the second conductivity type is provided with a MOSF.
The source of ET, the fifth semiconductor region of the second conductivity type low impurity concentration and the sixth semiconductor region of the second conductivity type high impurity concentration formed in the second semiconductor region are used as the drain of the MOSFET, the source, In an MOSFET having a gate electrode via an insulating film between drains, the film thickness of the gate electrode is larger than the gate length.
第１導電型の第７半導体領域を設けたことを特徴とする
請求項１記載の絶縁ゲート半導体装置。2. The insulated gate semiconductor device according to claim 1, further comprising a seventh semiconductor region of the first conductivity type provided adjacent to an end of the source region.
ゲート電極もしくはそのゲート電極を覆った絶縁物をマ
スクとして、半導体主面に対して斜め方向のイオン打込
み法によって、形成されたことを特徴とする請求項２記
載の絶縁ゲート半導体装置。3. A seventh semiconductor region of the first conductivity type is formed by an ion implantation method in a direction oblique to the semiconductor main surface using the gate electrode or an insulator covering the gate electrode as a mask. The insulated gate semiconductor device according to claim 2, wherein
多結晶シリコンで形成されたことを特徴とする請求項１
記載の絶縁ゲート半導体装置。4. A part of the sixth semiconductor region of the second conductivity type is formed of polycrystalline silicon.
Insulated gate semiconductor device described.
多層金属電極で形成されていることを特徴とする請求項
１記載の絶縁ゲート半導体装置。5. A drain extraction electrode of a MOSFET,
The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is formed of a multilayer metal electrode.
体装置を用いて構成した高周波増幅器。6. A high-frequency amplifier constructed by using the insulated gate semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24295092A JP3216258B2 (en) | 1992-09-11 | 1992-09-11 | Insulated gate semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24295092A JP3216258B2 (en) | 1992-09-11 | 1992-09-11 | Insulated gate semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0697447A true JPH0697447A (en) | 1994-04-08 |
| JP3216258B2 JP3216258B2 (en) | 2001-10-09 |
Family
ID=17096640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24295092A Expired - Lifetime JP3216258B2 (en) | 1992-09-11 | 1992-09-11 | Insulated gate semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3216258B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1187220A2 (en) * | 2000-09-11 | 2002-03-13 | Kabushiki Kaisha Toshiba | MOS field effect transistor with reduced on-resistance |
| US6552389B2 (en) | 2000-12-14 | 2003-04-22 | Kabushiki Kaisha Toshiba | Offset-gate-type semiconductor device |
| US7176520B2 (en) | 2003-09-05 | 2007-02-13 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7432579B2 (en) | 2003-10-09 | 2008-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate |
-
1992
- 1992-09-11 JP JP24295092A patent/JP3216258B2/en not_active Expired - Lifetime
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1187220A2 (en) * | 2000-09-11 | 2002-03-13 | Kabushiki Kaisha Toshiba | MOS field effect transistor with reduced on-resistance |
| US6864533B2 (en) | 2000-09-11 | 2005-03-08 | Kabushiki Kaisha Toshiba | MOS field effect transistor with reduced on-resistance |
| US6552389B2 (en) | 2000-12-14 | 2003-04-22 | Kabushiki Kaisha Toshiba | Offset-gate-type semiconductor device |
| US7026214B2 (en) | 2000-12-14 | 2006-04-11 | Kabushiki Kaisha Toshiba | Offset-gate-type semiconductor device |
| US7061060B2 (en) | 2000-12-14 | 2006-06-13 | Kabushiki Kaisha Toshiba | Offset-gate-type semiconductor device |
| US7176520B2 (en) | 2003-09-05 | 2007-02-13 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same |
| US7791131B2 (en) | 2003-09-05 | 2010-09-07 | Renesas Electronics Corp. | Semiconductor device and a method of manufacturing the same |
| US7994567B2 (en) | 2003-09-05 | 2011-08-09 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same |
| US7432579B2 (en) | 2003-10-09 | 2008-10-07 | Kabushiki Kaisha Toshiba | Semiconductor device with horizontal MOSFET and Schottky barrier diode provided on single substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3216258B2 (en) | 2001-10-09 |
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