JPH0697073A - Formation of polycrystalline silicon layer and polycrystalline silicon thin film transistor using the same - Google Patents

Abstract

PURPOSE:To reduce a defect density in a polycrystalline silicon layer and improve electrical characteristics of a TFT, by thermally treating the polycrystalline silicon layer at a specific temperature after an annealing of a light beam. CONSTITUTION:A passivation film 2 such as silicon oxide is formed on a substrate 1 and further an amorphous silicon thin film 3 is formed on the passivation film 2. Then, a light beam 6 such as continuous oscillation laser light is applied to the amorphous silicon thin film 3, and an annealing of the light beam with a light beam scanning speed of 5000 per sec or longer the product of a beam spot diameter is performed and a polycrystalization is performed without resulting in a complete melting condition. After this, a formed polycrystalline silicon layer 30 is thermally treated at a temperature of 350 to 430 deg.C and a defect density in the polycrystalline silicon layer 30 is reduced. In this case, for example, a continuous oscillation argon ion laser having a high output is used as the light beam 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a polycrystalline silicon semiconductor device such as a polycrystalline silicon thin film transistor used for driving an image display device or the like.

[0002]

2. Description of the Related Art In recent years, thin film transistors (TFTs) have been actively developed for application to image display devices such as flat displays. A polycrystalline silicon TFT having a high operating speed is expected in order to cope with an increase in size and definition of a display and a TFT in a peripheral drive circuit. However, generally, the deposition temperature of the polycrystalline silicon film is 600
There is a problem that it is difficult to increase the area and reduce the cost required for image display devices, which is high at around ℃.

Therefore, a method of forming polycrystalline silicon from amorphous silicon by a low temperature process by laser annealing has been studied. For example, JP-A-60-833
No. 21, or magazine, solid physics: 16 [2] (Showa 56-
As described in 2), pages 47 to 53, etc., single crystallization or polycrystallization by melting recrystallization of silicon is a so-called SOI.
There were many examples of research as technology (Silicon On Insulator).

On the other hand, in the high speed scanning laser annealing method disclosed in Japanese Patent Laid-Open No. 62-104117,
A polycrystalline silicon thin film was formed at a process temperature of 500 ° C. or less, and it became possible to use a low-cost glass substrate which was impossible by the melt recrystallization method.

By this high-speed scanning laser annealing method, an inverted stagger type device structure, which has been difficult to apply by a general laser annealing method, that is, a metal wiring is provided in a lower layer of a silicon film, and the metal wiring is a laser. It has become possible to manufacture a polycrystalline silicon TFT even in the case of an element structure that is affected by temperature rise during annealing.

However, as the size of the liquid crystal display device is further increased, and with the progress of the manufacturing technology of the liquid crystal display device, the area of the glass substrate used for manufacturing the amorphous silicon TFT is further increased. In order to manufacture a high-definition large-sized display element, it is necessary to suppress the dimensional variation at the time of manufacturing in accordance with a minute pixel size, and a technology equivalent to or more than the manufacturing of a general semiconductor integrated circuit is required. It In a high-performance polycrystalline silicon TFT that is being developed to replace the amorphous silicon TFT, the formation of the polycrystalline silicon layer is the key, and the process temperature is required to be further lowered. ing.

Here, the above-mentioned high-speed scanning laser annealing method will be outlined. This method uses continuous wave laser light and irradiates the light beam on the amorphous silicon thin film at high speed. The scanning speed at the time of irradiation becomes possible when the beam spot diameter × 5000 / sec or more.

The condition of the scanning speed will be described with reference to FIGS. 3 to 4 which are the embodiments of the present invention. When laser annealing the amorphous silicon thin film 3 and increasing the laser power from a small value, the amorphous silicon thin film begins to crystallize without obtaining a completely molten state, and a polycrystalline silicon layer is obtained. This is called the first laser power threshold.

It is considered that this is because polycrystallization has begun to occur due to the transient energy impact on the amorphous silicon thin film 3. Polycrystallization can occur almost uniformly in the thickness direction of the amorphous silicon thin film 3. In addition, it is considered that annealing is achieved for each minute region without disturbing the atomic profile.

When the laser power is further increased, the amorphous silicon thin film 3 finally passes through the process of polycrystallization in each minute region and reaches a completely molten state in almost the entire irradiated region. This is called the second laser power threshold. In this case, the amorphous silicon thin film 3 changes its state, shows an aggregated state on the glass substrate 1, and does not have a uniform film shape.

The beam spot diameter of the light beam × 5000 /
By scanning at a high speed of not less than a second, it becomes possible to obtain a sufficient effective width of laser power between the first laser power threshold value and the second laser power threshold value described above, and control of laser annealing can be performed. It will be easier.

In the case of laser annealing at a low speed, when the laser power is small, the translucency is slightly changed and polycrystallization does not occur. In addition, a slight increase in laser power will cause a transition to the molten state at once. For this reason, laser annealing at low speed is only possible with a method of complete melting.

On the other hand, in the high speed scanning laser annealing method, the laser power can be selected between the first laser power threshold value and the second laser power threshold value, and the polycrystallization of the amorphous silicon thin film 3 can be controlled. it can. Specifically, the desired performance is obtained when the scanning speed of the light beam is in the range of the beam spot diameter × tens of thousands / second or more.

In particular, the beam spot diameter × (200000
~ 400,000) / sec, a diagonal speed of 10
Approximately 1 panel with 640 x 400 pixels per inch
It is also possible to perform the annealing treatment within the time within minutes. And
Since such high-speed scanning light beam annealing is used, there is a manufacturing feature in that amorphous silicon is polycrystallized without reaching a completely molten state. Next,
Describe the entire process.

First, a passivation film 2 and an amorphous silicon thin film 3 are formed on a glass substrate at a substrate temperature of 450 ° C., an output light beam of an argon ion laser beam with an output of 13 W is condensed to a diameter of about 50 μm, and the output is about 11 m. The amorphous silicon thin film 3 is scanned and irradiated at a speed of / sec to polycrystallize the amorphous silicon thin film 3.

Further, the formed polycrystalline silicon layer 30
Heat treatment after light beam annealing is performed to improve the film quality (post light beam annealing). Then, a polycrystalline silicon TFT is formed by a normal TFT manufacturing process. Since it is considered that the heat treatment after the light beam annealing is more effective at higher temperatures, it is usually performed under the temperature condition of 450 to 500 ° C. in consideration of the heat resistance of the glass substrate.

[0017]

However, the polycrystalline silicon layer 30 is formed by the above-described high speed scanning light beam annealing method.
However, the defect density of the formed polycrystalline silicon layer 30 did not become sufficiently low even if the heat treatment was performed. Since the defect density is not reduced, there remains a problem in the electrical characteristics of the target device TFT. Further, there is a problem that the step of performing the heat treatment becomes a step requiring the highest temperature even in the TFT manufacturing process, which hinders the temperature reduction of the whole process.

[0018]

According to the present invention, an amorphous silicon thin film formed on an insulating substrate is irradiated with a light beam such as continuous wave laser light, and the scanning speed of the light beam is set to a beam spot diameter x The amorphous silicon thin film is light beam annealed at 5000 / sec or more to form a polycrystalline silicon layer without reaching a completely molten state, and this polycrystalline silicon layer is further heat-treated at a temperature of 350 ° C. or more and 430 ° C. or less. A method for forming a polycrystalline silicon layer is provided.

The following is a polycrystalline silicon T having a coplanar structure.
An example of FT will be described with reference to FIGS.

First, plasma CVD, sputtering, low pressure CVD, atmospheric pressure C on a substrate 1 such as glass or ceramics.
According to VD, etc., silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y : x = 0 to 2, y = 0
~ 1.8), a passivation film 2 (film thickness: 50 to 1000 nm) formed of a single layer or a multilayer film of tantalum oxide or the like.
Was formed. Furthermore, the amorphous silicon thin film 3 (film thickness: 1
0 to 500 nm) was formed at a film forming temperature of 300 ° C.

In order to control the threshold voltage of the TFT as necessary, impurities such as boron (B) or phosphorus (P) in the amorphous silicon thin film 3 are made uniform in the film thickness direction by about tens to hundreds of ppm. Alternatively, it was contained non-uniformly.

Then, the amorphous silicon thin film 3 was annealed by a light beam by the above-described high speed scanning laser annealing method, so that the amorphous silicon thin film 3 was polycrystallized without reaching a completely molten state. A high power continuous wave argon ion laser was used for the light beam 6.

After the completion of the light beam annealing, heat treatment was performed to reduce the defect density in the formed polycrystalline silicon layer 30. FIG. 1 shows the relationship between the defect density (unit on the vertical axis is [× 10 ¹⁷ / cm ³ ]) in the polycrystalline silicon layer 30 measured by the electron spin resonance method and the heat treatment temperature. When the heat treatment temperature was 400 ° C., the defect density was close to 0, and at 500 ° C., a value of 4.2 × 10 ¹⁷ defects / cm ³ was obtained. 350 ° C or more 430 centered at 400 ° C
The defect density was low in the range of ℃ or below, and the effect of heat treatment was the largest.

Generally, a polycrystalline silicon film formed by low pressure CVD without using the laser annealing method has 6
It is known that heat treatment at around 00 ° C. improves the film quality. It is said that this film quality improvement does not occur at 550 ° C. or lower.

Therefore, it is considered that the reduction of the defect density in the polycrystalline silicon layer by the heat treatment in the manufacturing method of the present invention is due to a mechanism different from the conventionally known heat treatment at 600 ° C. That is, it is considered to be peculiar to the polycrystalline silicon layer 30 formed by the high speed scanning laser annealing method. Further, the characteristic curve of FIG. 1 is a universal characteristic of the polycrystalline silicon layer 30 which has been subjected to the high speed scanning light beam annealing and subjected to the heat treatment. It was found that it did not depend on the film apparatus, film forming conditions, heat treatment conditions, and the like.

Further, the polycrystalline silicon layer 30 is patterned by photolithography, and the plasma C is formed on the polycrystalline silicon layer 30.
A gate insulating film 4 (film thickness: 100 to 500 nm) consisting of a single layer or a multilayer film of silicon oxide, silicon nitride, silicon oxynitride, tantalum oxide, etc. is formed by VD, sputtering, low pressure CVD, atmospheric pressure CVD, etc.
Furthermore, chromium is deposited by vacuum deposition, sputtering, etc.
The gate electrode 5 made of a single layer or a multilayer film of tantalum, aluminum or the like was formed.

Further, the gate electrode 5 is formed by the ion implantation method.
Using as a mask, the respective regions of the polycrystalline silicon layer 30 serving as the source 31 and the drain 32 of the TFT were doped with impurity ions such as phosphorus (P), boron (B), and arsenic (As). After heat treatment for activating the impurity ions as necessary, an interlayer insulating film 8 is deposited, contact holes are formed on the respective regions of the source 31 and the drain 32, and the contact holes are formed on the source 31 or the drain 32. The electrode layer 9 to be connected was formed (FIG. 4).

The heat treatment for reducing the defect density in the polycrystalline silicon layer 30 described above can be performed as a single process, and may be combined with a process such as sintering for activating impurity ions. It is also possible to perform the film forming step for the gate insulating film 4 and the interlayer insulating film 8 as well.

The case of the coplanar type polycrystalline silicon TFT has been described above as an example. However, the structure of the TFT may be a TFT of other structure such as an inverted stagger type or a stagger type, and other types such as a solar cell. It can also be applied to crystalline silicon devices.

[0030]

【Example】

(Example 1) Example 1 of the present invention will be described. In this embodiment, the heat treatment of the present invention is carried out immediately after the high speed scanning laser annealing, and the subsequent steps are carried out as usual. A 200 nm thick silicon oxide passivation film 2 is formed on a glass substrate 1 (Corning 7059) by a plasma CVD method, and a 100 nm thick amorphous silicon thin film 3 is formed thereon at a substrate temperature of 300 ° C. Heat treated for 30 minutes.

On the amorphous silicon thin film 3, a light beam of an argon ion laser with an output of 13 W was condensed and irradiated at a diameter of about 50 μm. This light beam was scanned and irradiated at a speed of about 11 m / sec (beam spot diameter × scanning speed of 220,000) to polycrystallize the amorphous silicon thin film 3. Then, heat treatment was performed at 400 ° C. for 1 hour.

Further, the polycrystalline silicon layer 30 is patterned into an island shape by photolithography, and a gate insulating film 4 made of silicon nitride having a thickness of 200 nm is deposited thereon at 300 ° C. by a plasma CVD method. Chromium with a thickness of 150 nm as the material of No. 5 was vapor-deposited at 300 ° C. by an electron beam heating vapor deposition method.

Then, the gate electrode 5 was patterned by photolithography. After the gate insulating film 4 is further etched, by using the gate electrode 5 as a mask by the ion implantation method, among the island portions of the polycrystalline silicon layer 30,
Phosphorus (P) ions are applied to the source or drain region of the TFT at an acceleration voltage of 10 kV and a dose of 2 × 10 ^15.
Doping was carried out under the condition of individual pieces / cm ² .

A heat treatment for activating the impurity ions is performed 30 times.
After 1 hour at 0 ° C., the interlayer insulating film 8 and the transparent conductor film 1
1 was deposited, the transparent conductor film 11 was patterned into the shape of a display electrode, a contact hole was formed on the source or drain region, and an electrode layer 9 connected to the source or drain was formed thereon.

(Second Embodiment) Next, a second embodiment will be described. In this embodiment, the film forming temperature of the gate insulating film 4 and the activation annealing temperature of the impurity ions are set to appropriate temperatures for the heat treatment of the present invention, thereby omitting a single heat treatment step immediately after laser annealing.

A 200 nm thick silicon oxide passivation film 2 and a 100 nm thick amorphous silicon thin film 3 are formed on a glass substrate (Corning 7059) 1 by plasma CVD at a substrate temperature of 300 ° C. and at 350 ° C.
Heat treated for minutes. A light beam of an argon ion laser with an output of 13 W is condensed to a diameter of about 50 μm, and scanning irradiation is performed on the amorphous silicon layer 3 at a speed of about 11 m / second (beam spot diameter × 220,000 / second scanning speed). The amorphous silicon thin film 3 was polycrystallized.

The polycrystalline silicon layer 30 is patterned into an island shape by photolithography, and a plasma CV is formed thereon.
A gate insulating film 4 made of silicon nitride having a thickness of 200 nm was deposited by the method D at 350 ° C., and chromium having a thickness of 150 nm as a material for the gate electrode 5 was vapor-deposited at a temperature of 300 ° C. by an electron beam heating vapor deposition method.

Then, a pattern of the gate electrode 5 was formed by photolithography. Furthermore, the gate insulating film 4
After etching, the gate electrode 5 is formed by the ion implantation method.
Is used as a mask, and phosphorus (P) ions are applied at an accelerating voltage of 1
Doping was performed under the conditions of 0 kV and a dose amount of 2 × 10 ¹⁵ pieces / cm ² .

Further, after heat treatment for activating the impurity ions is performed at 350 ° C. for 1 hour, the interlayer insulating film 8 is deposited,
Contact holes were formed on the regions of the source 31 and the drain 32, and the electrode layer 9 connected to the source 31 or the drain 32 was formed thereon.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. Example 3 is an inverted stagger type polycrystalline silicon TFT formed at a process maximum temperature of 300 ° C. because aluminum is used as a gate electrode material.

Aluminum having a thickness of 50 nm is formed on the glass substrate 1.
With a thickness of 1 nm by electron beam heating vapor deposition method, a pattern of the gate electrode 5 is formed by photolithography, and silicon nitride SiN _x (x
= 1.1 to 1.6) A gate insulating film 4 having a thickness of 200 nm and an amorphous silicon thin film 3 having a thickness of 100 nm are stacked at a film forming temperature of 200 ° C., and silicon nitride SiN _{x is} further formed.
(X = 1.2 to 1.6) Antireflection film 1 made of 50 nm
0 was formed at a film forming temperature of 300 ° C. to form an amorphous silicon thin film 3
It also served as a heat treatment after the film formation.

About 10 W of argon ion laser light was used.
The light was focused to a diameter of 0 μm, and scanning irradiation was performed at a speed of about 13 m / sec (beam spot diameter × 260000 / sec). The amorphous silicon thin film 3 was polycrystallized. Thus, the polycrystalline silicon layer 30 was formed (FIG. 5).

After removing the antireflection film 10, a positive photoresist (OFPR-800 manufactured by Tokyo Ohka Co., Ltd.) is applied,
By exposing and developing from the back surface of the substrate, a photoresist layer having the same pattern as the gate electrode 5 was formed in a self-aligned manner. By using the photoresist layer pattern as a mask, phosphorus (P) ions are accelerated by an ion implantation method to the portions that will be the source and drain regions of the polycrystalline silicon layer 30.
Doping was performed under the conditions of kV and a dose amount of 2 × 10 ¹⁵ pieces / cm ² .

After removing the photoresist layer by oxygen plasma, a heat treatment for activating impurity ions is performed for 30 minutes.
It was carried out at 0 ° C. for 1 hour. The polycrystalline silicon layer 30 is patterned into an island shape by photolithography, and silicon oxynitride is deposited thereon by plasma CVD.
Formed to a thickness of 00 nm, an interlayer insulating film 8 is deposited, and a contact hole is formed on the source or drain region,
The electrode 9 was formed on it (FIG. 6).

FIG. 2 is a characteristic curve of leakage current-drain voltage of a polycrystalline silicon TFT manufactured by using the method for forming a polycrystalline silicon thin film of the present invention and a TFT manufactured by a conventional method.

Curve A is the leak current of the TFT by the conventional example (heat treatment at 450 ° C.). Curve B represents the present invention (40
It is the leak current of the TFT due to the heat treatment at 0 ° C.). Three
The TFT formed by the heat treatment at 50 ° C. also showed the same characteristics as the curve B. It can be seen that in the TFT of the present invention, the leak current is greatly reduced as compared with the conventional example. It was also confirmed that the on-current and threshold characteristics of the TFT are improved.

International Conference on Display Technology SID '91 (Soc
yety for Information Disp
Lay) 's digest (pages 663-666) shows that the heat shrinkage of Corning 7059 glass, which is most commonly used in liquid crystal display manufacturing, is 1 hour after treatment.
It is 3 ppm at 300 ° C., 6 ppm at 350 ° C., 15 ppm at 400 ° C., and 40 ppm at 450 ° C.

For example, on a glass substrate having a side length of 300 mm, a shrinkage of 10 ppm causes a pattern shift of 3 μm. In manufacturing liquid crystal display elements,
Although it depends on the size of the substrate used and the design rules, the effect of lowering the process temperature is extremely large.

[0049]

According to the method of the present invention, the heat treatment temperature after the light beam annealing, which was the highest temperature in the conventional manufacturing process, can be lowered, so that the driving circuit of the image display device using the high speed TFT can be formed. It has become possible to achieve lower temperatures in the entire manufacturing process.

That is, the temperature required in the manufacturing process is lowered, and an expensive high temperature furnace is not required. Also,
It is possible to manufacture at a relatively low temperature as compared with the conventional manufacturing method. It was found that the quality of the polycrystalline silicon layer formed by the high speed scanning laser annealing method was improved. In addition, temperature control becomes easier and the yield of TFT manufacturing is improved.

Further, variations in characteristics between manufacturing lots have also been reduced. Further, the throughput in all steps is shortened, and, for example, a high-performance liquid crystal panel driving circuit can be manufactured in a short cycle.

[Brief description of drawings]

FIG. 1 is a graph showing a relationship between a defect density in a polycrystalline silicon layer measured by an electron spin resonance method and a heat treatment temperature.

FIG. 2 is a graph showing leakage current-drain voltage characteristics of a polycrystalline silicon TFT of the present invention and a conventional example.

FIG. 3 is a schematic view showing a state in which an amorphous silicon thin film 3 is irradiated with a light beam 6 to be polycrystallized.

FIG. 4 is a partial cross-sectional view of a coplanar TFT of Example 2.

FIG. 5 is a cross-sectional view in the process of manufacturing an inverted stagger type TFT of Example 3.

FIG. 6 is a cross-sectional view of an inverted stagger type TFT of Example 3.

[Explanation of symbols]

 1: Substrate 2: Passivation film 3: Amorphous silicon thin film 4: Gate insulating film 5: Gate electrode 6: Light beam 11: Transparent conductor film 30: Polycrystalline silicon layer

Claims (2)

[Claims] 1. An amorphous silicon thin film formed on an insulating substrate is irradiated with a light beam such as continuous wave laser light, and the scanning speed of the light beam is beam spot diameter × 50.
The amorphous silicon thin film is annealed with a light beam at a rate of 00 / sec or more to form a polycrystalline silicon layer without reaching a completely molten state.
A method for forming a polycrystalline silicon layer, which comprises performing heat treatment at a temperature of 0 ° C. or higher and 430 ° C. or lower. 2. A polycrystalline silicon thin film transistor formed by using the polycrystalline silicon layer formed by the method of claim 1.