JPH0694804A - Ic testing device - Google Patents

Abstract

PURPOSE:To provide an IC testing device which is so structured that a plurality of control units are connected between a bus driver and bus receiver of a control part via a control buns and which can perform self-diagnosis of the interrupt signal processing line of the control part even in the condition that no control unit is connected with the control part. CONSTITUTION:An interruption signal generator 18 is furnished in a control part 10, and an interrupt signal for self-diagnosis is generated from the interrupt signal generator 18 when a self-diagnostic program is executed. This interrupt signal is fed to a control bus 30 via a bus driver 16, and thereby it is possible to make self-diagnosis of the interruption signal processing line even in the condition that the control part 10 remains in single state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic configuration of a conventional IC test apparatus. In the figure, 10 indicates a control unit. The control unit 10 is generally composed of a computer. As is well known, the computer has a central processing unit 11 called a CPU, a ROM 12, a RAM 13, an input port 14,
It is composed of the output port 15 and the like. A bus driver 16 is provided on the output side of the output port 15. A control signal is applied to the control bus 30 by the bus driver 16.
Control units 20A to 20N are connected in series to the control bus 30. The control units 20A to 20N constitute an IC test apparatus, for example, a pattern generator, a timing generator,
Refers to units such as waveform formatters and pin electronics. The control units 20A to 20N are connected to the control units 20A to 20N from the control unit 10 through the bus driver 16.
At a timing assigned to 0N, a control signal such as an initial setting value is transferred and given to operate as an IC test apparatus. Further, the data sent from each of the units 20A to 20N to the control unit 10 is sent to the control unit 10 at the timing assigned to each of the control units 20A to 20N, and the bus receiver 1
7 is taken into the control unit 10 through the input port.

An interrupt signal generator 21 is provided in each of the control units 20A to 20N. The interrupt signal generator 21 urgently controls the control unit 1 in each of the control units 20A to 20N.
When it is desired to transmit data to 0, an interrupt signal is generated, and the control unit permitted by the interrupt signal transmits the data to the control unit 10.

[0004]

In the conventional IC test apparatus, the interrupt signal generator 21 is provided in each of the control units 20A to 20N.
However, it is not provided in the control unit 10.
Therefore, since the control unit 10 cannot generate an interrupt signal in a stand-alone state, there is a problem that it is not possible to self-diagnose whether or not to respond correctly to an interrupt signal.

[0005]

According to the present invention, an interrupt signal generator is provided in the control unit of the IC test apparatus, and the control unit can also send an interrupt signal. Therefore, according to the present invention, it is possible to generate an interrupt signal from itself by activating the self-diagnosis program even in the state of the control unit alone. Therefore, if a dummy bus line is connected between the bus driver and the bus receiver. It is possible to output an interrupt signal from the bus driver and have the bus receiver receive the interrupt signal from the bus driver via the interrupt signal line on the bus line. Therefore, by receiving this interrupt signal, it is possible to cause the control unit to execute the operation of the interrupt signal processing system and perform self-diagnosis as to whether or not the operation is normal.

Further, even when the control unit is connected, the control unit 10 can generate an interrupt signal at an arbitrary time. Therefore, it is possible to easily self-diagnose disconnection of the interrupt signal line of the bus line.

[0007]

FIG. 1 shows an embodiment of the present invention. According to the present invention, an interrupt signal generator 18 is provided between the output port 15 and the bus driver 16 which constitute the control unit 10, and the self-diagnosis program is activated, so that the interrupt signal generator 18 is provided at a key point of the self-diagnosis program. An interrupt signal generation command gives an interrupt command signal to the interrupt signal generator 18 through the output port 15. The interrupt signal generator 18 outputs an interrupt signal to the bus driver 16 by receiving the interrupt command signal,
An interrupt signal is sent to the interrupt signal line of the control bus 30.

FIG. 2 shows the configuration of the interrupt signal generator 18.
The interrupt signal generator 18 is, for example, a control code register 18A.
, Decoder 18B, retiming register 18C,
It can be configured by an SR flip-flop 18D that constitutes an interrupt signal generation register. These control code register 18A, decoder 18B, retiming register 18C, and SR flip-flop 18D are provided in N sets corresponding to the number of control units 20A to 20N, and are configured to generate an N-bit interrupt signal. To be done.

The decoder 18B is a control code register 18
The code signal set to A is converted into a control signal for generating and stopping an interrupt signal. That is, the control code register 18A
When the interrupt command signal is set to, the decoder 18B outputs H logic, and this H logic signal is output to the retiming register 1
Read in 8C. H for retiming register 18C
When the logic is read, the SR flip-flop 18D is set to generate an H logic interrupt signal. When the retiming register 18C reads the L logic, the SR flip-flop 18D is reset and the generation of the interrupt signal is stopped.

[0010]

As described above, according to the present invention, the control unit 10 can independently generate an interrupt signal.
Therefore, by connecting a dummy control bus between the bus driver 16 and the bus receiver 17, the control units 20A-2
Even if 0N is not connected, the interrupt processing function of the control unit 10 can be self-diagnosed.

Even when the control units 20A to 20N are properly connected, the interrupt signal can be generated from the interrupt generator 21 provided in each of the control units 20A to 20N, and also from the control unit 10. It is possible to generate an embedded signal. Therefore, from the control unit 10 to each control unit 20A
By generating an interrupt signal corresponding to ~ 20N,
All loops of the interrupt signal line of the control bus 30 (bus driver 1
It is possible to diagnose the presence / absence of a disconnection between 6 and the bus receiver 17.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a connection diagram specifically showing a configuration of a main part of the present invention.

FIG. 3 is a block diagram for explaining a conventional technique.

[Explanation of symbols]

 10 Control Unit 11 Central Processing Unit 12 ROM 13 RAM 14 Input Port 15 Output Port 16 Bus Driver 17 Bus Receiver 18 Interrupt Signal Generator 20A-20N Control Unit 21 Interrupt Signal Generator 30 Control Bus

Claims (1)

[Claims] 1. A control unit includes a bus driver and a bus receiver, and a plurality of control units are connected between the bus driver and the bus receiver of the control unit through a control bus, and the bus driver controls the plurality of controls. In an IC test apparatus that transmits a control signal to each of the units and receives the signal from each control unit through the bus receiver to the control unit so as to receive and transmit the signal, an interrupt signal is generated for the control unit. An IC test apparatus provided with an interrupt signal generator, and configured so that the controller can be self-diagnosed by an interrupt signal output from the interrupt signal generator.