JPH0693627B2 - Variable frequency divider - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a variable frequency divider capable of changing a frequency division number, and more particularly to a variable frequency divider whose internal state preset is variable.

[Conventional technology]

FIG. 1 is a block diagram showing a basic configuration of a conventional programmable variable frequency dividing device, which is a reset type variable frequency dividing circuit 1 capable of changing the frequency dividing number, and a frequency dividing number data generating circuit for generating the frequency dividing number. It consists of two.

In the reset operation of this circuit, as shown in FIG. 2 (a), if the frequency division number n is set in advance, the frequency division operation is started at the frequency division number n immediately after the reset is released. Since this is an example of the operation of the programmable counter, the frequency division output is at the low level only when the count number becomes "3", and the rest is at the high level. It is low level during reset.

As can be seen from the figure, the delay time from the reset release to the actual start of frequency division is within one cycle of the input clock.

However, when the clock is very fast, there is a delay until the release of the reset signal substantially appears in the operation of the variable frequency divider circuit. Therefore, as shown in FIG. The delay time until the actual frequency division start time may extend over one cycle of the input clock.

This is because when the frequency division of a high frequency clock is started in synchronization with the reference signal as shown in FIG. 3 and a frequency division signal whose phase is synchronized with the reference signal is produced, the delay time is directly synchronized. There will be an error.

As described above, there is a method of using a frequency divider with a preset function when it is desired to synchronize and output the phase of the variable frequency dividing circuit. The preset is a function capable of arbitrarily setting the internal state when starting frequency division.

FIG. 4 is a diagram for explaining the preset function using the preset counter as an example.

In the figure, (a) shows a case with a reset function, and the frequency division output is a low level during reset and a 50% duty pulse after reset is released.

In addition, (b) is the case of the preset function, for example, when preset to "1", when preset is on, the divided output is at a high level corresponding to "1", and clocks are counted sequentially from there. And count as shown.

As shown in FIG. 4, when presetting is canceled and frequency division is started, if the internal state is preset by shifting the internal state by the number of input clocks corresponding to the delay, an error within one cycle of the input clock is added to the reference signal. It is possible to obtain the frequency division output synchronized with.

FIG. 5 is a block diagram showing the basic configuration of a conventional pulse swallow-type variable frequency divider circuit.
Variable frequency divider circuit 3 with a built-in frequency division number P and (P + 1)
It is composed of a prescaler 4 that can be switched to and a frequency division number data generation circuit 2. The variable frequency dividing circuit 3
Causes the counter A and the counter B to simultaneously count the output pulses of the prescaler. At this time, the frequency division number of the prescaler is set to P + 1.

Further, the frequency division numbers of the counter A and the counter B are a and b, respectively (b> a). When the counter A counts the output pulses of the prescaler a, the frequency division number of the prescaler is P +
Switching from 1 to P stops the counting operation.

The counter B counts the number of prescaler output pulses by b and outputs the pulses, of which a is P + 1 frequency divisions and (b−a) is P frequency divisions. At this time, the total frequency division number N is represented by N = a (P + 1) + (b−a) P = bP + a.

When the counter B outputs a pulse, each counter and prescaler are reset. At this time, it is reset to the frequency division number (P + 1) of the prescaler. This pulse swallow type variable frequency divider is used in frequency synthesizers of several tens of MHz or more. When the frequency of the input clock is high like this, it is usually 1 /
A fixed divider for high frequency of 4 or 1/8 is installed in front of the variable divider. By doing so, the total number of divisions is 4 or 8.
It becomes a multiple of and it is difficult to perform fine frequency division control. However, as described above, in the pulse swallow method, it is possible to directly divide the high frequency, and also it is possible to change the total number of divisions by one.

Even in the case of such a pulse swallow type variable frequency dividing circuit, it is possible in principle to synchronize the phase of the frequency division output with the reference signal by adding the preset function as described above.

[Problems to be solved by the invention]

The addition of the preset function to the frequency dividing circuit as described above can be easily performed in the conventional fixed frequency dividing circuit, but it is very difficult in the programmable variable frequency dividing circuit and the pulse swallow type variable frequency dividing circuit. Atsuta

That is, in order to add the preset function to the pulse swallow type variable frequency divider, the prescaler preset function is required. However, the addition of a prescaler preset function for high-speed (1 GHz to 3 GHz) frequency division is not preferable because it impedes high-speed operation, low power consumption, etc., and leads to performance degradation.

Further, for the programmable variable frequency divider, since the preset function of the frequency dividing circuit is used in constructing the variable frequency divider, it is not easy to add the preset function.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a variable frequency divider capable of adding a preset function with a simple circuit configuration.

[Means for solving problems]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, the present invention provides a variable frequency dividing device including a frequency dividing number data generating circuit for generating frequency dividing number data and a reset type variable frequency dividing circuit capable of changing the frequency dividing number in response to the frequency dividing number data. In the above, the frequency division number data holding circuit for temporarily holding the frequency division number data, and the control circuit for controlling the trigger signal of the frequency division number data holding circuit and the frequency division number data of the frequency division number data generation circuit First after releasing
The frequency division number data is controlled to be switched between the frequency division operation of the first cycle and the frequency division operation of the second and subsequent cycles.

In the above configuration, the frequency division number data of the frequency division operation of the first cycle can be selected to an arbitrary value, whereby the function equivalent to the preset can be easily realized.

FIG. 6 is a timing chart showing the operation of the variable frequency divider using a preset signal preset to "2", and it can be seen that the frequency divider operates normally at the frequency division ratio of 10 after the second cycle. By properly selecting the preset value, the time until the normal frequency division operation starts can be set appropriately (clock cycle unit).

The present invention realizes such a preset function by changing the frequency division ratio between the first cycle after reset and the subsequent cycles.

The present invention detects the output signal of the variable frequency dividing circuit and resets the frequency division number data, and performs the frequency division operation of the first cycle and the frequency division of the second and subsequent cycles after the reset is released. It is different from the conventional variable frequency divider in two points that the frequency division numbers are not the same in the operation.

〔Example〕

FIG. 7 is a block diagram of the first embodiment of the present invention,
Reference numeral 1 denotes a reset-type variable frequency dividing circuit, 2 denotes a frequency dividing number data generating circuit, 6 denotes temporarily holding the frequency dividing number data output from the frequency dividing number data generating circuit 2, and when the trigger signal is input, A frequency dividing number data holding circuit for sending the frequency dividing number data to the reset type variable frequency dividing circuit 1, and 7 a control circuit.

A timing chart of the preset operation of this embodiment is shown in FIG. In the reset state, the output of the variable frequency dividing circuit 1 is set to high level or low level. In the meantime, the frequency division number n generated in the frequency division number data generating circuit 2 is set in the frequency division number data holding circuit 6, and subsequently a trigger signal is applied to the frequency division number data holding circuit 6 to reset the variable frequency division circuit. Set the frequency division number of 1 to n.

When the reset operation is released and the frequency dividing operation is started, the frequency dividing operation in the first cycle is the n frequency dividing operation. A new frequency division number m is generated in the frequency division number data generation circuit 2 after the reset is released until the internal state of the reset type variable frequency division circuit 1 advances by n. Then, the count operation of the n-th input clock is detected, a trigger signal is applied to the frequency division number data holding circuit 6,
Reset type variable frequency divider 1 within 1 cycle of input clock
Change the frequency division number of to m.

Therefore, after the frequency dividing operation of the second cycle, the frequency dividing operation is performed with the frequency dividing number m.

In the above operation, if n is arbitrarily selected, the cycle of the first frequency division operation can be made variable, and the initial phase when the reset is released can be adjusted with the cycle of the input clock as a unit. The output signal of the variable frequency dividing circuit is equivalent to the preset function considering that the low level state is generally only one cycle of the input clock and the duty ratio does not matter so much.

FIG. 9 is a block diagram of the second embodiment of the present invention.

In the present embodiment, instead of the reset type variable frequency dividing circuit 1 in the first embodiment, a prescaler 4 capable of switching the frequency division number between P and (P + 1), and a counter A.
A pulse swallow-type variable frequency dividing circuit 5 (with a reset function) including a variable frequency dividing circuit 3 incorporating a (frequency dividing number a) and a counter B (frequency dividing number b) is provided. The details of these frequency dividing operations are as described in the above-mentioned "prior art".

The timing chart of the preset operation of the present embodiment
Shown in the figure. When both the prescaler 4 and the variable frequency dividing circuit 3 are reset, the output of the prescaler 4 and the output of the variable frequency dividing circuit 3 are set to high level or low level.
In the meantime, the frequency division number N is set by the frequency division number data generation circuit 2, a trigger signal is subsequently added to the frequency division number data holding circuit 6, and a pulse swallow-type variable frequency division circuit including a prescaler 4 and a variable frequency division circuit 3 is set. The frequency division number of 5 is set to N, and the frequency division number of the prescaler 4 is set to (P + 1).

Specifically, the counter A in the variable frequency dividing circuit 3 is for changing the frequency dividing number of the prescaler and does not contribute to the total frequency dividing number. When receiving the data N, the frequency dividing circuit 5 has a function of appropriately setting the frequency dividing numbers of the prescaler 4 and the counter B so that the frequency dividing number becomes N. Therefore, the frequency division number data holding circuit 6 may be exactly the same as that used in the first embodiment.

When the reset operation is released and the frequency dividing operation is started, the pulse swallow-type variable frequency dividing circuit 5 causes the prescaler 4 to move during the frequency dividing operation.
While changing the frequency division number of (P + 1) from P, N input clocks are counted and the frequency division operation of the first cycle is performed.
At this time, the counter B of the variable frequency dividing circuit 3 is operated by the prescaler 4
B output pulses are counted. However, N = bP + a
Is.

In the frequency division operation, a new frequency division number M is generated in the frequency division number data generation circuit 2 after the reset is released until the variable frequency division circuit 3 counts b output pulses of the prescaler 4. Subsequently, the variable frequency dividing circuit 3 detects that the output pulse of the prescaler 4 has been counted b times, and a trigger signal is applied to the frequency division number data holding circuit 6 so that the pulse swallow type pulse is generated within one cycle of the output pulse of the prescaler 4. The frequency division number of the variable frequency dividing circuit 5 is changed to M. From the frequency dividing operation of the second cycle of the pulse swallow type frequency dividing circuit 5, the frequency dividing operation is performed with the frequency dividing number M.

In the above operation, it is possible to change the cycle of the first frequency-dividing operation of the pulse swallow-type variable frequency dividing circuit 5 by selecting N to an arbitrary value, and the initial period when the reset is released. The phase can be adjusted in units of the cycle of the input clock of the prescaler 4.

In the first embodiment, the setting margin time is within one cycle of the input clock until the frequency dividing number of the reset type variable frequency dividing circuit 1 is changed to m by using the output of the frequency dividing operation of the first cycle as a trigger. However, in this embodiment, the setting margin time before changing the frequency division number of the pulse swallow frequency divider circuit 5 to M is triggered by the frequency division output of the first cycle of the pulse swallow frequency divider circuit 5 as a trigger. One cycle of the input clock of the variable frequency dividing circuit 3, that is, (P + 1) times the input clock of the prescaler 4.

Therefore, if the input clocks are the same in the first embodiment and this embodiment, the margin time for setting the frequency division number is (P + 1) times in this embodiment.

As described above, also in this embodiment, since the cycle of the first frequency division operation can be freely changed in units of clock cycle, the same effect as the preset function can be obtained.

〔The invention's effect〕

According to the present invention, a preset function can be added to the variable frequency dividing device by a simple control in which the frequency dividing number is switched when the frequency dividing is started.

The preset function determines the initial phase of the output pulse of the variable frequency divider when releasing the reset, and the initial phase can be set in the unit of the cycle of the input clock. Therefore, when the frequency of the input clock is high and the cycle is short, the phase of the output pulse can be finely advanced or delayed, and in particular, the delay of the reset release signal that has passed through several stages of the gate circuit can be adjusted by the preset function described above. Can be offset by.

An example of the effect obtained by using the second embodiment will be shown below.

FIG. 11 is a block diagram showing a phase periodic loop (PLL).

This PLL comprises a control circuit 7 ', a voltage controlled oscillator 8, a prescaler 9, a reset type variable frequency dividing circuit 10, a phase comparator 11,
It is composed of a reference oscillator 12 and a loop filter 13.

The output signal of the voltage controlled oscillator 8 is frequency-divided by the prescaler 9 and the reset type variable frequency dividing circuit 10 and the phase of the output signal of the reference oscillator 12 is compared, and the voltage corresponding to the phase difference is loop filtered. It is fed back to the control terminal of the voltage controlled oscillator 8 through 13.

The PLL operates so that the phase difference becomes zero, and in the stable operation state, the oscillation output of the voltage controlled oscillator 8 having the same degree of stability as the reference oscillator 12 is obtained. By the way, if you want to operate the PLL intermittently to reduce power consumption, turn on the switch between the PLL loop filter and the phase comparator to
Use by opening and closing the loop.

That is, the voltage controlled oscillator 8 is continuously operated and other PL
This is a method of reducing power consumption by repeatedly turning ON / OFF the power supply of the L circuit and operating intermittently. When the power is turned off, the switch is opened so that the control voltage of the voltage controlled oscillator 8 does not leak. When the switches are closed again to form a loop, the two input signals to the phase comparator generally do not have the same phase, so that there is a disadvantage that the convergence time until the stable operation of the PLL loop becomes long. To improve this,
A method of presetting the prescaler and the variable frequency divider circuit with the output signal of the reference oscillator 12 immediately before closing the loop and matching the phases and then closing the loop can be considered.

However, until the prescaler and the variable frequency divider are reset by detecting the output signal of the reference oscillator 12, a delay (generally several tens of nanoseconds) is caused by the gate circuit. In such a case, if the present invention is applied, the initial phase of the output of the prescaler and the variable frequency divider circuit can be adjusted in the unit of the cycle of the input clock, so that the above delay can be canceled without using the delay line of the analog circuit. it can.

For example, if the frequency of the voltage controlled oscillator is 1 GHz, the delay amount can be adjusted every 1 nsec (= 1/1 GHz).

Since the present invention can be configured with all digital ICs, it can be easily integrated into an IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of a conventional programmable variable frequency divider, FIG. 2 is a timing chart at the time of reset operation of a conventional reset type variable frequency divider, and FIG. 3 is a conventional reset type variable frequency divider. FIG. 4 is a timing chart explaining a synchronization error in the case of a device, FIG. 4 is a timing chart explaining a preset function, FIG. 5 is a block diagram showing a basic configuration of a conventional pulse swallow type variable frequency dividing circuit, and FIG.
FIG. 7 is a timing chart for explaining the preset operation of the present invention, FIG. 7 is a block diagram showing the configuration of the first embodiment of the present invention, and FIG. 8 is a timing chart for explaining the preset operation of the first embodiment. FIG. 9 is a block diagram showing the configuration of the second embodiment of the present invention, FIG. 10 is a timing chart explaining the preset operation of the second embodiment, and FIG. 11 is a block diagram showing a phase locked loop. . 1 ... Reset type variable frequency divider circuit, 2 ... Frequency division number data generation circuit, 3,10 ... Variable frequency divider circuit with built-in counter A and counter B, 4, 9 ... Prescaler, 5 ... Pulse swallow Type variable frequency dividing circuit, 6 ... Frequency dividing number data holding circuit, 7,
7 '... control circuit, 8 ... voltage controlled oscillator, 11 ... phase comparator, 12 ... reference oscillator, 13 ... loop filter

Claims (1)

[Claims] 1. A variable frequency division device comprising a frequency division number data generation circuit for generating frequency division number data and a reset type variable frequency division circuit capable of changing the frequency division number in response to the frequency division number data. , A frequency division number for temporarily holding frequency division number data between the frequency division number data generation circuit and the reset type variable frequency division circuit and sending the frequency division number data to the reset type variable frequency division circuit by a trigger signal. A data holding circuit is provided, and when the reset type variable frequency dividing circuit is in a reset state, the frequency dividing number data n is set in the variable frequency dividing circuit through the frequency dividing number data holding circuit,
After releasing the reset state and before counting the nth input clock in the frequency dividing operation of the first cycle,
New frequency division number data m is set in the frequency division number data holding circuit from the frequency division number data generation circuit, a count operation of the nth input clock is detected, and a trigger signal is applied to the frequency division number data holding circuit. The frequency dividing number of the reset type variable frequency dividing circuit is changed to m, and the frequency dividing operation is performed at the frequency dividing number m after the second frequency dividing operation. apparatus.