JPH0693228B2 - Information processing equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus capable of realizing a virtual computer, and more specifically, a simulation process for an operation request relating to a real resource requested by the virtual computer. The present invention relates to an information processing apparatus having a virtual computer support function that enables high-speed execution.

[Conventional technology]

The virtual computer is a technology that makes it possible to virtually realize a plurality of computer systems on a single computer system. By using this, in one computer system, multiple virtual computers are realized under the control program (hereinafter referred to as “parent OS”) that runs on the parent computer, and each virtual computer runs on each virtual computer. Operating system (hereinafter referred to as "child OS") can be run.
The virtual machine system is designed to operate as a child OS under the parent OS without making any changes to the existing OS. To achieve this, for example, the following method Has been taken.

That is, among the instructions realized on the virtual machine, the instructions for directly instructing the resources on the real machine to operate (for example, input / output instructions, hardware register control instructions, etc.) are among the privileged instructions. By utilizing the fact that it is limited to, the interrupt is generated to the parent OS when the privileged instruction is executed on the virtual machine. This allows
Parsing a privileged instruction issued by the parent OS on the parent computer, performing a simulated operation on the parent OS that should have been performed by this privileged instruction, and reflecting the result on the child OS on the virtual computer. This makes the virtual machine look like it has executed a privileged instruction on itself.

[Problems to be solved by the invention]

Conventionally, virtual computers have been used more and more in general-purpose large-scale computers, but in systems using microprocessors, the needs for multi-OS and the like are increasing, and virtual computers are being required. In some cases, the microprocessor uses a method of reading and writing data to and from memory (hereafter called memory-mapped input / output). The difference is that it is executed as a read and write to memory instead of just. Therefore, in a computer that employs memory-mapped I / O, when a read / write request is made to the memory of the child OS, if the requested address is for the port address of the I / O device, a means to generate an interrupt to the parent OS is provided. Must have

The problem here is that some of the input / output devices are exclusively used by only a specific virtual computer. For example, it is conceivable that a large-capacity hard disk is shared by a plurality of virtual machines and a relatively small-capacity floppy disk device is exclusively used by a specific virtual machine.
In this case, input / output from the virtual machine to the shared hard disk device causes an interrupt to the parent OS, and it is necessary to simulate on the parent OS. On the other hand, the parent OS may simulate the input / output to / from the floppy disk device exclusively occupied by a specific virtual computer, but this is not always necessary, and the exclusive virtual computer may directly perform the input / output.

Rather, simulating the input / output of a virtual machine on the parent OS leads to an increase in processing time compared to the case where the virtual machine directly inputs / outputs, so it is desirable for the virtual machine to directly input / output. It is considered.

[Means for solving problems]

According to the present invention, the first means for determining whether a read / write operation to an arbitrary memory address corresponds to input / output, and the virtual computer can directly read / write to / from a memory address to be input / output to / from a certain device. A second means for determining whether or not the virtual computer directly handles input / output to / from a device that the virtual computer is allowed to input / output. And a fourth means for notifying the parent computer of input / output to / from a device that is not permitted, wherein the first means is a logical address tag, a physical page address holding unit, and whether the physical page is an input / output space. It has an entry composed of a flag indicating whether to output an instruction signal for an input logical address, which indicates whether the corresponding physical page number and an I / O port is included in the physical page. The second means comprises a plurality of entries for storing input / output port logical addresses that can be directly input / output by the virtual computer, and the input / output ports that can directly input / output the input logical addresses with respect to the output logical addresses. The fourth means is an input / output port capable of directly inputting the instruction signal from the first means and the logical address output from the second means. And a determination result of whether or not to interrupt the parent computer, the third means, the physical address corresponding to the logical address output of the first means and , The output of the fourth means is determined as to whether or not an interrupt is to be performed, as an input signal, and it is determined whether to perform memory access or access to an input / output port, thereby performing virtual calculation. Wherein the input and output direct virtual machine executes to perform a read or write to the memory of the above.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, the address conversion unit 1 corresponding to the first means is a device for converting a logical address signal 5 to be accessed by a virtual computer into a physical address signal 6. In the present embodiment, the applied logical address signal 5 is the port address of the input / output device or the port address of the input / output device.
Address space containing addresses (hereinafter called input / output space)
Then, the port / space discrimination signal 7 which is determined whether or not is output.

The direct input / output determination unit 2 corresponding to the second means checks whether the logical address signal 5 which a virtual computer is trying to access is the port address of a device which the virtual computer is allowed to directly input / output. The determined direct input / output enable / disable signal 8 is output.

The memory access control unit 3 corresponding to the third means actually reads / writes a memory and reads / writes to / from an input / output port with respect to a physical address, and outputs a memory access signal 10 for that purpose.

In the interrupt determination unit 4 corresponding to the fourth means, the parent OS is notified from the port / space determination signal 7 indicating the address to the input / output port and the direct input / output enable / disable signal 8 indicating whether direct input / output is possible. An interrupt signal 9 for deciding whether to generate an interrupt is output. Further, the logical address signal 5 represents a logical address that the virtual computer is trying to access, and a virtual computer identifier for uniquely identifying each virtual computer may be added.

FIG. 2 is an explanatory diagram of the address conversion unit 1 of the embodiment shown in FIG. 1, and like the associative memory and high-speed address conversion mechanism, the address tag unit 11 and the physical page address holding unit 12 are shown.
And a flag holding part that indicates whether it is an input / output page space
Composed of 13. The entry number selection signal 14 transmits the entry number hit in the address tag section 11 to the physical page address holding section 12 and the flag holding section 13 indicating whether it is an input / output page space, selects an output entry, and selects the logical address signal 6 and the port. The space discriminating signal 7 is output.

FIG. 3 is an explanatory diagram of the direct input / output determination unit 2 of the embodiment shown in FIG. 1, in which a gate 15 for taking a physical sum and a plurality of entries 16 for holding port addresses of input / output devices capable of direct input / output are provided. And a plurality of comparators 17 and entry selection line write signals 18 and 19 for rewriting the port address of the input / output device that can directly input / output. As for the logical address signal 5, a direct input enable / disable signal 8 indicating that the output is hit is obtained when the matching address is registered in a plurality of entries in response to the access of the virtual computer.

Next, the operation of this embodiment will be described with reference to FIG.

First, a logical address signal 5 indicating a logical address for which an access request has been issued on a virtual computer
Entered in. The address translation unit 1 translates the input logical address into physical addresses in page units and outputs a physical address signal 6, and similarly determines whether the logical addresses input in page units are input / output spaces. The port / space discrimination signal 7 is output. On the other hand, the logical address signal 5 for which an access request has been issued on the virtual computer is also input to the direct input / output determination unit 2 and is compared and matched with the direct input / output enabled port address registered in the direct input / output determination unit 2. A direct input / output enable / disable signal 8 indicating the presence / absence of entry select line interrupt signals 18 and 19 is output.

Next, the interrupt determination unit 4 receives the port / space determination signal 7 from the address conversion unit 1 and the direct input / output enable / disable signal 8 from the direct input / output determination unit 2, determines whether or not to interrupt the parent OS, and interrupts. Generate signal 9. It is determined that the parent OS should be interrupted, the logical address for which an access request is made on the virtual computer is the I / O space (identified from the port / space discrimination signal 7) and is not a directly I / Oable address. This is the case (clear from the direct input / output enable / disable signal 8). On the other hand, the interrupt to the parent OS is suppressed even though it is an I / O space, because the logical address for which an access request was made on the virtual machine is the I / O space (identified from the port / space discrimination signal 7) and directly This is the case when the address is an input / output enable address (obtained from the direct input / output enable / disable signal 8).

Other combinations of signals may indicate that the port / space discrimination signal 7 is not an input / output space and that the direct input / output enable / disable signal 8 is not a direct input / output enable address (simple memory reference). In addition, port / space discrimination signal 7
Is not an input / output space, and the direct input / output enable / disable signal 8 is not a direct input / output enable address (meaningless exception event). In these cases, the parent
The OS does not generate interrupts to simulate I / O.

Finally, the output (interrupt signal 9) of the interrupt determination unit is sent to the unit for controlling memory access and the interrupt acceptance portion. The memory access controller actually reads / writes the memory and reads / writes to the input / output port / address unless it receives an interrupt.

〔The invention's effect〕

As described above, the present invention provides a first means for determining whether a read / write operation to an arbitrary memory address corresponds to input / output, and a direct virtual computer for reading / writing to / from a memory address to be input / output to / from a certain device. The second means for determining whether or not the virtual machine can perform, the third means for the virtual machine to handle the input / output to / from the device that the virtual machine is allowed to directly input / output, and the direct virtual machine Since it has a fourth means for notifying the parent computer of the input / output to / from the device which is not permitted to input / output, the input / output to / from the memory on the virtual computer is directly performed by the virtual computer. Can be performed, and there is an effect that a specific virtual computer can speed up input / output processing to a device that is used exclusively for a relatively long time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing apparatus of the present invention, FIG. 2 is an explanatory diagram of an address conversion unit in the present invention, and FIG. 3 is an explanatory diagram of a direct input / output determination unit in the present invention. . In the figure, 1 ... Address conversion unit, 2 ... Direct input / output determination unit, 3 ... Memory access control unit, 4 ... Interrupt determination unit.

Claims (1)

[Claims] 1. A virtual computer system having memory-mapped input / output for realizing a plurality of virtual computers on one computer system, wherein it is determined whether a read / write operation to an arbitrary memory address corresponds to the input / output. One means, a second means for determining whether or not the virtual computer can directly read / write a memory address as input / output to / from a device, and a direct virtual computer is allowed to perform input / output. A third means for the virtual machine to handle input and output to and from the existing device,
And a fourth means for notifying the parent computer of input / output to / from a device that the virtual computer is not allowed to directly input / output, wherein the first means is a logical address tag, a physical page address holding unit, and An entry including a flag indicating whether the physical page is an input / output space is provided, and for an input logical address, a corresponding physical page number and an instruction signal indicating whether the physical page includes an input / output port are provided. The second means comprises a plurality of entries for storing input / output port logical addresses that can be directly input / output by the virtual machine, and the input logical addresses can be directly input / output to / from the input logical address. The fourth means determines whether or not it is an output port and outputs it. The fourth means directly outputs the instruction signal from the first means and the logical address output from the second means. The determination result of whether or not the input / output port is capable of direct input is used as an input, and it is determined whether or not to interrupt the parent computer. The third means is a logical output of the first means. By receiving the physical address corresponding to the address and the determination result of whether or not to perform the interrupt, which is the output of the fourth means, as an input signal, and determining whether to perform the memory access and the access to the input / output port. An information processing device characterized in that a virtual computer directly performs input / output to / from a memory on / from the virtual computer.