JPH0690265B2 - Test circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit incorporated in a circuit for testing each circuit portion constituting a circuit such as an LSI.

[Prior Art] As the design of circuits such as LSI becomes more complicated, the test becomes more complicated. In such a case, a test circuit may be incorporated between each circuit portion forming the circuit so that a test can be appropriately performed in each circuit portion unit.

FIG. 2 shows a conventional scan register type test circuit incorporated between each circuit portion in order to test each circuit portion.

This test circuit is designed so that when a circuit is tested, test data can be input to a desired circuit section, data processed by the circuit section can be output, and the output data can be verified. If not, the entire circuit composed of a plurality of circuit parts can perform normal operation.

In FIG. 2, the circuit parts 1a, 2a, 3a that make up the circuit are
For example, it is composed of a combinational logic circuit and has n input terminals 11, 21, 31 and n output terminals 12, 22, 32, respectively.

The test circuit includes n scan latch circuits 9 _{1 to} 9 _n arranged between the first circuit portion 1a and the second circuit portion 2a,
And a second circuit portion 2a and arranged n number of scan latch circuits 9 _{n + 1} to 9 _2n between the third circuit portion 3a.

The scan latch circuits 9 _{1 to} 9 _2n include a first input terminal a, a second input terminal b, a control terminal c, and an output terminal d.
And a signal input to the first input terminal a or a signal input to the second input terminal b is selectively output terminal d by the control signal C input to the control terminal c. It is designed to be output to.

Shows the configuration of the scan latch circuit 9 ₁ to 9 _2n in Figure 3.

This scan latch circuit is composed of an inverter 4 and a multiplexer 7 including two transmission gates 5 and 6, and a latch circuit 8. In this multiplexer 7, when the control signal C input to the control terminal c is at the "L" level, the transmission gate 5 is in the ON state, and the transmission gate 6
Is turned off, the signal DI ₁ input to the first input terminal a is transferred to the latch circuit 8. On the other hand, when the control signal C is at "H" level, the transmission gate 5 is turned off and the transmission gate 6 is turned on, so that the signal DI ₂ input to the second input terminal b is transferred to the latch circuit 8. It

The latch circuit is a master-slave type latch circuit synchronized with the clock signal φ. When the clock signal φ is at “H” level, the data DI from the multiplexer 7 is taken in, and when the clock signal φ is at “L” level, Output and hold the captured data DI. That is, this scan latch circuit takes in the signal DI ₁ input to the first input terminal a when the control signal C is at “L” level,
When the control signal C is at "H" level, the signal DI ₂ input to the second input terminal b is taken in.

In FIG. 2, the scan latch circuits of the first stage to the nth stage
The first input terminals a of 9 _{1 to} 9 _n are respectively connected to the output terminals 12 of the first circuit portion 1a, and the output terminal d is the second circuit portion.
2a is connected to the input terminal 21 of and are connected to the second input terminal b of the next scan latch circuits 9 ₂ ~9 _{n + 1.}

(N + 1) th to 2nth stage scan latch circuits 9 _{n + 1 to} 9
The first input terminal a of _2n is the output terminal 22 of the second circuit portion 2a.
And the output terminal d is connected to the input terminal 31 of the third circuit portion 3a. In addition, (n +
1) Stage- (2n-1) th stage scan latch circuit _{9n + 1-}
The output terminal d of 9 _2n-1 is connected to the second input terminal b of each of the scan latch circuits 9 _{n + 2 to} 9 _2n in the next stage.

The control terminals c of all the scan latch circuits 9 _{1 to} 92 _n are commonly connected, and the control signal C is input to the control terminals c. Input terminals 11 are respectively connected to the data input terminal I ₁ ~I _n of the first circuit portion 1a. The output terminals 32 of the circuit portion 3a are data output terminals, respectively.
It is connected to the O ₁ ~ O _n.

Next, the operation of this test circuit will be described.

In the operation of this test circuit, the control signal C is "L".
The operation mode when the level is high and the shift mode when the control signal C is at the "H" level are divided.

In operating mode, all scan latch circuits 9 _{1 to} 9 _2n
Since There has been a state for taking a signal being input to the first input terminal a, data input from the data input terminal I ₁ ~I _n in parallel are input to the first circuit part 1a, this data processed in the first circuit portion 1a is transferred to the second circuit portion 2a through the scan latch circuit 9 ₁ to 9 _n. The data processed by the second circuit portion 2a is transferred to the third circuit portion 3a via the scan latch circuits _{92n to} 9n _{+ 1} , and the data processed by the circuit portion 3a is output to the data output terminal. O ₁ is outputted from the ~ O _n in parallel. That is,
In the operation mode, the entire circuit composed of circuit portions 1a, 2a and 3a sequentially performs normal data processing in synchronization with clock signal φ. In the shift mode, all the scan latch circuits 9 _{1 to} 9 _2n are in a state of taking in the signal input to the second input terminal b, so that the scan latch circuits 9 _{1 to} 9 _2n are in one shift register. Make up. Thus, the serial data SI is input to the second input terminal b of the first-stage scan latch circuits 9 ₁ clock signal φ
In synchronization with the sequentially shifted to the next-stage scan latch circuits 9 ₂ to 9 _2n, it is output from the output terminal d of the scan latch circuit 9 _2n in the final stage as the output data SO. By combining these two operations, it becomes possible to carry out a test in circuit unit units.

For example, a case of testing the second circuit portion 2a will be described.

First, the test signal is set to the shift mode by setting the control signal C to the “H” level, and the test data for testing the second circuit portion 2a is supplied to the second scan latch circuit 9 ₁ of the second stage. The data is serially input from the input terminal b and stored in the scan latch circuits 91 to 9n in the _{first to nth} stages. Then the test circuit by the control signal C to "L" level to the operation mode, the output data of the second circuit portion 2a (n + 1) -th stage ~2n-th scan latch circuits 9 _{n +} Tokomu to ₁ ~9 _2n. Then, the mode is switched to the shift mode again, and the data taken in by the scan latch circuits 9 _{n + 1 to} 92 _n is output to the outside from the output terminal d of the final stage scan latch circuit 9 _2n by the shift operation, and this data is verified. To do.

[Problems to be Solved by the Invention] In the conventional test circuit described above, it is necessary to serially input test data for testing each circuit portion and take out the data processed by each circuit portion serially. Therefore, there are problems that the test time becomes long and that the test data creation becomes complicated.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a test circuit that can shorten the test time and can easily perform the test.

[Means for Solving Problems] The test circuit according to the present invention is composed of a plurality of parallel registers. Each parallel register is composed of a plurality of scan latch circuits. Each of the scan latch circuits has a first input terminal, a second input terminal,
It is provided with a first control terminal, a second control terminal, an output terminal, a selection means, and a latch means. Here, the selecting means selects the signal input to the first input terminal or the second input terminal in response to the signal input to the first control terminal. The latch means is the second
The signal selected by the selecting means is latched in response to the signal input to the control terminal of and is output to the output terminal. The first input terminal of each scan latch circuit in each parallel register is connected to the output terminal of the circuit portion, and the second input terminal is connected to the input terminal of the circuit portion, and The output terminal of the scan latch circuit is connected to the input terminals of other circuit parts. Furthermore, the first of each scan latch circuit
Control terminals are commonly connected to each parallel register, and the second control terminals of each scan latch circuit are all commonly connected.

[Operation] In the test circuit according to the present invention, the signal inputted to the first input terminal of the scan latch circuit is taken in and outputted by the signal inputted to the control terminal of the scan latch circuit forming each parallel register. Alternatively, it is possible to select, for each parallel register, whether to capture and output the signal input to the second input terminal.

In the parallel register in which the first input terminal is selected, each scan latch circuit takes in and outputs the data processed by the circuit portion connected to the input side of the parallel register.

In the parallel register in which the second input terminal is selected, each scan latch circuit takes in and outputs the output of each scan latch circuit of the other parallel register connected to the input side of the parallel register. That is, when the second input terminal is selected, the data input to the parallel register does not pass through the circuit portion connected to the input side of the parallel register.

Further, since the latch means in the scan latch circuit latches the selected signal and outputs it to the output terminal, the test data is input to the circuit portion to be tested at the same timing as the normal operation mode, and The data processed in the circuit portion is output at the same timing as in the normal operation mode.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a test circuit according to the present invention which is incorporated between these three circuit parts 1a, 2a, 3a in order to test the three circuit parts constituting the circuit.

Each circuit portion 1a, 2a, 3a is composed of, for example, a combinational logic circuit and has n input terminals 11, 21, 31 and n output terminals 12, 22, 32, respectively.

The test circuit has n scan latch circuits 1 ₁ to
Three parallel registers 10,20 consisting of 1 _n , 2 _{1 to} 2 _n , 3 _{1 to} 3 _n
It consists of 30. Each scan latch circuit 1 ₁ ~
1 _n , 2 _{1 to} 2 _n , 3 _{1 to} 3 _n have a first input terminal a, a second input terminal b, a control terminal c, and an output terminal d,
By the control signal C input to the control terminal c,
A signal input to the first input terminal a or the second input terminal b is selectively output to the output terminal d.

The scan latch circuits 1 ₁ to 1 _n , 2 ₁ to 2 _n , and 3 _{1 to} 3 _{n have} the same structure as that shown in FIG. 3, and when the control signal C is at "L" level, The signal input to the first input terminal a is taken in and output in synchronization with the clock signal φ, and when the control signal C is at the “H” level, the second signal is output in synchronization with the clock signal φ. Input terminal a
The signal input to is captured and output.

The first parallel register 10 is arranged between the first circuit part 1a and the second circuit part 2a, and the second parallel register 20 is arranged between the second circuit part 2a and the third circuit part 3a. The third parallel register 30 is arranged on the output side of the third circuit portion 3a.

Each input terminal 11 of the first circuit portion 1a has a data input terminal I ₁ ...
Connected to I _n . The first input terminals a of the scan latch circuits 1 ₁ to 1 _n forming the first parallel register 10 are respectively connected to the output terminals 12 of the first circuit portion 1a, and the second input terminals a b are connected to the data input terminal I ₁ ~I _n. The output terminal d of the scan latch circuits 1 ₁ to 1 _n are connected to the input terminals 21 of the second circuit portion 2a.

Further, the first input terminal a of each scan latch circuit 2 ₁ to 2 _n forming the second parallel register 20 is connected to the second circuit portion 2a.
The second input terminal b is connected to the output terminal d of each of the scan latch circuits ₁₁ to 1 _n forming the first parallel register 10. Then, the output terminals d of the scan latch circuits 2 ₁ to 2 _n
Are connected to the respective input terminals 31 of the third circuit portion 3a.

Further, the first input terminal a of each of the scan latch circuits 3 _{1 to} 3 _n forming the third parallel register 30 has a third circuit portion.
The second input terminal b is connected to the respective output terminals 32 of 3a, and the second input terminal b is connected to the output terminals d of the respective scan latch circuits 2 ₁ to 2 _n forming the second parallel register 20. The output terminals d of the scan latch circuits 3 _{1 to} 3 _n
They are respectively connected to the data output terminal O ₁ ~ O _n.

The control terminals c of the scan latch circuits 1 ₁ to 1 _n , 2 ₁ to 2 _n , and 3 _{1 to} 3 _n are commonly connected to each of the parallel registers 10, 20, and 30 and independently control signal C ₁ , C ₂ , C ₃ are given.

Next, the operation of the test circuit shown in FIG. 1 will be described.

The operation of this test circuit is divided into an operation mode and a test mode.

The operation mode is a state in which the control signals C ₁ , C ₂ and C ₃ are all fixed at the “L” level. At this time, the scan latch circuits 1 ₁ to 1 _n , 2 ₁ to 2 _n , and 3 _{1 to} 3 _n take in the data input to the first input terminal a and output the output terminal d.
Since output data sequential circuit portion 1a inputted to the data input terminal I ₁ ~I _n, 2a, after being processed by 3a, it is outputted from the data output terminal O ₁ ~ O _n. That is, the circuit part
The entire circuit composed of 1a, 2a and 3a sequentially performs data processing in synchronization with the clock signal φ.

In the test mode, any _one of the control signals C ₁ , C ₂ , and C ₃ is fixed to the “L” level.

For example, when testing the second circuit portion 2a sets the control signal C _1, C ₃ to "H" level, and sets the control signal C ₂ to the "L" level. At this time, the scan latch circuit 1 ₁ to 1 _n Since the output to the output terminal d by captures and data that is input to the second input terminal b,
The test data input to the data input terminals I _{1 to} I _n is the second
Is input to the circuit part 2a. Also, scan latch circuit
Since 2 _{1 to} 2 _n take in the data input to the first input terminal a and output it to the output terminal d, the second circuit portion 2a
The data processed by the scan latch circuit 2 ₁ to 2 _n
And is output to the output terminal d. Further, since the scan latch circuits 3 _{1 to} 3 _n take in the data input to the second input terminal b and output it to the output terminal d, the data is output to the output terminal d of the scan latch circuits 2 ₁ to 2 _n. the displayed data is outputted from the data output terminal O ₁ ~ O _n.

In this way, the test data input to the data input terminals I _{1 to} I _n is taken into the second circuit portion 2a via the first parallel register 10 and is supplied to the second circuit portion 2a. after being processed, is output to the data output terminal O ₁ ~ O _n via the second parallel register 20 and the third parallel register 30. Therefore, in this test mode, one parallel register is equivalently installed in the front stage of the second circuit portion 2a and two parallel registers are installed in the rear stage.

As described above, according to this test circuit, the test data can be input in parallel to a desired circuit portion and the data processed by the circuit portion can be output in parallel, which facilitates the testing of each circuit portion. In addition, the test time can be shortened.

The circuit portions 1a, 2a, 3a are not limited to the combinational logic circuit, and may be circuits having a pipeline structure that operate in synchronization with the clock signal.

Further, the scan latch circuit is not limited to the circuit shown in FIG. 3, and may be any circuit having a structure capable of selecting an input signal by a control signal.

As described above, according to the present invention, a parallel register is formed by using a plurality of scan latch circuits capable of selecting inputs, and a test circuit is formed by using a plurality of parallel registers. The test data can be input in parallel to the desired circuit part and the data processed in that circuit part can be output in parallel, which simplifies test data creation and facilitates testing of each circuit part. Also, the test time can be shortened.

Moreover, the test data can be input to the circuit part to be tested at the same timing as the normal operation mode, and the data processed by the circuit part can be output at the same timing as the normal operation mode. Therefore, an accurate test including the operation timing of the circuit portion can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a test circuit according to the present invention, FIG. 2 is a circuit diagram of a conventional scan register type test circuit, and FIG. 3 is a circuit diagram showing a configuration of a scan latch circuit. . In the figure, 1a, 2a, 3a are circuit parts, 11, 21, 31 are input terminals, 12, 22, 32 are output terminals, 1 ₁ to 1 _n , 2 ₁ to 2 _n , 3 _{1 to} 3 _n are scan latches. A circuit, a is a first input terminal, b is a second input terminal, c is a control terminal, d is an output terminal, and 10, 20 and 30 are parallel registers. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A test circuit which is incorporated between a plurality of circuit parts constituting a circuit and can test each of the circuit parts, wherein the test circuit comprises a plurality of parallel registers, Each parallel register includes a plurality of scan latch circuits, and each scan latch circuit has a first input terminal and a second input terminal.
An input terminal, a first control terminal, a second control terminal, an output terminal, and the first input terminal or the second input in response to a signal input to the first control terminal. Selecting means for selecting a signal input to the terminal;
Latching means for latching the signal selected by the selecting means in response to a signal inputted to the control terminal of the parallel latch and outputting the signal to the output terminal. Is connected to the output terminal of the circuit part, the second input terminal is connected to the input terminal of the circuit part, and the output terminal of each scan latch circuit is connected to the other circuit part. The input terminals are connected, the first control terminals of the scan latch circuits are commonly connected for each parallel register, and the second control terminals of the scan latch circuits are all commonly connected. Test circuit. 2. A circuit according to claim 1, wherein each of the circuit portions is composed of a combinational logic circuit.
Test circuit described in paragraph. 3. The test circuit according to claim 1, wherein each circuit portion is a circuit which operates in synchronization with a clock signal.