JPH0690264B2 - Integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a diagnostic method for an integrated circuit such as an LSI, and more particularly, to specify a test mode without adding an input terminal for specifying a test mode in the integrated circuit. The present invention relates to a possible integrated circuit diagnostic method.

An integrated circuit such as an LSI is a package of a logic circuit group composed of a large number of logic gate elements and is handled as one closed circuit (black box) having a certain unit of logic function and data processing function. On the other hand, in order to test (diagnose) the function of this integrated circuit, it is necessary to directly obtain the output of each part of the built-in logic circuit group. On the other hand, however, there is a great demand for avoiding the addition or addition of special input / output terminals for testing to the integrated circuit.

[Conventional technology]

Conventionally, for example, a diagnostic method as shown in FIG. 2 is used.

In FIG. 2, reference numeral 10 denotes a circuit to be diagnosed, which is a packaged integrated circuit such as an LSI. 11 to 19 are integrated circuits 10
Is a group of logic circuits built in. In the example shown in the figure, the counter unit 11 including multi-connected counter elements 11-0, 11-1, ... 11-n, a parity checker including multiple gates, a flip-flop 13, a reset circuit 14, and an AND gate 15 are provided. , 16, OR gates 17 and 19, and inverters 18 and other logic circuits.

In FIG. 2, a signal line extending from the left side of the integrated circuit 10 is an input signal line to the circuit 10. Further, a signal line extending to the right of the circuit 10 represents an output signal line. It goes without saying that the circuit 10 is provided with an input / output terminal corresponding to each of these input / output signal lines.

Therefore, the counter section 11 is supplied with the test signal TEST1 for forcibly operating the counter elements 11-1, ... Of each stage in addition to the operation clock CLK. The test signal TEST1 becomes an equable (E) input to the counter element via the OR gate 19. As a result, the output CT ₀ of the counter element at each stage, ...
… It becomes possible to obtain CTn all at once.

On the other hand, the parity checker 12 is normally supplied with data DATA from the CPU, memory, etc., and when a parity error occurs, the error signal ERR is sent via the flip-flop 13 to the interrupt signal N.
It is configured to be output as Mi. In order to directly see the error signal ERR at the time of circuit diagnosis, a circuit for switching the output is composed of the gates 15 to 18. That is, the direct output of the parity checker 12 can be seen as the output signal Aout by the test signal TEST2. still,
A is an output from a logic circuit (not shown).

[Problems to be solved by the invention]

As described above, in the related art, in order to obtain the output of each part in the integrated circuit 10, the test signals TEST1 to TEST1 to m are input from the outside. In other words, the circuit 10 itself receives the test signal TE
It was necessary to provide a special input terminal for inputting ST1 to m.

As is well known, LSIs and the like are provided with a large number of input / output terminals for connecting address data lines, data lines, or various control lines. Therefore, it is the case that it is impossible to provide a special test terminal like the above-mentioned method. Alternatively, even if a limited number of test terminals can be provided, there is a problem that a large number of types of tests cannot be specified over each part of the circuit. Furthermore, even if a test terminal can be provided, this terminal is used during normal operation (when incorporated in the device).
It is an unnecessary terminal that is not used for, and there is a big problem that it becomes completely useless.

[Means for solving problems]

An object of the present invention is to provide a diagnostic method capable of designating a desired type of test mode without providing an input terminal for designating a test mode in order to solve the above-mentioned problems.

Therefore, in the present invention, a memory circuit such as a register for storing the test mode is provided in the integrated circuit, and data indicating the test mode is written to this memory circuit by using a normal external access operation. It is configured to be plugged in (set).

[Action]

That is, in the present invention, the test mode is treated as data supplied from the outside, and one or a subsequent address map is assigned to the memory circuit provided in the integrated circuit. Therefore, the test mode can be set by using a normal access operation (access of a memory or the like by outputting an address and data). The present invention will be described in detail below with reference to examples.

〔Example〕

FIGS. 1 (a) and 1 (b) are views showing an embodiment of the present invention, and portions common to FIG. 2 are designated by the same reference numerals.

FIG. 1 (a) shows a configuration for diagnosing the integrated circuit 10 by itself. As shown in the figure, in this embodiment, a register 22 is provided inside the circuit 10 instead of the test signal TEST conventionally supported from the outside via an input terminal. A specific address is assigned to this register 22.

Therefore, an address assigned to the register 22 is issued from a diagnostic device (not shown), and data indicating the test mode is output. This address is supplied to the address decoder 21. The decoder 21 issues a chip select signal which activates the register 22 indicated by the given address. As a result, the data output from the diagnostic device is set in the register 22.

As a result, each bit information "1,0" of the data set in the register 22 is issued as the test signals TEST1 to m.

Although not shown in FIG. 2, the address decoder 21 shown in the embodiment may be considered as an existing one provided in the integrated circuit 10. During normal operation, it is used to decode the address of a processing device such as a processor.

FIG. 1 (b) shows a configuration in which the integrated circuit 10 is mounted in a device or the like for operation.

As shown in the figure, the processing device such as the processor 30 and the control line,
The address and data lines will be connected. As a result, the processor 30 presets data in a buffer or the like in the circuit 10 (not shown), and performs operations performed by the circuit 10.
The data processing function will be used.

In this case, the address map space issued by the processor 30 does not include the address assigned to the register 22.
However, due to the runaway of the processor 30, the register 22
May be accessed.

Therefore, in the present embodiment, a means for always making the reset terminal scale of the register 22 valid (level "0") is provided at the time of mounting on the device. That is, the register reset terminal 23 of the integrated circuit 10 corresponding to the reset terminal R is always at the 0 level "Z0
For example, a grounding mechanism 24 is provided so as to give 0 ".

As a result, the register 22 is always in the reset state, and even if the processor 30 erroneously accesses the test signal TEST,
Can be prevented from accidentally becoming the "1" level.

〔The invention's effect〕

As described above, according to the present invention, a desired type of test mode can be set in the integrated circuit without providing a test terminal. Therefore, the operation of each part of the integrated circuit can be diagnosed, and the diagnosis rate can be improved.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1A is a diagram showing a connection example during diagnosis, and FIG. 1B is a diagram showing a connection example during normal operation. FIG. 2 is a diagram showing a conventional diagnosis method.

Claims (1)

[Claims] 1. An integrated circuit having a logic circuit group including storage means such as a counter, and obtaining an output of each part of the logic circuit group with respect to data given to the integrated circuit through an input terminal. Input terminal, a memory circuit in which data for testing a logic circuit group is stored, an address input from the input terminal is decoded, a chip is selected based on the input address, and a test mode is set. When the indicated address is input from the input terminal,
An integrated circuit having an address decoder for selecting a memory circuit.