JPH0690147A - Digital clock multiplying circuit - Google Patents

Abstract

PURPOSE:To provide the clock multiplying circuit which multiplies the frequency of an input clock signal with simple circuit configuration. CONSTITUTION:This circuit is provided with a buffer logic 11 for delay serially connecting buffers 11a-11e provided with the delay characteristics of signal propagation. When an input clock signal (a) is inputted from an input terminal 10, a delayed clock (b) is generated. When this signal and the input clock signal (a) are exclusively ORed by an EOR 12 and the output is dispatched to an LPF 13, a sine wave signal double multiplying the frequency is generated. When the waveform of this signal is shaped by a buffer 16, a clock signal (e) multiplying the frequency is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital clock multiplication circuit for multiplying the frequency of a clock signal of a digital circuit.

[0002]

2. Description of the Related Art In recent years, digitalization of signal processing has advanced, and a clock signal having a high frequency has been often used. Along with this, a problem of unnecessary radiation radiated from a wiring line or the like for transmitting a clock signal has become a problem. Therefore, some electronic circuits transmit a clock signal at a low frequency, and use a PLL circuit or the like to multiply the frequency of the clock signal to a desired frequency before performing digital signal processing.

[0003]

However, in the digital clock multiplication circuit using the PLL circuit, circuits such as a phase comparator, a low-pass filter, a voltage controlled oscillator, and a frequency divider are required respectively, and the circuit configuration becomes large. There was a drawback. In order to solve such a conventional problem, the inventor has proposed a digital clock multiplication circuit that doubles the frequency by using a simple logic circuit (not yet published).

FIG. 3 is a circuit diagram of a digital clock multiplication circuit constructed by using a simple logic circuit, and FIG. 4 is a time chart showing its operation. In FIG. 3, as shown in FIG.
It is assumed that a pulse a having a frequency of Hz and a duty ratio of 50% is input.
If the signal delay time of each of the buffers 2a to 2e in the buffer logic 2 is, for example, 5 nsec, the buffer logic 2 delays the pulse b by 25 nsec as shown in FIG. 4B.
Is output.

The exclusive OR circuit (EOR) 3 outputs a pulse a
When the exclusive OR of the pulse b and the pulse b is obtained, a pulse c as shown in FIG. 4C is generated. That is, the output pulse c of the EOR3 has a frequency of 20 MHz and a duty ratio of about 1: 1 and is output from the output terminal 4. As described above, only by using the plurality of buffers 2a to 2e and EOR3, it is possible to generate the clock signal whose frequency is doubled.

However, in such a configuration, the signal delay time of each of the buffers 2a to 2e changes depending on the variation of each element or the temperature characteristic, and the duty ratio of the output pulse c is not always 1: 1 and the ratio changes. There is a possible problem.

The present invention has been made in view of the above problems, and it doubles the frequency by using a simple logic circuit and is not affected by the temperature characteristics of the elements used in the buffer circuit. The duty ratio of the output pulse is always 1:
The object is to realize a digital clock multiplication circuit which becomes 1.

[0008]

According to the present invention, there is provided a delay circuit for delaying an input clock signal, an exclusive OR circuit for exclusive ORing an input clock signal and an output signal of the delay circuit,
A low-pass filter for inputting the output of the exclusive-OR circuit and passing components up to twice the frequency of the input clock signal; and a waveform shaping circuit for converting the output of the low-pass filter into pulses It is what

[0009]

According to the present invention having such characteristics, when the input clock signal is input to the delay circuit, the signal is delayed. When the exclusive OR circuit takes the exclusive OR of the input clock signal and the output signal of the delay circuit, a pulse whose frequency is doubled is obtained. Further, when this pulse is passed through a low pass filter, it is converted into a sine wave signal having a frequency twice that of the input clock signal. Then, when this sine wave signal is subjected to waveform conversion by a waveform shaping circuit, a clock signal having a frequency multiplied is output.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital clock multiplication circuit according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram showing the configuration of a digital clock multiplication circuit according to an embodiment of the present invention. In FIG. 1, the input terminal 10
Is an input terminal to which a clock signal a is input from a clock signal source (not shown) provided in the electronic device via a wiring line. The buffer logic 11 for delay is a delay circuit in which a plurality of buffers 11a to 11e are connected in series. The number of buffers 11a to 11e is, for example, one per circuit.
It is assumed that the signal delay time is about nsec.

Output b and input 1 of buffer logic 11
The signals a of 0 are given to the EOR 12, respectively. EOR12
Is an exclusive OR circuit, and a pulse c that changes at the rising and falling times of the input clock a and the delayed clock signal b
Is a circuit for generating. The output end of EOR12 is coil L
Is connected to the input end of C and the output end of coil L is capacitor C
1 is connected to one end. The coil L and the capacitor C1 are
Low-pass filter (LPF) 13 that blocks frequency components exceeding the repetition frequency of the pulse output from the EOR 12
Is.

Next, both ends of the capacitor C1 have resistors R1 and R
2 connected in series. The resistors R1 and R2 are LP
An amplitude adjusting circuit 14 that attenuates the output of F13 and adjusts the amplitude to a predetermined level. The common connection ends of the resistors R1 and R2 are connected to the level adjusting circuit 15. Level adjustment circuit 1
5 is a resistor C3 between the capacitor C2, the power source Vcc and the ground.
This is a circuit provided with a series connection body of R4, and holds the DC level of the sine wave signal output from the capacitor C2 at a specific voltage. Next, the buffer 16 is a waveform shaping circuit that shapes the waveform of the sine wave signal output from the level adjustment circuit 15 and converts it into a pulse. The signal of the buffer 16 is output from the output terminal 17.

The operation of the digital clock multiplication circuit of the present embodiment thus constructed will be described with reference to the time chart of FIG. The input terminal 10 has an oscillation frequency of, for example, 10 MHz and a duty ratio of about 1: 1 as shown in FIG.
It is assumed that the pulse a of is input. Buffer logic 11
The internal buffers 11a to 11e each have a unique signal delay time, and the buffer logic 11 outputs a delayed pulse b as shown in FIG. 2 (b). When the EOR 12 takes the exclusive OR of the pulse a and the pulse b,
A pulse c as shown in (c) is generated. That is, EOR1
The output pulse c of 2 has its repetition frequency multiplied to 20 MHz. The duty ratio is set to the buffers 11a to 11
It depends on the element characteristics or temperature characteristics of e, and is not always 1:
It cannot be 1.

Next, when the output of the EOR 12 is given to the LPF 13, the signal component exceeding 20 MHz is cut off, and the signal shown in FIG.
A sine wave signal d of 20 MHz is generated as shown in FIG. When this signal d is input to the buffer 16 via the amplitude adjusting circuit 14 and the level adjusting circuit 15, as shown in FIG.
A 20 MHz pulse e is generated.

By thus providing the LPF 13, even if the duty ratio of the pulse output from the EOR 12 changes, only the fundamental frequency component of the pulse is filtered and a multiplied sine wave signal is generated. When such a sine wave signal is passed through a buffer of a digital circuit, its waveform is converted into a binary signal, and a pulse having a duty ratio of about 1: 1 is generated.

[0016]

As described above, according to the present invention, the input clock signal delayed by the delay circuit is subjected to exclusive OR with the original input clock signal to generate a pulse having a frequency doubled. This pulse is passed through a low-pass filter to generate a frequency-multiplied sinusoidal signal. By passing this signal through a waveform shaping circuit, a digital clock with a duty ratio of 1: 1 can be obtained. Therefore, it is possible to lower the frequency of the clock line in the electronic device and easily multiply the clock frequency at the input section of the signal processing circuit of the terminal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a digital clock multiplication circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the digital clock multiplication circuit of this embodiment.

FIG. 3 is a circuit diagram showing a configuration example of a clock multiplication circuit using a buffer logic.

FIG. 4 is a time chart showing an operation of a clock multiplication circuit using a buffer logic.

[Explanation of symbols]

 10 Input Terminal 11 Buffer Logic for Delay 11a to 11e, 16 Buffer 12 EOR 13 LPF 14 Amplitude Adjusting Circuit 15 Level Adjusting Circuit

Claims (1)

[Claims] 1. A delay circuit for delaying an input clock signal, an exclusive OR circuit for exclusive ORing an input clock signal and an output signal of the delay circuit, and an output of the exclusive OR circuit. A digital clock multiplying circuit comprising: a low-pass filter that passes a component up to twice the frequency of the input clock signal; and a waveform shaping circuit that transforms the output of the low-pass filter into a pulse.