JPH0683289A - Display control device - Google Patents

Abstract

PURPOSE:To perform finely display control of a ferroelectric liquid crystal display device having a storing characteristic for a display state by using a dedicated display control device for a CRT. CONSTITUTION:A rewriting and detecting/flag generation circuit 5 detects an address accessing to a VRAM3 via an SVGA1 being a display control device for a CRT in order to rewrite a display by a CPU of host side, and sets a flag in a register of a corresponding address. The CPU reads out a flag relating to this rewriting, sends an ENABLE signal for transferring a line address and line data to the SVGA1 via a line address generating circuit 7, and transfers rewriting display data from the VRAM3 to an FLCD20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
More specifically, the present invention relates to a display control device for a display device that includes a display element that can maintain a display state updated by applying an electric field or the like using a ferroelectric liquid crystal as an operation medium for display update.

[0002]

2. Description of the Related Art In information processing systems and the like, a display device is used as an information display means having a function of visually expressing information. As such a display device, a CRT display device (hereinafter, simply referred to as CRT) is generally used. Target.

There are various types of information processing systems available as so-called personal computers depending on the hardware, software, signal transmission system, etc. used therein. In this case, the display control device (CRTC) of the CRT is also unique to each system. As such a CRTC, for example, a VGA (Vi
VG as a Deo Graphics Array)
A81 (by IBM) or 86C as SVGA (Super VGA) with an accelerator function etc. added when displaying a predetermined image such as a circle or rectangle.
911 (according to S3 company) is known.

FIG. 1 is a block diagram showing an example of a configuration using SVGA for CRTC.

When the host CPU of the information processing system rewrites a part of the display memory window area in the host side memory space, the rewritten display data is transferred to the VRAM 3 via the system bus 40 and the SVGA 1. The SVGA 1 generates a VRAM address based on the address of the display memory window area,
In 3, the display data specified by this VRAM address is rewritten.

On the other hand, the SVGA1 accesses the VRAM3 in the same cycle as the scanning cycle in the CRT, and the VRAM3
The display data that is expanded to are sequentially read, and RAMDAC2
Transfer to. The RAMDAC 2 sequentially converts the display data into R, G, B analog signals and transfers them to the CRT 4. Thus, the SVGA used as the display control device for the CRT functions to unilaterally transfer the display data to the CRT side at a predetermined cycle.

In the case of the above-mentioned CRT display control, VRAM
Since 3 is a dual port RAM, writing of display data to the VRAM for changing display information and the like, and operation of reading the display data from the VRAM and displaying the data can be performed independently of each other. For this reason,
The host CPU has an advantage that desired display data can be written at any timing without any consideration of display timing and the like.

However, since the CRT requires a certain length in the thickness direction of the display screen, the volume of the CRT becomes large as a whole, and it is difficult to reduce the size of the entire display device.
In addition, the degree of freedom in using an information processing system that uses such a CRT as a display is also improved.
That is, the degree of freedom in installation location, portability, etc. is impaired.

A liquid crystal display (hereinafter referred to as LCD) can be used as a display device that compensates for this point. That is, according to the LCD, it is possible to reduce the size (in particular, reduce the thickness) of the entire display device. In such LCD,
Ferroelectric liquid crystal (hereinafter, FLC: Ferroelectric
There is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of ic Liquid Crystal), and one of the features is that the liquid crystal cell has a storage state of a display state against the application of an electric field. It is in. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and excluding the electric field. However, each alignment state is maintained. Due to the bistability of the FLC molecule, the FLCD
Has memory. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-76357.

Although the FLCD has the above-mentioned memory property, the display update operation of the FLC is relatively slow, and therefore, for example, cursor movement, character input, scrolling, etc.
In some cases, it is not possible to follow the change in the display information that requires the display to be immediately rewritten.

An FLCD having such contradictory characteristics
Are derived from these characteristics or supplement these characteristics, so that various driving modes for display thereof are possible. That is, in the refresh driving in which the scanning lines on the display screen are sequentially and continuously driven like the CRT and other liquid crystal display devices, a relatively long margin can be provided in the driving cycle. In addition to this refresh driving, partial rewriting driving for updating the display state of only a portion (line) corresponding to a change on the display screen and interlaced driving for driving by thinning out scanning lines on the display screen are possible. Then, the partial rewriting drive and the interlace drive can improve the followability to the change of the display information.

If the display control of the FLCD having the above advantages can be performed using the existing CRT display control circuit, an information processing system using the FLCD as a display device can be constructed at a relatively low cost. It is advantageous.

[0013]

An object of the present invention is to provide a display control device capable of satisfactorily controlling the display of an FLCD using a display control circuit for a CRT.

In particular, it is an object of the present invention to provide a display control device capable of favorably performing partial rewriting specific to FLCD.

[0015]

Therefore, according to the present invention,
In a display control device of a display device capable of updating a display state only for a display element associated with a display change, a display data storage unit storing display data and a display data stored in the storage unit A display control circuit that can be sequentially read and transferred to the display device at regular intervals and that can partially rewrite the display data stored in the storage means; and a display control circuit for rewriting the display data. A rewrite detecting means for detecting an address to be accessed by the display data storing means, a read operation for reading the address detected by the rewrite detecting means, and a transfer for permitting the display control circuit to transfer only the display data of the read address. It is characterized by comprising permission means.

[0016]

According to the above construction, when the display control circuit rewrites the display data, the address of the display data is detected, and only the display data of the address is read by the display control circuit and transferred to the display device. .

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an information processing system in which an FLC display device having a display control device according to an embodiment of the present invention is used as a display device for displaying various characters and image information.

In the figure, 21 is a CPU for controlling the entire information processing system, 22 is a ROM for storing a program executed by the CPU 21, and 28 is a main memory used as a work area or the like for executing the program. is there. Reference numeral 14 is a DMA controller (Direct Me) that transfers data between the main memory 28 and various devices constituting this system without going through the CPU 21.
(more access controller, hereinafter referred to as DMAC). 32 is Ethernet (XER
It is a LAN interface between a LAN (Local Area Network) 37 such as OX Company and this system. Reference numerals 26 and 27 are a hard disk device and its interface and a floppy disk device and its interface as external storage devices, respectively. 36 is a printer which can be constituted by an ink jet printer, laser beam printer or the like capable of relatively high resolution recording, 31 is a parallel interface for making a signal connection between the printer and this system, and 29 is A keyboard and a controller for inputting character information such as various characters and control information. 33 is a communication modem for performing signal modulation between the communication line and the system of this example, 34 is a mouse as a pointing device, 35 is an image scanner for reading images, etc. Example Exchange signals with the system. The interrupt controller 24 controls interrupt processing in program execution, and the real-time clock 25
Controls the timekeeping function in this system. Reference numeral 20 denotes an F display whose display is controlled by the FLCD interface 10 as a display control device according to an embodiment of the present invention.
It is an LC display device (also called FLCD), and has a display screen using the above-mentioned ferroelectric liquid crystal as its display operation medium.
A display memory window area accessible by the CPU 21 is also expanded in the FLCD interface 10. Reference numeral 40 is a system bus composed of a data bus, a control bus, and an address bus for connecting signals between the above-mentioned devices.

In the information processing system in which the above-described various devices are connected, the system user generally
The operation is performed while responding to various information displayed on the display screen of the FLCD 20. That is, the external device connected to the LAN 37, the hard disk 26, the floppy disk 27, the scanner 35, the characters supplied from the keyboard 29, the mouse 34, image information, and the main memory 2
The operation information related to the user's system operation stored in 8 is displayed on the display screen of the FLCD 20, and the user edits the information and gives an instruction operation to the system while watching this display. Here, the above various devices are
A display information supply unit is configured for the LCD 20.

First Embodiment FIG. 3 is a block diagram showing details of the FLCD interface 10 according to the first embodiment of the present invention.

As shown in the figure, the FLCD interface 10 of this embodiment, that is, the display control device, uses an existing SVGA which is a display control circuit for a CRT.
A1 is used. The configuration of the SVGA 1 of this example will be described with reference to FIG.

In FIG. 4, the rewrite display data that the host CPU 21 (see FIG. 2) accesses for writing in the display memory window area of the FLCD interface 10 (see FIG. 2) is transferred via the system bus 40, It is temporarily stored in the FIFO 101. Also,
Bank address data for projecting the display memory window area onto an arbitrary area of the VRAM 3 is also stored on the system bus 4.
Transferred via 0. The display data has a form of 24-bit data representing 256 gradations of R, G and B colors. The control information such as the command from the CPU 21 and the bank address data described above is transferred in the form of register set data, and the register get data is transferred to the CPU 21 side for the CPU 21 to know the state of the SVGA side. The resist set data and display data stored in the FIFO 101 are sequentially output, and the bus interface unit 103 and VGA are output according to these data.
It is set in each register in 111. The VGA 111 can know the bank address, its display data and the control command depending on the set state of these registers.

The VGA 111 generates a VRAM address in the VRAM 3 corresponding to the address of the display memory window area and the bank address,
At the same time, the strobe signals RAS and CAS as the memory control signals, the chip select signal CS, and the write enable signal WE are transferred to the VRAM 3 via the memory interface unit 109, whereby the display data is written to the VRAM address. be able to. At this time, the display data to be rewritten is similarly VRA via the memory interface unit 109.
Transferred to M3.

On the other hand, the VGA 111 is a VRAM specified by the requested line address transferred from the line address generation circuit 7 (see FIG. 3), as will be described later.
The display data of No. 3 is read from the VRAM 3 in accordance with the line data transfer enable signal similarly transferred, and the FIF
Store in O113. From the FIFO 113, the display data is sent to the FLCD side in the order in which the display data was stored.

The SVGA 1 is provided with the data manipulator 105 and the graphics engine 107 that fulfill the accelerator function as described above. For example, when the CPU 21 sets a circle and its center and radius data in the register of the bus interface 103 and instructs drawing of the circle, the graphics engine 10
7 generates the circle display data, and the data manipulator 105 writes this data in the VRAM 3.

The SVGA 1 described above with reference to FIG.
Is obtained by making a slight modification to the VGA portion of the existing SVGA for CRT.

Referring again to FIG. 3, the rewrite detection / flag generation circuit 5 monitors the VRAM address generated by the SVGA 1, and the VRAM address when the display data of the VRAM 3 is rewritten (written), that is, a write. The VRAM address when the enable signal and the chip select signal CS become "1" is fetched. Then, this VRAM address and the VRA obtained from the CPU 9
A line address is calculated based on each data of M address offset, total line number, and total line bit number. The concept of this calculation is shown in FIG.

As shown in FIG. 5, the pixel indicated by the address X on the VRAM 3 corresponds to the line N of the FLCD screen, one line is made up of a plurality of pixels, and one pixel is made up of a plurality of pixels. It shall consist of (n) bytes. At this time, the line address (line number N)
Is calculated as follows:

[0030]

[Equation 1]

The rewrite detection / flag generation circuit 5 sets a partial rewrite line flag register included therein according to the calculated line address. This state is shown in FIG.
Shown in.

As is apparent from FIG. 6, in order to display the character "L", for example, when the display of the corresponding address on the VRAM 3 is rewritten, the rewritten line address is detected by the above calculation, and this address is detected. A flag is set in the register corresponding to (1 is set).

The CPU 9 reads the contents of the rewrite line flag register of the rewrite detection / flag generation circuit 5 via the line address generation circuit 7 and sends the line address in which the flag is set to the SVGA 1. At this time, the line address generation circuit 7 sends a line data transfer enable signal corresponding to the line address data, and S
The display data of the above address is transferred from the VGA 1 (FIFO 113 thereof) to the binarization halftone processing circuit 11.

The binarization halftone processing circuit 11 includes R, G, B
The multi-value display data of 256 gradations represented by 8 bits for each color is converted into binary pixel data corresponding to each pixel on the display screen of the FLCD 20. In this example, one pixel of the display screen has display cells having different areas for each color as shown in FIG. Accordingly, the data for one pixel also has 2 bits (R1, R2, G1, G2, B1, B2) for each color, as shown in FIG. Therefore, the binarization halftone processing circuit 11 converts 8-bit display data into 2-bit binary data of each color (that is, 4-value data of each color).

FIG. 9 shows the flow of data until it is converted into pixel data for FLCD display as described above.

As is apparent from FIG. 9, in this example, VRA
The display data of M3 is stored as multi-valued data of 8 bits for each color of R, G and B, and is binarized when these are read out and displayed. As a result, the host CPU 21 (see FIG. 2) can access the FLCD 20 side as in the case of using a CRT, and can ensure compatibility with the CRT.

A known method can be used as the method used in the binarization and halftone processing. As such a method, for example, an error diffusion method, an average density method, a dither method, etc. are known. There is.

In FIG. 3, the border generation circuit 13 is
The pixel data of the border portion on the FLCD display screen is generated. That is, as shown in FIG.
The display screen of 0 has 10 lines per line consisting of 1280 pixels.
There are 24 lines, and a border portion of this display screen that is not used for display is formed so as to frame the display screen.

Due to the existence of this border portion, F
The format of the pixel data transferred to the LCD 20 is
It becomes what is shown in FIG. 8 (A) or FIG. 8 (B). Figure 8
7A shows the data format of the display line A shown in FIG. 7, that is, the display line in which all the display lines are included in the border portion, and FIG. 8B shows the display line B shown in FIG. This is the data format of the line used. The data format of display line A is
A line address is added to the beginning, and this is followed by border pixel data. On the other hand, since both ends of the display line B are included in the border portion, the data format thereof follows the line address, followed by border pixel data, pixel data, and border pixel data in this order.

The border pixel data generated by the border generation circuit 13 is serially synthesized by the synthesis circuit 15 with the pixel data from the binarization halftone processing circuit 11. Further, the combined line 17 is combined with the display line address from the line address generation circuit 7 in the combined circuit 17 and then sent to the FLCD 20.

The CPU 9 controls the entire configuration described above. That is, the CPU 9 is the host CPU 2
1 (see FIG. 2), the total number of lines on the display screen, the total number of line bits, and cursor information are received. Also, CP
U9 sends VRA to the rewrite detection / flag generation circuit 5.
The M address offset, the total number of lines, and the total number of line bits are transmitted, the line flag register is initialized, and the line address generation circuit 7 receives a display start line address, a continuous display line number, The total number of lines, the total number of line bits, and the data of the border area are transmitted, and the partial rewriting line flag information is obtained from the circuit 7. Further, the CPU 9 sends each data of the bandwidth, the total number of line bits and the processing mode to the binarization halftone processing circuit 11 and sends the border pattern data to the border generation circuit 13.

Further, the CPU 9 receives the temperature information and status signals such as a Busy signal from the FLCD 20, and sends a command signal and a reset signal to the FLCD 20.

The FLC described above mainly with reference to FIG.
The display control of partial rewriting by the D interface 10 will be described.

FIG. 10 is a flow chart showing the flow of processing at the time of partial rewriting, and FIG. 11 is a timing chart of each signal and data.

Display control for partial rewriting will be described below with reference to FIGS.

Whether the host CPU 21 writes the display data in the VRAM 3 (step S101 in FIG. 10; hereinafter, only step numbers are shown), or the host CPU 21 outputs SV.
Instruct the GA1 accelerator to draw (step S
121), when the accelerator writes the display data in the VRAM 3 (step S122), the write enable signal WE and the chip select signal CS generated by the SVGA1 at this time become "1", so the rewrite detection / flag generation circuit 5 This is detected in step S102 (time point in FIG. 11; hereinafter, only time point is shown), and the rewritten VRAM address is fetched. Then, the rewriting line address is calculated based on the rewriting VRAM address in step S103 (time point), and the rewriting line flag is set in step S104 (time point).

The SVGA 1 sends V-sync to the rewrite detection / flag generation circuit 5 at a predetermined cycle (time point), whereby the rewrite detection / flag generation circuit 5 outputs rewrite line flag information. On the other hand, step S
At 105, the CPU 9 reads the rewriting line flag information via the line address generating circuit 7 (time point). Figure 11
As can be seen from the above, the flag set before the sending of the V-sync is read by the V-sync.

The CPU 9 selects a display line according to the priority order of cursor information or the like based on the rewriting line flag information obtained through the line address generating circuit 7 (step S106), and the line address generating circuit 7 receives the selected line. The display start line address corresponding to the display line and the number of continuous display lines are designated (step S107). In response to this, in step S108, the line address generation circuit 7
Sends the line address of the rewriting line to SVGA1 (time point) and sends a line data transfer enable signal (time point) to request display data transfer.

In response to this request, in step S109,
Upon receiving the line data transfer enable signal, the rewrite / flag generation circuit clears the rewrite line flag corresponding to the requested line address (at the time point), and in step S110, the SVGA1 outputs the display data of the requested line address to the VRAM3. Read out and sent to the binarization halftone processing circuit 11 (time point). Next, in step S111, the binarization halftone processing circuit 11

[0050]

[Outer 1]

In step S112, border pixel data is added to this pixel data, and further,

[0052]

[Outside 2]

Based on the data of this rewriting line, the FLCD
20 displays (step S114).

As described above, the FLCD interface, which is the display control circuit of this example, can be accessed only when the host CPU accesses the VRAM for display rewriting.
It is possible to transfer the line address and line data transfer enable signal relating to the rewriting to the SVGA and send the display data to the FLCD, whereby the partial rewriting can be performed.

The SVGA accesses the VRAM to read and transfer the display data only when the line data transfer enable signal is transferred.
This is possible with a few modifications to

That is, the SVGA 1 originally has a function of reading the display data of the VRAM in synchronization with the scanning cycle of the CRT for CRT display, and this can be performed by the address counter of the SVGA. In this example,
This address counter modifies the SVGA so that it can count up only when the line data transfer enable signal is "1".

Further, in the configuration using the line data transfer enable signal and the address counter as described above, the display control of the refresh and the interface is performed as follows.

The CPU 9 sets the refresh mode when, for example, the read rewriting line flags are continuously set for a predetermined number or more. For example, the first display on the FLCD display screen is set.
The th line is the display start line address, and the number of continuous display lines is the total number of lines (1024 lines) on the display screen. As a result, the line address generation circuit 7 causes the SVG
The line data transfer enable signal is transferred in the same cycle as the VRAM read cycle that A1 originally has.

In the interlaced display mode,
In this mode, the number of thinned lines is FLCD20.
Although it is determined by the temperature information from the above and the trimmer information according to the user's preference, the CPU 9 appropriately sets the display start line address and the number of continuous display lines to provide interlaced display.

The refresh display can be performed in a predetermined cycle other than when the host CPU accesses the VRAM for rewriting. According to this, it is possible to correct a slight deviation of the alignment of the liquid crystal molecules caused by the electric field generated by the common electrode of the FLCD display panel, and to maintain a good display state.

Embodiment 2 FIG. 12 is a block diagram showing the configuration of an FLCD interface according to Embodiment 2 of the present invention, and FIG.
It is a block diagram which shows the detail of SVGA1A shown in FIG.
In the configurations shown in these figures, the same elements as those of the first embodiment shown in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

This example differs from the first example in that SVGA1
A rewrite detection / line address generation circuit 115 is provided in A, and the rewrite detection / line address generation circuit 11 is provided.
The point is that the flag generation circuit 5A sets the rewriting line flag of the flag register in accordance with the rewriting line address generated by 5 (see step S202 in FIG. 14).

According to the above configuration, the number of signal lines connecting between the SVGA 1A and the flag generation circuit 5A is reduced by the number of control signal lines as compared with the first embodiment.

Third Embodiment FIG. 15 is a block diagram showing the structure of an FLCD interface according to the third embodiment of the present invention, and FIG. 16 is shown in FIG.
It is a block diagram which shows the detail of SVGA1B shown in FIG. In the configurations shown in these figures, the same elements as those of the first embodiment shown in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

This example differs from the first example in that SVGA1
The point is that a rewrite detection / flag generation circuit 117 and a rewrite line flag register 119 are provided in B. As a result, as shown in step S302 of FIG. 17, the SVGA1B finally sets the rewrite line flag, and CP
U9 is connected to the SVGA1B via the line address generation circuit 9.
The rewrite line flag information can be read from the.

According to the above configuration, SVGA1B through F
The signal output to the LCD side is only the rewriting line flag information, and the number of signal lines is further reduced as compared with the second embodiment.

Embodiment 4 In each of the embodiments described above, the host CPU monitors the address for accessing the VRAM for display rewriting, identifies the rewriting portion based on this address, and rewrites only that portion. .

By the way, the operating temperature of the display element of the FLCD changes according to the ambient temperature. For example, in the configuration of FIG. 3, it can be said that the FLCD 20 receives pixel data and the like and the display speed based on this changes with temperature.

Therefore, in this example, for example, in FIG. 3, the FLCD 20 generates a Busy signal as a status signal, and the CPU 9 monitors the cycle of the Busy signal. Then, the pixel data transfer cycle is determined according to this cycle. Instead of the Busy signal, the temperature information may be directly fetched and the transfer cycle may be changed accordingly.

FIG. 18 is a flowchart showing the flow of the above processing.

In step S401, the cycle of the Busy signal is fetched, and in step S402, it is determined whether this cycle is longer or shorter than a predetermined cycle. If the period is longer than the predetermined period, the period M is set in the interval register provided in the line address generation circuit, for example, in step S403, and if it is shorter, N is set shorter than M in step S404. Then, in step S405, the display data is transferred from the SVGA1 in the cycle M or N. In this case, when the display data is transferred in the cycle of M or N, the display data of the line address corresponding to the flag set in the rewriting line flag register is transferred in accordance with the priority order during these cycles. That is, the address generation circuit sends out the line address in which the rewrite flag is set and its data transfer enable.

According to this example, the time taken for the SVGA to read the display data from the VRAM and to transfer the display data to the FLCD side is small in the processing time of the entire SVGA. That is, when the FLCD side receives the display data and the like, the time for waiting the transfer of the display data and the like during the Busy signal becomes short, and the SVGA is used for writing to the VRAM and exchanging data with the host CPU. Processing time can be reduced. In addition, since the waiting time is shortened, it is possible to reduce the line buffer.

[0073]

As is apparent from the above description, according to the present invention, when the display control circuit rewrites the display data,
The address of the display data is detected, and only the display data of the address is read by the display control circuit and transferred to the display device.

As a result, for example, VGA or SVG having a function of reading and transferring display data at a predetermined cycle for CRT
Even when a display control circuit such as A is used, it is possible to particularly satisfactorily perform partial rewriting in a display device including a ferroelectric liquid crystal or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional display control device.

FIG. 2 is a block diagram showing an information processing system according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a display control device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing details of the SVGA shown in FIG.

FIG. 5 is a schematic diagram for explaining conversion from a VRAM address to a line address in the embodiment of the present invention.

FIG. 6 is a schematic diagram showing a relationship between a rewriting display pixel and a rewriting line flag register in the embodiment of the present invention.

FIG. 7 is a schematic view showing an FLCD display screen in the embodiment of the present invention.

8A and 8B are schematic diagrams showing a data format of display data in the embodiment of the present invention.

FIG. 9 is a block diagram showing a flow of processing of display data in the embodiment of the present invention.

FIG. 10 is a flowchart showing a flow of processing by the display control device according to the first embodiment of the present invention.

FIG. 11 is a timing chart of processing by the display control device according to the first embodiment of the present invention.

FIG. 12 is a block diagram showing a display control device according to a second embodiment of the present invention.

13 is a block diagram showing details of the SVGA shown in FIG.

FIG. 14 is a flowchart showing a flow of processing by the display control device of the second embodiment.

FIG. 15 is a block diagram showing a display control device according to a third embodiment of the present invention.

16 is a block diagram showing details of the SVGA shown in FIG.

FIG. 17 is a flowchart showing a flow of processing by the display control device of the third embodiment.

FIG. 18 is a flowchart showing a flow of processing by the display control device according to the fourth embodiment of the present invention.

[Explanation of symbols]

 1, 1A, 1B SVGA 3 VRAM 5, 117 Rewrite detection / flag generation circuit 5A Flag generation circuit 7 Line address generation circuit 9 CPU 10 FLCD interface 11 Binary halftone processing circuit 13 Border generation circuit 15, 17 Synthesis circuit 20 FLCD 21 CPU / FPU 101, 103 FIFO 103 Bus interface unit 105 Data manipulator 107 Graphics engine 109 Memory interface unit 111 VGA 115 Rewrite detection / line address generation circuit 117 Partial rewrite line graph circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tatsuya Sakashita 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Kenichiro Ono 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Eiichi Matsuzaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (5)

[Claims] 1. A display control device of a display device capable of updating a display state only for a display element associated with a display change, and a display data storage unit storing display data, and a display data storage unit stored in the storage unit. A display control circuit capable of sequentially reading display data at a predetermined cycle and transferring the display data to the display device, and partially rewriting the display data stored in the storage means, and the display control circuit. Is a rewriting detection unit for detecting an address accessed by the display data storage unit for the rewriting, and an address detected by the rewriting detection unit is read, and only the display data of the read address is read by the display control circuit. A display control device comprising: a transfer permission unit for permitting transfer. 2. The rewriting detection means has a flag register corresponding to an address of the display data in the display data storage means, sets a flag of the detected address, and the transfer permission means of the flag register. A display control device characterized by reading an address relating to detection from a state of a flag. 3. The display control device according to claim 1, wherein the transfer permission unit permits the transfer in a cycle corresponding to a display drive cycle in the display device. 4. The display control device according to claim 1, wherein the transfer permission unit permits the transfer at a cycle corresponding to a temperature applied to the display device. 5. The display data stored in the display data storage means is multi-valued data that is larger than binary and is binarized when read by the display control circuit and transferred to the display device. The display control device according to claim 1, wherein the display control device is a display control device.