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JPH0682760A - Driving method for ferroelectric liquid crystal display device - Google Patents

Driving method for ferroelectric liquid crystal display device

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Publication number
JPH0682760A
JPH0682760A JP23494392A JP23494392A JPH0682760A JP H0682760 A JPH0682760 A JP H0682760A JP 23494392 A JP23494392 A JP 23494392A JP 23494392 A JP23494392 A JP 23494392A JP H0682760 A JPH0682760 A JP H0682760A
Authority
JP
Japan
Prior art keywords
voltage
liquid crystal
temperature
flc
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23494392A
Other languages
Japanese (ja)
Inventor
Koji Numao
孝次 沼尾
Hirofumi Katsuse
浩文 勝瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP23494392A priority Critical patent/JPH0682760A/en
Publication of JPH0682760A publication Critical patent/JPH0682760A/en
Pending legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE:To improve the display quality at a generally used low temperature by varying the application frequency of both polarity pulses in conformation to the temperature of a FLC panel. CONSTITUTION:A ferroelectric liquid crystal(FLC) display has a scanning side driving circuit 2 connected to the scanning electrode L of a FLC panel 1 and a signal side driving circuit 3 connected to a signal electrode S. The change of transmitted light quantity in a first picture element formed of the scanning electrode to which a non- selective voltage and the signal electrode to which a rewrite voltage is applied is made nearly equal to that of a second picture element formed of the scanning electrode to which the non-selective voltage is applied and the signal electrode to which a holding voltage is applied, and the change of transmitted light quantity in a third picture element formed of the scanning electrode to which a selective voltage is applied and the signal electrode to which the holding voltage is applied is made nearly equal to or smaller than those in the first and second picture elements. According to the temperature of a ferroelectric liquid crystal molecule forming the liquid crystal panel, the application frequency of both polarity pulses to be applied to the first, second and third picture elements is changed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示装置の駆動方法
に関し、特に強誘電性液晶(以下FLCと略称する)パ
ネルの表示装置の駆動方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a liquid crystal display device, and more particularly to a method of driving a display device of a ferroelectric liquid crystal (hereinafter abbreviated as FLC) panel.

【0002】[0002]

【従来の技術】FLCパネルの構成は図3に概略的な断
面図で示されるものである。即ち、2枚のガラス基板5
a,5b は互いに対向させて配置され、一方のガラス基板
5a の表面にはインジウム錫酸化物(以下ITOと略称
する)等からなる透明な信号電極Sが複数本互いに平行
に配置されており、その上はSiO2 等からなる透明な
絶縁膜6a で被覆されている。信号電極Sと対向するも
う一方のガラス基板5bの表面にはITO等からなる透
明な走査電極Lが信号電極Sと直交する向きに複数本互
いに平行に配置されており、その上はSiO2 からなる
透明な絶縁膜6bで被覆されている。
2. Description of the Related Art The structure of an FLC panel is shown in a schematic sectional view in FIG. That is, two glass substrates 5
a and 5b are arranged to face each other, and a plurality of transparent signal electrodes S made of indium tin oxide (hereinafter abbreviated as ITO) or the like are arranged in parallel on the surface of one glass substrate 5a, It is covered with a transparent insulating film 6a made of SiO 2 or the like. On the surface of the other glass substrate 5b facing the signal electrode S, a plurality of transparent scanning electrodes L made of ITO or the like are arranged in parallel to each other in a direction orthogonal to the signal electrode S, and SiO 2 is formed on the transparent scanning electrodes L. Is covered with a transparent insulating film 6b.

【0003】各絶縁膜6a,6b 上にはラビング処理など
施したポリビニルアルコール等からなる透明な配向膜7
a,7b が各々形成されている。この2枚のガラス基板5
a,5b は一部に注入口を残して封止剤8で貼り合わさ
れ、その注入口から配向膜7a,7b で挟まれる空間内に
真空注入によってFLC9が導入された後、上記注入口
は封止剤8で封止される。このようにして貼り合わせた
2枚のガラス基板5a,5b は、互いの偏光軸が直交する
よう配置した2枚の偏光板10a,10b で挟まれてい
る。
A transparent alignment film 7 made of polyvinyl alcohol or the like, which has been subjected to a rubbing treatment, is formed on each of the insulating films 6a and 6b.
a and 7b are formed respectively. These two glass substrates 5
a and 5b are bonded together with a sealant 8 leaving an injection port in part, and after the FLC 9 is introduced by vacuum injection into the space sandwiched between the alignment films 7a and 7b from the injection port, the injection port is sealed. It is sealed with a stopper 8. The two glass substrates 5a and 5b thus bonded together are sandwiched by two polarizing plates 10a and 10b arranged such that their polarization axes are orthogonal to each other.

【0004】図4は、このFLCパネル1の走査電極L
に走査側駆動回路2を接続し、信号電極Sに信号側駆動
回路3を接続したFLCディスプレイ(以下FLCDと
略称する)4の概略的な構成を示す平面図である。ここ
では説明を簡単にする為に走査電極Lが16本で信号電
極Sが16本の場合、つまり16×16の画素で構成さ
れているFLCD4の場合について示しており、走査電
極Lの各々は符号Lに添字i(i=0〜F)を付加して
区別し、信号電極Sの各々は符号Sに添字j(j=0〜
F)を付加して区別している。また、以後の説明では、
任意の走査電極Li と任意の信号電極Sj が交差する部
分の画素を符号Aijで表すものとする。
FIG. 4 shows the scanning electrodes L of the FLC panel 1.
FIG. 3 is a plan view showing a schematic configuration of an FLC display (hereinafter abbreviated as FLCD) 4 in which the scanning side drive circuit 2 is connected to and the signal side drive circuit 3 is connected to the signal electrode S. Here, for simplification of description, the case where the number of scan electrodes L is 16 and the number of signal electrodes S is 16, that is, the case of the FLCD 4 configured by 16 × 16 pixels is shown, and each of the scan electrodes L is shown. The subscript i (i = 0 to F) is added to the reference symbol L for distinction, and each signal electrode S has a subscript j (j = 0 to 0) added to the reference symbol S.
F) is added for distinction. Also, in the following explanation,
A pixel at a portion where an arbitrary scan electrode Li and an arbitrary signal electrode Sj intersect is represented by a symbol Aij.

【0005】この走査側駆動回路2は走査電極Lに電圧
を印加する為の回路であり、図示しないアドレス デコ
ーダーとラッチとアナログ スウィッチから構成され、
指定されたアドレスAx に対応する走査電極Li へ選択
電圧VC1を印加し、それ以外の走査電極Lk(k≠i)
へ非選択電圧VC0を印加する。また信号側駆動回路3は
信号電極Sに電圧を印加する為の回路であり、図示しな
いシフトレジスタとラッチとアナログ スウィッチから
構成され、データDATAが「1」に対応する信号電極
Sへアクテブ電圧VS1を印加し、データDATAが
「0」に対応する信号電極Sへノンアクテブ電圧VS0を
印加する。
The scanning side driving circuit 2 is a circuit for applying a voltage to the scanning electrode L, and is composed of an address decoder, a latch and an analog switch (not shown).
The selection voltage VC1 is applied to the scan electrodes Li corresponding to the designated address Ax, and the other scan electrodes Lk (k ≠ i)
The non-selection voltage VC0 is applied to. The signal side drive circuit 3 is a circuit for applying a voltage to the signal electrode S, and is composed of a shift register (not shown), a latch and an analog switch, and the active voltage VS1 is applied to the signal electrode S corresponding to the data DATA of "1". Is applied, and the non-active voltage VS0 is applied to the signal electrode S corresponding to the data DATA of "0".

【0006】この画素Aijを構成するFLC分子11
は、図5(B)に示すように分子の長軸方向と垂直に自
発分極Ps を持ち、走査電極Lの電圧と信号電極Sの電
圧から作られる電界Eと自発分極Ps のベクトル積に比
例した力を受け2倍のチルト角2θの頂角を持った円錐
12の表面上を移動する。FLC分子11は2つの安定
状態を持ち、電界EによりFLC分子11が図5(A)
に示す軸17まで移動させられると安定状態15とな
り、電界EによりFLC分子11が軸16まで移動させ
られると安定状態14となる性質を持つ。FLC分子1
1をその与えられた安定状態から電界Eにより動かす
と、その安定状態が替わらない限り元の安定状態へ戻ろ
うとする復元力がFLC分子11へ働く。
FLC molecule 11 constituting this pixel Aij
Has a spontaneous polarization Ps perpendicular to the long axis direction of the molecule as shown in FIG. 5B, and is proportional to the vector product of the electric field E generated from the voltage of the scan electrode L and the voltage of the signal electrode S and the spontaneous polarization Ps. It receives the force and moves on the surface of the cone 12 having the apex angle of twice the tilt angle 2θ. The FLC molecule 11 has two stable states, and the electric field E causes the FLC molecule 11 to move as shown in FIG.
When the FLC molecule 11 is moved to the axis 16 by the electric field E, the stable state 15 is obtained. FLC molecule 1
When 1 is moved from the given stable state by the electric field E, a restoring force for returning to the original stable state acts on the FLC molecule 11 unless the stable state is changed.

【0007】一般に、ある温度T°において自発分極P
s と電界EとFLC分子11の回転粘度ηと応答速度τ
との間には τ=k2 (T)×η/(Ps ×E) (1) の関係があると言われている。また、電界EによりFL
C分子11を軸16から軸17または軸17から軸16
へ移動させ、FLC分子11を一方の安定状態からもう
一方の安定状態へ変化させるのに必要なメモリパルス幅
τm と応答速度τとの間には τm =k3 (T,E)×τ (2) の関係があると言われている。
In general, the spontaneous polarization P at a certain temperature T °
s, electric field E, rotational viscosity η of FLC molecule 11 and response speed τ
It is said that there is a relation of τ = k2 (T) × η / (Ps × E) (1) between and. Also, due to the electric field E, FL
C molecule 11 from axis 16 to axis 17 or axis 17 to axis 16
Between the memory pulse width τm and the response speed τ required to change the FLC molecule 11 from one stable state to the other stable state by τm = k3 (T, E) × τ (2 ) Is said to have a relationship.

【0008】実際、チッソ社製の以下の相転移温度を持
つ液晶組成物A K Sc Sa N I 液晶組成物A ・<−20°・ 55° ・67°・73°・ について、温度T=0°〜40°の範囲で応答速度τと
メモリパルス幅τm を測定したのが図6である。
In fact, for a liquid crystal composition A K Sc Sa N I liquid crystal composition A. <-20 ° .55 ° .67 ° .73 °. FIG. 6 shows the response speed τ and the memory pulse width τm measured in the range of 40 °.

【0009】図6から判るように、FLCの応答速度τ
とメモリパルス幅τm の温度依存性は非常に大きい。そ
こで、FLCパネル1に温度センサなどを付け、パネル
の温度に合わせて印加電圧Vやメモリパルス幅τm を変
えていくという特許出願が、例えば特開昭62−118
326等でなされている。
As can be seen from FIG. 6, the FLC response speed τ
And the temperature dependence of memory pulse width τm is very large. Therefore, there is a patent application in which a temperature sensor or the like is attached to the FLC panel 1 and the applied voltage V and the memory pulse width τm are changed according to the temperature of the panel, for example, JP-A-62-118.
It is made in 326 mag.

【0010】しかし、FLC分子には自発分極Ps と電
界Eに比例した力の他に、FLC分子の長軸方向と短軸
方向の誘電率の差Δεと電界Eの2乗に比例した力が働
く。つまりFLC分子に働く力Fは F=k0 ×Ps ×E+k1 ×Δε×E2 (3) となる。そこで誘電異方性Δεが負のFLC材料をパネ
ルへ封止すれば、FLC分子へ働く力は、ある電界Ee
で最大値Fe を持つ。
However, in addition to the force proportional to the spontaneous polarization Ps and the electric field E, the FLC molecule has a force proportional to the square of the electric field E and the difference Δε in the dielectric constant between the major axis direction and the minor axis direction of the FLC molecule. work. That force F acting on FLC molecules becomes F = k0 × Ps × E + k1 × Δε × E 2 (3). Therefore, if an FLC material with a negative dielectric anisotropy Δε is sealed in the panel, the force acting on the FLC molecules will be a certain electric field Ee.
Has the maximum value Fe.

【0011】特願平3−293179の駆動方法は、誘
電異方性Δεが負のFLCDにおいて、FLC分子へ電
界Ee を与える電圧Ve に対して、 V0 /2<Ve (4) なる電圧V0 /2のときFLC分子に働く力F0 F0 =k0 ×Ps ×(E0 /2)+k1 ×Δε×(E0 /2)2 (5) と、 V0 +V1 >Ve (6) なる電圧V0 +V1 のときFLC分子に働く力F1 F1 =k0 ×Ps ×(E0 +E1 )+k1 ×Δε×(E0 +E1 )2 (7) との間に、 F0 =F1 (8) なる関係が成立する電圧V0 /2,V0 +V1 が存在す
ることを利用し、図1の(A)と(B)の電圧波形の組
合せ使って、以下の3つの場合 1)画素を構成するFLC分子を一方の安定状態からも
う一方の安定状態へ書き換える場合、 2)画素を構成するFLC分子をもう一方の安定状態か
ら一方の安定状態へ書き換える場合、 3)画素を構成するFLC分子の安定状態を書き換えな
い場合、を区別し、 1)画素をもう一方の安定状態へ書き換えるときには、
図1(A)の5)の電圧と図1(B)の6)の電圧を画
素に印加し、 2)画素を一方の安定状態へ書き換えるときには、図1
(A)の6)の電圧と図1(B)の5)の電圧を画素に
印加し、 3)画素の安定状態を書き換えないときには、図1
(A)の6)の電圧と図1(B)の6)の電圧を画素に
印加する駆動方法である。
According to the driving method of Japanese Patent Application No. 3-293179, in an FLCD having a negative dielectric anisotropy Δε, a voltage V0 / Ve <4 (4) with respect to a voltage Ve which gives an electric field Ee to FLC molecules, The force acting on the FLC molecule when 2 is F0 F0 = k0 x Ps x (E0 / 2) + k1 x Δε x (E0 / 2) 2 (5) and when the voltage V0 + V1> Ve (6) V0 + V1 FLC molecule The forces V1 F1 = k0 × Ps × (E0 + E1) + k1 × Δε × (E0 + E1) 2 (7) and the voltage V0 / 2, V0 + V1 that satisfies the relationship F0 = F1 (8) Utilizing the existence, by using the combination of voltage waveforms of (A) and (B) of FIG. 1, the following three cases 1) FLC molecules constituting a pixel are changed from one stable state to the other stable state. When rewriting, 2) change the FLC molecule forming the pixel from the other stable state When rewriting to one stable state, 3) when the stable state of the FLC molecule forming the pixel is not rewritten is distinguished, and 1) when rewriting the pixel to the other stable state,
When the voltage of 5) in FIG. 1A and the voltage of 6) in FIG. 1B are applied to the pixel and 2) the pixel is rewritten to one stable state,
When the voltage of 6) in (A) and the voltage of 5) in FIG. 1 (B) are applied to the pixel and 3) the stable state of the pixel is not rewritten,
This is a driving method in which the voltage 6) in (A) and the voltage 6) in FIG. 1B are applied to the pixel.

【0012】図1(A)の1)に示す波形は走査電極L
i へ印加され、その走査電極Li 上の画素Aijを構成す
るFLC分子をもう一方の安定状態へ書き換えることが
できるようにする選択電圧VCAであり、図1(A)の
2)に示す波形は走査電極Lk(i≠k)へ印加され、
その走査電極Lk 上の画素Akjを構成するFLC分子の
安定状態を書き換えないようにする非選択電圧VCBであ
り、図1(A)の3)に示す波形は信号電極Sj へ印加
され、選択電圧VCAが印加されている走査電極Li 上の
画素Aijを構成するFLC分子をもう一方の安定状態へ
書き換えるアクテブ電圧VSCであり、図1(A)の4)
に示す波形は信号電極Sl へ印加され、選択電圧VCAが
印加されている走査電極Li 上の画素Ailを構成するF
LC分子の安定状態を書き換えないノンアクテブ電圧V
SDである。
The waveform shown in 1) of FIG. 1A is the scanning electrode L.
is a selection voltage VCA applied to i to rewrite the FLC molecule forming the pixel Aij on the scan electrode Li to the other stable state, and the waveform shown in 2) of FIG. Applied to the scan electrode Lk (i ≠ k),
The non-selection voltage VCB that prevents the stable state of the FLC molecules constituting the pixel Akj on the scan electrode Lk from being rewritten. The waveform shown in 3) of FIG. 1A is applied to the signal electrode Sj and the selection voltage This is the active voltage VSC for rewriting the FLC molecules constituting the pixel Aij on the scan electrode Li to which VCA is applied to the other stable state, which is 4) in FIG. 1A.
The waveform shown in FIG. 4 is applied to the signal electrode Sl and F constituting the pixel Ail on the scan electrode Li to which the selection voltage VCA is applied.
Non-active voltage V that does not rewrite the stable state of LC molecules
It is SD.

【0013】図1(A)の5)に示す波形は走査電極L
i へ選択電圧VCAが印加され、信号電極Sj へアクテブ
電圧VSCが印加されたとき、画素Aijを構成するFLC
分子をもう一方の安定状態へ書き換える電圧A−Cであ
り、図1(A)の6)に示す波形は走査電極Li へ選択
電圧VCAが印加され、信号電極Sl へノンアクテブ電圧
VSDが印加されたとき、画素Ailを構成するFLC分子
の安定状態を書き換えない電圧A−Dであり、図1
(A)の7)に示す波形は走査電極Lkへ非選択電圧V
CBが印加され、信号電極Sj へアクテブ電圧VSCが印加
されたとき、画素Akjを構成するFLC分子へ印加され
る電圧B−Cであり、図1(A)の8)に示す波形は走
査電極Lkへ非選択電圧VCBが印加され、信号電極Sl
へノンアクテブ電圧VSDが印加されたとき、画素Aklを
構成するFLC分子へ印加される電圧B−Dである。
The waveform shown at 5) in FIG. 1A is the scanning electrode L.
The FLC forming the pixel Aij when the selection voltage VCA is applied to i and the active voltage VSC is applied to the signal electrode Sj.
A voltage AC for rewriting the numerator to the other stable state. The waveform shown in 6) of FIG. 1 (A) has the selection voltage VCA applied to the scanning electrode Li and the non-active voltage VSD applied to the signal electrode Sl. At this time, the voltage A-D that does not rewrite the stable state of the FLC molecule forming the pixel Ail is shown in FIG.
The waveform shown in 7) of (A) is applied to the non-selection voltage V to the scan electrode Lk.
When CB is applied and the active voltage VSC is applied to the signal electrode Sj, it is the voltage B-C applied to the FLC molecules forming the pixel Akj. The waveform shown in 8) of FIG. The non-selection voltage VCB is applied to Lk, and the signal electrode Sl
When the non-active voltage VSD is applied to the FLC molecules, the voltage BD is applied to the FLC molecules constituting the pixel Akl.

【0014】図1(B)の1)に示す波形は走査電極L
i へ印加され、その走査電極Li 上の画素Aijを構成す
るFLC分子を一方の安定状態へ書き換えることができ
るようにする選択電圧VCAであり、図1(B)の2)に
示す波形は走査電極Lk (i≠k)へ印加され、その走
査電極Lk 上の画素Akjを構成するFLC分子の安定状
態を書き換えないようにする非選択電圧VCBであり、図
1(B)の3)に示す波形は信号電極Sj へ印加され、
選択電圧VCAが印加されている走査電極Li 上の画素A
ijを構成するFLC分子を一方の安定状態へ書き換える
アクテブ電圧VSCであり、図1(B)の4)に示す波形
は信号電極Sl へ印加され、選択電圧VCAが印加されて
いる走査電極Li 上の画素Ailを構成するFLC分子の
安定状態を書き換えないノンアクテブ電圧VSDである。
The waveform shown in 1) of FIG. 1B is the scanning electrode L.
is a selection voltage VCA applied to i to rewrite the FLC molecules constituting the pixel Aij on the scan electrode Li to one stable state, and the waveform shown in 2) of FIG. The non-selection voltage VCB applied to the electrode Lk (i ≠ k) so as not to rewrite the stable state of the FLC molecule forming the pixel Akj on the scan electrode Lk, which is shown in 3) of FIG. 1B. The waveform is applied to the signal electrode Sj,
The pixel A on the scan electrode Li to which the selection voltage VCA is applied
The active voltage VSC that rewrites the FLC molecules forming ij to one stable state. The waveform shown in 4) of FIG. 1B is applied to the signal electrode Sl and the selection voltage VCA is applied to the scanning electrode Li. Is the non-active voltage VSD that does not rewrite the stable state of the FLC molecule that constitutes the pixel Ail.

【0015】図1(B)の5)に示す波形は走査電極L
i へ選択電圧VCAが印加され、信号電極Sj へアクテブ
電圧VSCが印加されたとき、画素Aijを構成するFLC
分子を一方の安定状態へ書き換える電圧A−Cであり、
図1(B)の6)に示す波形は走査電極Li へ選択電圧
VCAが印加され、信号電極Sl へノンアクテブ電圧VSD
が印加されたとき、画素Ailを構成するFLC分子の安
定状態を書き換えない電圧A−Dであり、図1(B)の
7)に示す波形は走査電極Lk へ非選択電圧VCBが印加
され、信号電極Sj へアクテブ電圧VSCが印加されたと
き、画素Akjを構成するFLC分子へ印加される電圧B
−Cであり、図1(B)の8)に示す波形は走査電極L
k へ非選択電圧VCBが印加され、信号電極Sl へノンア
クテブ電圧VSDが印加されたとき、画素Aklを構成する
FLC分子へ印加される電圧B−Dである。
The waveform shown in 5) of FIG. 1 (B) is the scanning electrode L.
The FLC forming the pixel Aij when the selection voltage VCA is applied to i and the active voltage VSC is applied to the signal electrode Sj.
The voltage A-C that rewrites the molecule to one stable state,
In the waveform shown in 6) of FIG. 1B, the selection voltage VCA is applied to the scan electrode Li and the non-active voltage VSD is applied to the signal electrode Sl.
Is a voltage A-D that does not rewrite the stable state of the FLC molecules forming the pixel Ail, and the waveform shown in 7) of FIG. 1B has a non-selection voltage VCB applied to the scan electrode Lk. When the active voltage VSC is applied to the signal electrode Sj, the voltage B applied to the FLC molecules forming the pixel Akj
-C, and the waveform shown in 8) of FIG.
The voltages BD are applied to the FLC molecules constituting the pixel Akl when the non-selection voltage VCB is applied to k and the non-active voltage VSD is applied to the signal electrode Sl.

【0016】このように画素へ印加する電圧波形を決め
れば、特願平3−293179の駆動方法において、画
素を書き換えない限り、画素へは図1(A)または
(B)の6)の電圧波形や図1(A)の7)か8)また
は図1(B)の7)か8)の電圧波形が印加される。
By thus determining the voltage waveform to be applied to the pixel, in the driving method of Japanese Patent Application No. 3-293179, the voltage of 6) in FIG. 1A or 1B is applied to the pixel unless the pixel is rewritten. The waveform or the voltage waveform of 7) or 8) of FIG. 1A or 7) or 8) of FIG. 1B is applied.

【0017】予め、電圧V0 /2のときFLC分子に働
く力F0 と電圧V0 +V1 のときFLC分子に働く力F
1 がほぼ等しくなるよう電圧V0 /2とV0 +V1 を決
めているので、図1(A)または(B)の6)の電圧波
形を画素を構成するFLC分子に印加したときの画素の
透過光量の変化と、図1(A)の7)か8)または図1
(B)の7)か8)の電圧波形を画素を構成するFLC
分子に印加したときの画素の透過光量の変化はほぼ等し
いはずであり、画素を書き換えるない限り書換え周波数
に依らずフリッカのない画像表示が得られる。
The force F0 acting on the FLC molecule when the voltage V0 / 2 and the force F acting on the FLC molecule when the voltage V0 + V1 are applied in advance.
Since the voltages V0 / 2 and V0 + V1 are determined so that 1 becomes almost equal, the amount of light transmitted through the pixel when the voltage waveform of 6) in FIG. 1A or 1B is applied to the FLC molecule forming the pixel. Changes and 7) or 8) of FIG. 1 (A) or FIG.
FLC that configures the pixel with the voltage waveform of 7) or 8) of (B)
The change in the amount of transmitted light of the pixel when applied to the molecule should be almost equal, and flicker-free image display can be obtained regardless of the rewriting frequency unless the pixel is rewritten.

【0018】[0018]

【発明が解決しようとする課題】誘電異方性Δεが負の
FLC分子へ働く力が最大となる電界Ee は、パネルへ
印加する電圧VとFLCの応答速度τまたはメモリパル
ス幅τm の関係を調べ、その応答速度τまたはメモリパ
ルス幅τm が最小となる電圧Ve とパネルのセル厚から
判る。
The electric field Ee that maximizes the force exerted on FLC molecules having a negative dielectric anisotropy Δε is expressed by the relationship between the voltage V applied to the panel and the response speed τ of the FLC or the memory pulse width τm. This can be understood from the voltage Ve at which the response speed τ or the memory pulse width τm becomes the minimum and the cell thickness of the panel.

【0019】そこで、BDH社の液晶組成物SCE−8
に誘電異方性が負の化合物Bを添加した以下の転移温度
を示す液晶組成物B について、温度T=25°〜50°の範囲で印加電圧V
とメモリパルス幅τm の関係を調べたのが図7である。
Therefore, the liquid crystal composition SCE-8 manufactured by BDH
Liquid crystal composition B having the following transition temperature in which compound B having a negative dielectric anisotropy is added to Applied voltage V in the range of temperature T = 25 ° to 50 °
FIG. 7 shows the relationship between the pulse width and the memory pulse width τ m.

【0020】図7からメモリパルス幅τm の温度依存性
は非常に大きが、メモリパルス幅τm が最小となる電圧
Ve の温度依存性は非常に小さいことが判る。この結果
から、特願平3−293179の駆動方法においては、
パネルの温度が変化しても電圧V0 /2とV0 +V1 は
あまり変化させる必要はないが、メモリパルス幅τm は
温度により大きく変化させる必要があることが判る。こ
のような誘電異方性が負の駆動方法において、特開昭6
2−118326等のように、パネルの温度に合わせて
印加電圧Vやメモリパルス幅τm を変えていては、温度
が高くなるほど(電圧Vはほぼ一定なのだから)メモリ
パルス幅τmを小さくしなければならない。
It can be seen from FIG. 7 that the temperature dependence of the memory pulse width τm is very large, but the temperature dependence of the voltage Ve at which the memory pulse width τm is minimum is very small. From this result, in the driving method of Japanese Patent Application No. 3-293179,
It is understood that the voltages V0 / 2 and V0 + V1 do not need to change much even if the temperature of the panel changes, but the memory pulse width .tau.m needs to change greatly depending on the temperature. In such a driving method in which the dielectric anisotropy is negative, Japanese Patent Laid-Open No.
2-118326, etc., if the applied voltage V and the memory pulse width τm are changed according to the temperature of the panel, the memory pulse width τm must be reduced as the temperature rises (since the voltage V is almost constant). I won't.

【0021】ところが、液晶パネルは電気的にコンデン
サと同様に扱えるから、液晶パネルへ印加される電圧v
を v=Va ×sin (2πft) (9) とすると、容量Cの液晶パネルへ供給される電流iは i=C×dv/dt=2πfCVa ×cos (2πft) (10) となり、周波数fが高いほど多くの電流が必要となる。
However, since the liquid crystal panel can be electrically treated like a capacitor, the voltage v applied to the liquid crystal panel is
Where v = Va × sin (2πft) (9), the current i supplied to the liquid crystal panel of the capacitance C is i = C × dv / dt = 2πfCVa × cos (2πft) (10), and the frequency f is high. More current is needed.

【0022】つまり、誘電異方性が負の駆動方法におい
て、従来のように温度が高くなるに従いメモリパルス幅
τm を小さくする考えでは、温度が高くなるほど走査側
駆動回路2と信号側駆動回路3から大きな電流を供給す
る必要がある。
That is, in the driving method in which the dielectric anisotropy is negative, in consideration of reducing the memory pulse width τm as the temperature rises as in the conventional case, the scanning side drive circuit 2 and the signal side drive circuit 3 increase as the temperature rises. It is necessary to supply a large current from.

【0023】しかし、一般に半導体内での発熱量は電流
供給量に比例して大きくなり、半導体からの放熱量は周
囲温度が高くなるほど小さくなる。その結果、半導体の
電流供給能力は周囲温度が高くなるほど小さくなる。例
えばNEC社製のオペアンプμPC157Dの出力電流
はカタログにおいて図8のように示されている。
However, the amount of heat generated in the semiconductor generally increases in proportion to the amount of current supplied, and the amount of heat released from the semiconductor decreases as the ambient temperature rises. As a result, the current supply capability of the semiconductor decreases as the ambient temperature increases. For example, the output current of the NEC operational amplifier μPC157D is shown in the catalog as shown in FIG.

【0024】このような半導体の出力電流特性を考える
と、誘電異方性が負の駆動方法において、温度が高くな
るに従いメモリパルス幅τm を小さくする為には、逆に
最初に動作最高温度での印加電圧の周期2t0 を決め、
その温度でのメモリパルス幅τm から図1のパルスの印
加回数Nを決めなければならない。しかし、図8の半導
体の電流供給能力の温度変化に較べ、図6に示すFLC
パネルのメモリパルス幅τm の温度変化は非常に大きい
ので、動作最高温度での印加電圧の周期2t0とメモリ
パルス幅τm の比は小さく、印加回数Nが小さくなるの
で、動作温度が低くなっても(印加回数Nが大きくでき
るのに)印加回数Nが一定だとコントラストが悪いまま
であるという問題がある。本発明はこのような問題点に
対してなされたものである。
Considering the output current characteristics of such a semiconductor, in the driving method in which the dielectric anisotropy is negative, in order to reduce the memory pulse width τm as the temperature increases, conversely, first, at the maximum operating temperature, The period 2t0 of the applied voltage of
From the memory pulse width τm at that temperature, the number of pulse application times N of FIG. 1 must be determined. However, compared with the temperature change of the current supply capacity of the semiconductor shown in FIG. 8, the FLC shown in FIG.
Since the temperature variation of the memory pulse width τm of the panel is very large, the ratio of the period 2t0 of the applied voltage at the maximum operating temperature to the memory pulse width τm is small, and the number of times N of application is small, so even if the operating temperature becomes low If the number of applications N is constant (even though the number of applications N can be increased), the contrast remains poor. The present invention has been made to solve such a problem.

【0025】[0025]

【課題を解決するための手段】この発明は、互いに交差
する方向に配列した複数の走査電極と複数の信号電極と
の間に誘電異方性が負の強誘電性液晶を介在させ、走査
電極に選択電圧又は非選択電圧を選択的に印加すると共
に、信号電極に書換え電圧又は保持電圧を選択的に印加
して走査電極と信号電極とが交差する領域の各画素の表
示を変化させるようにした液晶表示装置の駆動方法であ
って、非選択電圧を印加した走査電極と書換え電圧を印
加した信号電極から構成される第1画素と、非選択電圧
を印加した走査電極と保持電圧を印加した信号電極から
構成される第2画素へ、正電圧と負電圧から構成される
両極性パルスを複数回印加し、第1および第2画素の透
過光量の変化をほぼ等しくし、選択電圧を印加した走査
電極と保持電圧を印加した信号電極から構成される第3
画素へ、強誘電性液晶分子に働く誘電異方性負の効果が
大きな領域の正又は負電圧と、強誘電性液晶分子に働く
誘電異方性負の効果が小さな領域の負又は正電圧から構
成される両極性パルスを複数回印加し、第3画素の透過
光量の変化を第1及び第2画素の透過光量の変化にほぼ
等しくするか、またはそれより小さくすると共に、液晶
パネルを構成する強誘電性液晶分子の温度に合わせて、
第1、第2及び第3画素へ印加する両極性パルスの印加
回数を変化させることにより、前述の問題点を解決する
ことを特徴とする液晶表示装置の駆動方法を与えるもの
である。
According to the present invention, a ferroelectric liquid crystal having a negative dielectric anisotropy is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in directions intersecting with each other, and To selectively apply the selection voltage or the non-selection voltage to the signal electrode and selectively apply the rewriting voltage or the holding voltage to the signal electrode to change the display of each pixel in the region where the scan electrode and the signal electrode intersect. In the driving method of the liquid crystal display device, a first pixel including a scan electrode to which a non-selection voltage is applied and a signal electrode to which a rewriting voltage is applied, a scan electrode to which a non-selection voltage is applied, and a holding voltage are applied. A bipolar pulse composed of a positive voltage and a negative voltage was applied to the second pixel composed of the signal electrode a plurality of times to make the changes in the transmitted light amount of the first and second pixels substantially equal, and a selection voltage was applied. Scan electrode and holding voltage The third consists of pressurizing the signal electrodes
To the pixel, from the positive or negative voltage in the region where the negative effect of the dielectric anisotropy acting on the ferroelectric liquid crystal molecule is large and the negative or positive voltage in the region where the negative effect of the negative dielectric anisotropy acting on the ferroelectric liquid crystal molecule is small. By applying the constituted bipolar pulse a plurality of times to make the change in the amount of transmitted light of the third pixel substantially equal to or smaller than the change in the amount of transmitted light of the first and second pixels, and to configure the liquid crystal panel. According to the temperature of the ferroelectric liquid crystal molecules,
The present invention provides a method for driving a liquid crystal display device, which solves the above-mentioned problems by changing the number of times of application of bipolar pulses applied to the first, second and third pixels.

【0026】[0026]

【作用】FLC分子のメモリパルス幅τm や応答速度τ
の温度依存性が非常に大きいのは、一般に(1)式から
自発分極Ps か回転粘度ηの温度依存性が非常に大きい
為と予想できる。ところが、従来例の液晶組成物Aのメ
モリパルス幅τm や応答速度τの温度依存性は図4のよ
うに数倍以上のオーダーで変化するのに対し、自発分極
Ps の温度依存性を調べると図9のように数割のオーダ
ーでしか変化しかない。
[Function] Memory pulse width τ m and response speed τ of FLC molecule
It can be expected that the temperature dependence of is very large in general because of the very large temperature dependence of the spontaneous polarization Ps or the rotational viscosity η from the equation (1). However, while the temperature dependence of the memory pulse width τm and the response speed τ of the liquid crystal composition A of the conventional example changes in the order of several times or more as shown in FIG. 4, the temperature dependence of the spontaneous polarization Ps is examined. As shown in FIG. 9, it changes only on the order of several tenths.

【0027】このことから、FLC分子のメモリパルス
幅τm や応答速度τの温度依存性が非常に大きいのは回
転粘度ηの温度依存性が非常に大きい為と結論づけられ
る。また、従来例の液晶組成物Bの電圧V−メモリパル
ス幅τm 特性の温度依存性は図7のようになり、FLC
分子へ働く力が最小となる電圧Ve の温度依存性があま
り見られない。この事と、FLC分子に働く力が(3)
式で表され、図9のようにFLC分子の自発分極Ps の
温度依存性が小さい事から、誘電異方性Δεの温度依存
性も小さいはずであり、(8)式を満たす電圧V0 /2
と電圧V0 +V1 の温度依存性も小さいはずだというこ
とが予想できる。
From this, it can be concluded that the memory pulse width τ m and response speed τ of FLC molecules have a very large temperature dependence because the rotational viscosity η has a very large temperature dependence. Further, the temperature dependence of the voltage V-memory pulse width τm characteristic of the liquid crystal composition B of the conventional example is as shown in FIG.
The temperature dependence of the voltage Ve at which the force acting on the molecule is minimized is not seen so much. This and the force acting on the FLC molecule is (3)
Since the temperature dependence of the spontaneous polarization Ps of the FLC molecule is small as shown in FIG. 9, the temperature dependence of the dielectric anisotropy Δε should also be small, and the voltage V0 / 2 satisfying the formula (8)
It can be expected that the temperature dependence of the voltage V0 + V1 should be small.

【0028】そこで、FLCパネル1の動作温度をT0
°〜T1 °とし電圧V0 /2と電圧V0 +V1 をパネル
温度に依らず一定とする。まず、両極性パルスのパルス
幅t0 を決める。動作最高温度T1 °をFLCに与える
周囲温度T3 °において、走査側駆動回路2と信号側駆
動回路3から供給できる電流i0 により、FLCパネル
1の1本の走査電極上の全画素を電圧V0/2から電圧
−(V0 +V1 )へ、または電圧−(V0 +V1 )から
電圧V0 /2へ充電するのに必要な時間をt1 とする
と、時間t0 は t0 >t1 (11) であれば良い。
Therefore, the operating temperature of the FLC panel 1 is set to T0.
The voltage V0 / 2 and the voltage V0 + V1 are kept constant regardless of the panel temperature. First, the pulse width t0 of the bipolar pulse is determined. At the ambient temperature T3 ° at which the maximum operating temperature T1 ° is given to the FLC, the current i0 that can be supplied from the scanning side driving circuit 2 and the signal side driving circuit 3 causes all the pixels on one scanning electrode of the FLC panel 1 to have the voltage V0 / Assuming that the time required for charging from 2 to the voltage-(V0 + V1) or from the voltage-(V0 + V1) to the voltage V0 / 2 is t1, the time t0 may be t0> t1 (11).

【0029】時間t0 をパネル温度に依らず一定とし、
あるパネル温度Tp °における両極性パルスの印加回数
をPとすると、図1(A)または図1(B)の5)の書
き換える画素へ印加する電圧波形A−Cの絶対値の時間
積Wp は Wp =(V1 +V0 /2)×P×t0 (12) となる。
The time t0 is constant regardless of the panel temperature,
Assuming that the number of times the bipolar pulse is applied at a certain panel temperature Tp ° is P, the time product Wp of the absolute values of the voltage waveforms A-C applied to the pixel to be rewritten in FIG. 1A or 5B is Wp = (V1 + V0 / 2) .times.P.times.t0 (12).

【0030】その温度Tp °での両極性パルスの最小印
加回数Pは、その温度Tp °における印加電圧Vm とメ
モリパルス幅τm の関係より Wp >Vm ×τm >(V0 /2)×t0 (13) なる整数の最小値である。
The minimum number P of times the bipolar pulse is applied at the temperature Tp ° is Wp> Vm × τm> (V0 / 2) × t0 (13) from the relationship between the applied voltage Vm and the memory pulse width τm at the temperature Tp °. ) Is the minimum integer.

【0031】温度Tp °においては、両極性パルスの印
加回数NはP以上であれば問題がなく、 Tp <Tr (14) なる温度Tr でも、(時間積は温度と共に減少するのだ
から)両極性パルスの印加回数NはP以上であれば問題
がない。
At the temperature Tp °, there is no problem if the number N of times of application of the bipolar pulse is P or more, and even at the temperature Tr where Tp <Tr (14), the bipolar property is decreased because the time product decreases with temperature. There is no problem if the pulse application count N is P or more.

【0032】そこで、パネルの温度が下がっているとき
は、 Tp ≦T (15) なる温度Tで両極性パルスの印加回数NはPとし、 T<Tp (16) なる温度Tで両極性パルスの印加回数NはP+1とし、
パネルの温度が上がっているときは、 T<Tr (17) なる温度Tで両極性パルスの印加回数NはP+1とし、 Tr ≦T (18) なる温度Tで両極性パルスの印加回数NはPとする。
Therefore, when the temperature of the panel is lowered, the number of times N of application of the bipolar pulse is set to P at the temperature T of Tp≤T (15), and the bipolar pulse is applied at the temperature T of T <Tp (16). The number of application times N is P + 1,
When the temperature of the panel is rising, the number of times N of application of the bipolar pulse is set to P + 1 at the temperature T of T <Tr (17), and the number of application N of the bipolar pulse is set to P + 1 at the temperature T of Tr ≤T (18). And

【0033】このようにすれば、FLC分子に温度T0
°〜T1 °を与える周囲温度T2 °〜T3 °において、
その温度で走査側駆動回路2と信号側駆動回路3から供
給できる電流iにより、FLCパネル1へ図1の(A)
や(B)の電圧波形の組合せが印加可能となり、FLC
パネル1は正常な動作が保証される。また、FLCパネ
ルの選択期間の変化を両極性パルスの印加時間の変化よ
り小さくすれば、温度が高くなるほど0v印加の期間が
長くなり走査側駆動回路2と信号側駆動回路3の発熱量
を抑え、駆動回路からの電流供給能力を向上できる。
In this way, the FLC molecule has a temperature T0.
At ambient temperature T2 ° to T3 °, which gives ° to T1 °,
By the current i that can be supplied from the scanning side driving circuit 2 and the signal side driving circuit 3 at that temperature, the FLC panel 1 is supplied to the FLC panel 1 as shown in FIG.
And (B) voltage waveform combinations can be applied, and FLC
The panel 1 is guaranteed to operate normally. If the change in the selection period of the FLC panel is made smaller than the change in the application time of the bipolar pulse, the period of 0v application becomes longer as the temperature rises, and the heat generation amount of the scanning side drive circuit 2 and the signal side drive circuit 3 is suppressed. The current supply capacity from the drive circuit can be improved.

【0034】[0034]

【実施例】本実施例で用いられるFLCパネル1の構成
は図3に示す従来例と同じであるので、ここではその説
明は省略する。なお本実施例のFLCパネル1では配向
膜としてチッソ社製の配向膜PSI−X7355を用
い、液晶としてBDH社の液晶組成物SCE−8に誘電
異方性が負の化合物Bを8:2の割合で混合した液晶組
成物Bを用いている。
EXAMPLE Since the structure of the FLC panel 1 used in this example is the same as that of the conventional example shown in FIG. 3, its explanation is omitted here. In the FLC panel 1 of this example, an alignment film PSI-X7355 manufactured by Chisso Co. was used as an alignment film, and a liquid crystal composition SCE-8 manufactured by BDH was used as a liquid crystal with a compound B having a negative dielectric anisotropy of 8: 2. The liquid crystal composition B mixed at a ratio is used.

【0035】本実施例で用いる1つの温度検出手段は、
図10ののように出力電圧Vt の定電圧源18とサーミ
スタ19と抵抗値Rt の定抵抗22とオペアンプ20と
アナログ/デジタル変換器21より構成されており、サ
ーミスタ19をFLCパネル1へ接触させ、そのサーミ
スタ19の抵抗値Rs が例えば図11に示すダイオード
型サーミスタのように温度に依って変化することによ
り、オペアンプ20の出力電圧Vが V=Vt ×Rs /(Rs +Rt ) (19) と変化することで検出するものである。
One temperature detecting means used in this embodiment is
As shown in FIG. 10, it comprises a constant voltage source 18 of output voltage Vt, a thermistor 19, a constant resistance 22 of resistance value Rt, an operational amplifier 20 and an analog / digital converter 21. The thermistor 19 is brought into contact with the FLC panel 1. , The resistance value Rs of the thermistor 19 changes depending on the temperature like the diode type thermistor shown in FIG. 11, so that the output voltage V of the operational amplifier 20 becomes V = Vt × Rs / (Rs + Rt) (19) It is detected by changing.

【0036】本実施例で用いる別の温度検出手段は、図
12に示すように光/電圧変換器23とアンプ24とロ
ーパスフィルタ25とデジタル化回路26と検出回路2
7と電圧制御回路28と電圧制御発振器29とカウンタ
30と電圧発生器31と減衰器32から構成される検出
器である。
Another temperature detecting means used in this embodiment is, as shown in FIG. 12, a light / voltage converter 23, an amplifier 24, a low pass filter 25, a digitizing circuit 26 and a detecting circuit 2.
7, a voltage control circuit 28, a voltage controlled oscillator 29, a counter 30, a voltage generator 31, and an attenuator 32.

【0037】この検出器は、電圧制御回路28から入力
された電圧によって電圧制御発振器29からクロックC
Pを発生させ、カウンタ回路30でクロックCPの周期
の一定倍数の時間2×tk をつくり、この時間2×tk
の複数倍の時間をフィールド周期Tf とし、偶数番目の
フィールドでは電圧Vthをtk 時間出力後、電圧−Vth
をtk 時間出力し、その後は電圧0を出力しする。奇数
番目のフィールドでは電圧−Vthをtk 時間出力後、電
圧Vthをtk 時間出力し、その後は電圧0を出力する。
この電圧波形は減衰器31で減衰されFLCパネル1の
図示しない専用電極に印加される。なお、減衰器31の
減衰率は実際にパネル全体が書換えられるかを見ながら
決められる。
This detector uses a voltage input from the voltage control circuit 28 to output a clock C from the voltage controlled oscillator 29.
P is generated, and the counter circuit 30 creates a time 2 × tk which is a constant multiple of the cycle of the clock CP, and this time 2 × tk
Is set to a field cycle Tf, and in the even-numbered field, the voltage Vth is output for tk time and then the voltage -Vth.
Is output for tk time, and then voltage 0 is output. In the odd-numbered field, the voltage -Vth is output for tk time, the voltage Vth is output for tk time, and then the voltage 0 is output.
This voltage waveform is attenuated by the attenuator 31 and applied to a dedicated electrode (not shown) of the FLC panel 1. The attenuation factor of the attenuator 31 is determined by actually rewriting the entire panel.

【0038】このようにして、パネルの一部の画素を周
期的に「明」「暗」の状態にして、この時のパネルの透
過光量を光/電圧変換器23で検値してアナログ電圧に
変え、アンプ24でこの電圧を増幅し、このフィールド
周期Tf に近い周波数を取り出すためのローパスフィル
タ25を通して、デジタル化回路26に入力する。デジ
タル化回路26では数フィールドに渡る入力電圧の平均
値を基準にして、その電圧より入力電圧が高いか低いか
により入力電圧をデジタル信号に変換する。この信号は
検出回路27に入力され、検出回路27では入力された
信号を1フィールドに1回サンプリングし、前後のフィ
ールドで値が違えば電圧制御回路28の出力電圧を少し
低くして電圧制御発振器29の出力クロックCPの周波
数を高くし、前後のフィールドで値が同じならば電圧制
御回路28の出力電圧を少し高くして電圧制御発振器2
9の出力クロックCPの周波数を低くする。
In this way, some pixels of the panel are periodically set to the "bright" and "dark" states, and the amount of transmitted light of the panel at this time is measured by the light / voltage converter 23 to obtain an analog voltage. Then, the voltage is amplified by the amplifier 24 and input to the digitizing circuit 26 through the low pass filter 25 for extracting the frequency close to the field period Tf. The digitizing circuit 26 converts the input voltage into a digital signal depending on whether the input voltage is higher or lower than the average value of the input voltage over several fields. This signal is input to the detection circuit 27, and the detection circuit 27 samples the input signal once per field, and if the values in the preceding and following fields are different, the output voltage of the voltage control circuit 28 is lowered a little and the voltage control oscillator is generated. The frequency of the output clock CP of 29 is increased, and if the values in the preceding and following fields are the same, the output voltage of the voltage control circuit 28 is increased a little and the voltage controlled oscillator 2
The frequency of the output clock CP of 9 is lowered.

【0039】この時の、パネルへの印加電圧を示したの
が図13の1),3)であり、図13の1),3)に対
応する予想される透過光量を示したのが図13の2),
4)である。図13の1)ではパネルに電圧Vthが印加
される時間がパネルの閾値を越え、図13の3)に示す
ようにパネルの透過光量は十分変化するが、図13の
3)ではパネルに電圧Vthが印加される時間がパネルの
閾値を越えず、図13の4)に示すようにパネルの透過
光量は十分変化しない。減衰器32から出力される電圧
Vthの印加時間は図13の1)と3)の間を行ったり来
たりするが、その中心となる時間は電圧Vthでのパネル
のメモリパルス幅τm 自体であり、パネル内の液晶の温
度を正確に示す。
The voltages applied to the panel at this time are shown in 1) and 3) of FIG. 13, and the expected amount of transmitted light corresponding to 1) and 3) of FIG. 13 is shown in the figure. 13-2),
4). In 1) of FIG. 13, the time when the voltage Vth is applied to the panel exceeds the threshold of the panel, and the transmitted light amount of the panel changes sufficiently as shown in 3) of FIG. 13, but in 3) of FIG. The time for which Vth is applied does not exceed the threshold value of the panel, and the amount of transmitted light of the panel does not change sufficiently as shown in 4) of FIG. The application time of the voltage Vth output from the attenuator 32 fluctuates between 1) and 3) in FIG. 13, but the central time is the memory pulse width τm itself of the panel at the voltage Vth. , Accurately indicate the temperature of the liquid crystal in the panel.

【0040】つまり、このフィールド周期Tf をFLC
Dのシステムクロックでカウントすれば、パネル内の液
晶の温度を検出できる。本実施例のFLCパネル1の電
圧V−メモリパルス幅τm 特性は図7の通りなので、電
圧V0 /2とV0 +V1 は V0 /2=12v V1 +V0 =30v と決まった。FLCパネル1の動作温度を25°〜50
°とすれば、パネル温度が50°のとき走査側駆動回路
2と信号側駆動回路3からFLCパネル1に供給される
電圧波形の立ち上がり観測し、時間t0 はt0 =30μ
sと決まった。また、5°刻みの各温度における両極性
パルスの最小印加回数Pは図7より、 温度Tp 25° 30° 35° 40° 45° 50° 最小印加回数P 12 8 5 4 3 2 となる。
That is, this field period Tf is set to FLC.
If the system clock of D is counted, the temperature of the liquid crystal in the panel can be detected. Since the voltage V-memory pulse width .tau.m characteristic of the FLC panel 1 of this embodiment is as shown in FIG. 7, the voltages V0 / 2 and V0 + V1 were determined to be V0 / 2 = 12v V1 + V0 = 30v. The operating temperature of the FLC panel 1 is 25 ° to 50 °
When the panel temperature is 50 °, the rise of the voltage waveform supplied from the scanning side drive circuit 2 and the signal side drive circuit 3 to the FLC panel 1 is observed, and the time t0 is t0 = 30μ.
It was decided to be s. Further, the minimum number of times P of application of the bipolar pulse at each temperature in steps of 5 ° is as follows from the temperature Tp 25 ° 30 ° 35 ° 40 ° 45 ° 50 ° Minimum number of times of application P 12 8 5 4 3 2.

【0041】そこで、温度Tp °にパネルの温度が低下
したときの両極性パルスの印加回数を、温度Tp −5°
における両極性パルスの最小印加回数Pと決め、温度T
p +2°にパネルの温度が上昇したときの両極性パルス
の印加回数を温度Tp °における両極性パルスの最小印
加回数Pと決める。つまり、各温度における両極性パル
スの許容印加回数Qは、 温度Tp 25°30° 32°35° 37°40° 42° 許容印加回数Q ・12・12〜8・ 8・8〜5・ 5・5〜4・ 4 温度Tp 42°45° 47°50° 許容印加回数Q ・ 4・4〜3・ 3・ となる。
Therefore, when the temperature of the panel is lowered to the temperature Tp °, the number of times the bipolar pulse is applied is set to the temperature Tp-5 °.
Determine the minimum number of times P of application of bipolar pulse in
The number of times the bipolar pulse is applied when the temperature of the panel rises to p + 2 ° is determined as the minimum number of times P of application of the bipolar pulse at the temperature Tp °. That is, the allowable number of times Q of applying the bipolar pulse at each temperature is as follows: temperature Tp 25 ° 30 ° 32 ° 35 ° 37 ° 40 ° 42 ° allowable number of applications Q ・ 12 ・ 12〜8 ・ 8.8 ・ 8 ・ 5 ・ 5 ・5-4. 4 Temperature Tp 42 ° 45 ° 47 ° 50 ° Allowable number of times of application Q. 4 · 4 to 4 · 3 · 3.

【0042】温度検出手段により検出した温度データD
T を、図14に示す入力制御回路33と出力制御回路3
4と表示メモリ回路35と識別メモリ回路36と同異メ
モリ回路37と駆動制御回路38から構成されるコント
ロール回路39のうち、図15に示す駆動信号回路40
とROM41と駆動電圧回路42から構成される駆動制
御回路38へ入力する。図15の駆動制御回路38で
は、現在の両極性パルスの印加回数Nが検出した温度デ
ータDT における印加許容回数Qと違えば、NとDT に
より駆動信号回路40からROM41へ新たな電圧波形
の組合せのアドレスが出力され、新たな電圧波形の組合
せがFLCD4へ出力される。
Temperature data D detected by the temperature detecting means
T is the input control circuit 33 and the output control circuit 3 shown in FIG.
4, a display memory circuit 35, an identification memory circuit 36, a different memory circuit 37, and a drive control circuit 38, and a drive signal circuit 40 shown in FIG.
And a drive control circuit 38 including a ROM 41 and a drive voltage circuit 42. In the drive control circuit 38 of FIG. 15, if the current application number N of the bipolar pulse is different from the detected application number Q of the temperature data DT, the combination of a new voltage waveform from the drive signal circuit 40 to the ROM 41 by N and DT. Is output, and a new combination of voltage waveforms is output to the FLCD 4.

【0043】例えば、図7の特性を示すFLCパネル1
の場合、温度検出手段により検出した温度データDT が
41°で現在の両極性パルスの印加回数Nが4のとき、
41°における印加許容回数は5〜4なので駆動信号回
路40からROM41へは従来のN=4の電圧波形の組
合せのアドレスが出力される。また、温度検出手段によ
り検出した温度データDT が43°で現在の両極性パル
スの印加回数Nが4のとき、43°における印加許容回
数は4なので駆動信号回路40からROM41へは従来
のN=4の電圧波形の組合せのアドレスが出力される。
For example, an FLC panel 1 having the characteristics shown in FIG.
In the case of, when the temperature data DT detected by the temperature detecting means is 41 ° and the current number of times N of application of the bipolar pulse is 4,
Since the allowable number of times of application at 41 ° is 5 to 4, the address of the conventional combination of voltage waveforms of N = 4 is output from the drive signal circuit 40 to the ROM 41. Further, when the temperature data DT detected by the temperature detecting means is 43 ° and the current number of times N of application of the bipolar pulse is 4, the allowable number of times of application at 43 ° is 4, so the conventional N = from the drive signal circuit 40 to the ROM 41. The address of the combination of the four voltage waveforms is output.

【0044】しかし、温度検出手段により検出した温度
データDT が39°で現在の両極性パルスの印加回数N
が4のとき、39°における印加許容回数は5なので駆
動信号回路40からROM41へは新たにN=5の電圧
波形の組合せのアドレスが出力される。また、温度検出
手段により検出した温度データDT が41°で現在の両
極性パルスの印加回数Nが5のとき、41°における印
加許容回数は5〜4なので駆動信号回路40からROM
41へは従来のN=5の電圧波形の組合せのアドレスが
出力される。
However, the temperature data DT detected by the temperature detecting means is 39 °, and the present number of times N of application of the bipolar pulse is N.
Is 4, the allowable number of times of application at 39 ° is 5, so that an address of a combination of voltage waveforms of N = 5 is newly output from the drive signal circuit 40 to the ROM 41. Further, when the temperature data DT detected by the temperature detecting means is 41 ° and the current number of times N of application of the bipolar pulse is 5, the allowable number of times of application at 41 ° is 5 to 4, so the drive signal circuit 40 reads the ROM.
The address of the conventional combination of N = 5 voltage waveforms is output to 41.

【0045】この場合は選択期間tを25t0 で固定し
た。選択期間を固定して両極性パルスの印加回数を変え
るというのは、例えば選択期間t=11t0 で両極性パ
ルスの印加回数Nが5の図1の電圧波形の組合せの1両
極性パルスを0電圧で置き換え、両極性パルスの印加回
数Nが4の図2の電圧波形の組合せにするということで
ある。なお、図2は図1とパルス印加回数以外は同じで
あるのでその説明は省略する。
In this case, the selection period t is fixed at 25t0. Changing the number of times the bipolar pulse is applied while fixing the selection period means, for example, that the number of times the bipolar pulse is applied N is 5 in the selection period t = 11t0 and one bipolar pulse of the combination of the voltage waveforms of FIG. 2 and the number of application times N of the bipolar pulse is 4, and the voltage waveforms in FIG. 2 are combined. Note that FIG. 2 is the same as FIG. 1 except for the number of times of pulse application, and therefore its explanation is omitted.

【0046】しかし、半導体の電流供給能力はパネルの
温度が低いときには問題がないので、パネルの温度が低
いときは両極性パルスの印加回数を変えながら選択期間
も変えられる。即ち、通常FLCD4が使われる最低温
度(15〜20°)で選択期間を例えば17t0 に固定
し、たまたま低温でFLCD4を使う為に両極性パルス
の印加回数を12としなければならなくなったときは、
選択時間を変化させて25t0とすることもできる。こ
のとき、1選択期間のデータDATAの転送時間を17
t0 より早くしておけば、選択期間が25t0 になって
問題はない。
However, since the current supply capacity of the semiconductor does not cause any problem when the panel temperature is low, when the panel temperature is low, the selection period can be changed while changing the number of times the bipolar pulse is applied. That is, when the selection period is fixed to, for example, 17t0 at the lowest temperature (15 to 20 °) at which the FLCD 4 is normally used, and the number of times of applying the bipolar pulse must be 12 in order to use the FLCD 4 at low temperature,
The selection time may be changed to 25t0. At this time, the transfer time of the data DATA in one selection period is set to 17
If it is set earlier than t0, the selection period becomes 25t0 and there is no problem.

【0047】[0047]

【発明の効果】この発明によれば、FLCパネルの温度
に対応し、滅多に使われない高温では表示品位はあまり
良くないが、通常使われる低温で良好な表示品位を与え
ることができる。
According to the present invention, the display quality is not so good at a high temperature which is rarely used and corresponds to the temperature of the FLC panel, but it is possible to give a good display quality at a low temperature which is usually used.

【図面の簡単な説明】[Brief description of drawings]

【図1】本実施例でFLCパネルの駆動に用いられる各
印加電圧を示す波形図である。
FIG. 1 is a waveform diagram showing each applied voltage used for driving an FLC panel in this embodiment.

【図2】本実施例でFLCパネルの駆動に用いられる各
印加電圧を示す波形図である。
FIG. 2 is a waveform diagram showing each applied voltage used for driving the FLC panel in the present embodiment.

【図3】FLCDで用いられるFLCパネルの構成を示
す断面図である。
FIG. 3 is a cross-sectional view showing a configuration of an FLC panel used in an FLCD.

【図4】FLCDに「ABCD」の文字を表示した状態
を示す図である。
FIG. 4 is a diagram showing a state in which characters “ABCD” are displayed on the FLCD.

【図5】FLC分子を示す説明図であり、(A)はスメ
クチックC相におけるFLC分子の状態を示す図であ
る。(B)はスメクチックC相におけるFLC分子の様
子を基板側からみた図である。
FIG. 5 is an explanatory diagram showing FLC molecules, and (A) is a diagram showing a state of FLC molecules in a smectic C phase. (B) is a view of the state of FLC molecules in the smectic C phase viewed from the substrate side.

【図6】液晶組成物Aの温度−応答速度・メモリパルス
幅の特性を示すグラフである。
FIG. 6 is a graph showing characteristics of liquid crystal composition A with respect to temperature-response speed / memory pulse width.

【図7】液晶組成物Bの温度を変えた電圧−メモリパル
ス幅の特性を示すグラフである。
FIG. 7 is a graph showing characteristics of voltage-memory pulse width when the temperature of liquid crystal composition B is changed.

【図8】オペアンプの温度を変えた出力電圧−出力電流
の特性を示すグラフである。
FIG. 8 is a graph showing the output voltage-output current characteristics when the temperature of the operational amplifier is changed.

【図9】液晶組成物Bの温度を変えたチルト角の特性を
示すグラフである。
9 is a graph showing the tilt angle characteristics of liquid crystal composition B when the temperature is changed. FIG.

【図10】本実施例で使われる温度検出回路の概略的な
構成を示すブロック図である。
FIG. 10 is a block diagram showing a schematic configuration of a temperature detection circuit used in this embodiment.

【図11】ダイオード型サーミスタの温度ー抵抗値特性
を示す説明図である。
FIG. 11 is an explanatory diagram showing temperature-resistance value characteristics of a diode type thermistor.

【図12】本実施例で使われる温度検出回路の概略的な
構成を示すブロック図である。
FIG. 12 is a block diagram showing a schematic configuration of a temperature detection circuit used in this embodiment.

【図13】図12の温度検出器の動作を説明する為の波
形図である。
13 is a waveform chart for explaining the operation of the temperature detector of FIG.

【図14】本実施例で使用する表示制御装置の概略的な
構成を示すブロック図である。
FIG. 14 is a block diagram showing a schematic configuration of a display control device used in this embodiment.

【図15】本実施例で使用する駆動制御回路の概略的な
構成を示すブロック図である。
FIG. 15 is a block diagram showing a schematic configuration of a drive control circuit used in this embodiment.

【符号の説明】[Explanation of symbols]

1 FLCパネル 2 走査側駆動回路 3 信号側駆動回路 4 FLCD 5 ガラス 6 絶縁膜 7 配向膜 8 封止剤 9 FLC 10 偏光版 18 定電圧源 19 サーミスタ 20 オペアンプ 21、26 アナログ/デジタル変換器 22 抵抗 23 フオトダイオード 24 アンプ 25 ローパスフィルタ 27 検出器 28 制御電圧発生器 29 電圧制御発振器 30 カウンタ 31 印加電圧発生器 32 減衰器 33 入力制御回路 34 出力制御回路 35 表示メモリ回路 36 群メモリ回路 37 同異メモリ回路 38 駆動制御回路 39 表示制御装置回路 40 駆動信号回路 41 ROM 42 駆動電圧回路 L 走査電極 S 信号電極 1 FLC panel 2 Scanning side driving circuit 3 Signal side driving circuit 4 FLCD 5 Glass 6 Insulating film 7 Alignment film 8 Sealant 9 FLC 10 Polarizing plate 18 Constant voltage source 19 Thermistor 20 Operational amplifier 21, 26 Analog / digital converter 22 Resistance 23 Photodiode 24 Amplifier 25 Low-pass filter 27 Detector 28 Control voltage generator 29 Voltage controlled oscillator 30 Counter 31 Applied voltage generator 32 Attenuator 33 Input control circuit 34 Output control circuit 35 Display memory circuit 36 Group memory circuit 37 Same memory Circuit 38 Drive control circuit 39 Display control device circuit 40 Drive signal circuit 41 ROM 42 Drive voltage circuit L Scan electrode S Signal electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 互いに交差する方向に配列した複数の走
査電極と複数の信号電極との間に誘電異方性が負の強誘
電性液晶を介在させ、走査電極に選択電圧又は非選択電
圧を選択的に印加すると共に、信号電極に書換え電圧又
は保持電圧を選択的に印加して走査電極と信号電極とが
交差する領域の各画素の表示を変化させるようにした液
晶表示装置の駆動方法であって、 非選択電圧を印加した走査電極と書換え電圧を印加した
信号電極から構成される第1画素と、非選択電圧を印加
した走査電極と保持電圧を印加した信号電極から構成さ
れる第2画素へ、正電圧と負電圧から構成される両極性
パルスを複数回印加し、第1および第2画素の透過光量
の変化をほぼ等しくし、 選択電圧を印加した走査電極と保持電圧を印加した信号
電極から構成される第3画素へ、強誘電性液晶分子に働
く誘電異方性負の効果が大きな領域の正又は負電圧と、
強誘電性液晶分子に働く誘電異方性負の効果が小さな領
域の負又は正電圧から構成される両極性パルスを複数回
印加し、第3画素の透過光量の変化を第1及び第2画素
の透過光量の変化にほぼ等しくするか、またはそれより
小さくすると共に、 液晶パネルを構成する強誘電性液晶分子の温度に合わせ
て、第1、第2及び第3画素へ印加する両極性パルスの
印加回数を変化させることを特徴とする液晶表示装置の
駆動方法。
1. A ferroelectric liquid crystal having a negative dielectric anisotropy is interposed between a plurality of scanning electrodes and a plurality of signal electrodes arranged in directions intersecting with each other, and a selection voltage or a non-selection voltage is applied to the scanning electrodes. A driving method of a liquid crystal display device, which selectively applies a rewriting voltage or a holding voltage to a signal electrode to change the display of each pixel in a region where a scanning electrode and a signal electrode intersect. The first pixel is composed of the scanning electrode to which the non-selection voltage is applied and the signal electrode to which the rewriting voltage is applied, and the second pixel composed of the scanning electrode to which the non-selection voltage is applied and the signal electrode to which the holding voltage is applied. A bipolar pulse composed of a positive voltage and a negative voltage is applied to the pixel a plurality of times to make the changes in the transmitted light amount of the first and second pixels substantially equal, and the scan electrode to which the selection voltage is applied and the holding voltage are applied. Consists of signal electrodes That the third pixel, and a positive or negative voltage dielectric anisotropy negative effects acting on the ferroelectric liquid crystal molecules is large area,
A bipolar pulse composed of a negative or positive voltage in a region where the negative effect of the dielectric anisotropy acting on the ferroelectric liquid crystal molecules is small is applied multiple times, and the change of the transmitted light amount of the third pixel is changed. Of the bipolar pulse applied to the first, second and third pixels according to the temperature of the ferroelectric liquid crystal molecules constituting the liquid crystal panel. A method for driving a liquid crystal display device, characterized in that the number of times of application is changed.
JP23494392A 1992-09-02 1992-09-02 Driving method for ferroelectric liquid crystal display device Pending JPH0682760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23494392A JPH0682760A (en) 1992-09-02 1992-09-02 Driving method for ferroelectric liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23494392A JPH0682760A (en) 1992-09-02 1992-09-02 Driving method for ferroelectric liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH0682760A true JPH0682760A (en) 1994-03-25

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Family Applications (1)

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JP23494392A Pending JPH0682760A (en) 1992-09-02 1992-09-02 Driving method for ferroelectric liquid crystal display device

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929833A (en) * 1995-09-11 1999-07-27 Nippondenso Co., Ltd. Matrix liquid crystal display having temperature-dependent element drive timing and method of driving the same
US5966111A (en) * 1995-10-26 1999-10-12 Denso Corporation Matrix type liquid crystal display device
US6676459B2 (en) 2001-05-31 2004-01-13 Canon Kabushiki Kaisha Conductor connection method, conductor connection structure, and solar cell module having connection structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929833A (en) * 1995-09-11 1999-07-27 Nippondenso Co., Ltd. Matrix liquid crystal display having temperature-dependent element drive timing and method of driving the same
US5966111A (en) * 1995-10-26 1999-10-12 Denso Corporation Matrix type liquid crystal display device
US6676459B2 (en) 2001-05-31 2004-01-13 Canon Kabushiki Kaisha Conductor connection method, conductor connection structure, and solar cell module having connection structure

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