JPH0681509B2 - Reference signal creation circuit for synchronous PWM inverter - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a circuit for digitally generating a reference signal of a PWM inverter.

[Prior art]

The ignition pulse of a synchronous PWM inverter, for example, an inverter whose switching element is a gate turn-off thyristor, has a reference triangular wave signal Vc and a sine wave signal Vcs as shown in FIG.
Are generated by comparing. Vp indicates an output pulse. In the case of the synchronous type, the number N of output pulses Vp included in one cycle is always an integer, but the number N of pulses is limited because the switching frequency of the switching element of the inverter is limited. As fo increases, it is necessary to reduce it correspondingly. That is, modulation reference frequency =
It is necessary to prevent fo × N from exceeding the maximum switching frequency fm. However, if the inverter load is an AC motor, it is better that the value of fo × N is as large as possible in order to reduce the torque pulsation of the motor.
As shown in the figure, the number of pulses N is changed according to the output frequency fo, but as a result, the modulation reference frequency f changes discontinuously as shown in the figure.

For this reason, in the conventional PWM control circuit using the microcomputer, as shown in FIG. 3, the modulation reference frequency f which changes discontinuously is stored as a function in the ROM indicated by reference numeral 1 and is called by D The signal is converted into an analog signal by the / A converter 2 and then guided to the voltage / frequency converter 3 to obtain a PWM reference signal having a modulation reference frequency.

As described above, in the conventional computer-controlled PWM reference signal generating circuit, it is necessary to restore the digital output of the ROM corresponding to the modulation reference frequency to the analog signal, so that the circuit is complicated and expensive.

[Outline of Invention]

The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and uses a computer controlled first and second programmable divider, and a PLL circuit having another fixed or programmable divider in a feedback circuit. First
The microcomputer's reference clock is given to the programmable divider of to generate the inverter frequency reference, and this inverter frequency reference is given to the PLL circuit,
The output of this PLL circuit is divided by the second programmable divider to obtain the PWM reference signal without changing the frequency division number of this feedback circuit.
The present invention proposes a reference signal generation circuit for a synchronous PWM inverter that can generate an M reference signal and is therefore less expensive than conventional ones.

Example of Invention

 FIG. 4 is a block diagram showing an embodiment of the present invention.

In the figure, reference numerals 10, 20, 30, 40 denote programmable dividers (hereinafter abbreviated as frequency dividers), the frequency division numbers of which are controlled by the microcomputer 100. 50 is PLL
A circuit which includes the frequency dividers 30 and 40 in its feedback circuit and performs a frequency multiplier operation.

The reference clock of the microcomputer 100 is input to the frequency divider 10. The frequency divider divides the frequency fc of the reference clock into a value corresponding to the output frequency fo of the inverter. In this case, if the frequency division number M1 of the frequency divider 10 is made sufficiently large, a highly accurate output frequency can be obtained. The output frequency fo thus obtained is given as the frequency reference of the PLL circuit 50. P
The output of the LL circuit 50 is input to the frequency divider (frequency division number M2) 20.
The dividers 30 and 40 of the feedback circuit may be integrated into a fixed divider.

Now, for convenience of explanation, the frequency division number of the frequency divider 30 is M3 = 256, the frequency divider 4
Assuming that the frequency division number of 0 is M4 = 135, the frequency division numbers appearing at the output points 51, 31, and 41 are 256 × 1 due to the nature of the PLL circuit 50.
35 × fo, 135 × fo, fo, and the output of the PLL circuit 50 has a value according to the output frequency fo. This value, that is, 56 × 135 × fo is given to the frequency divider 20. Therefore, the frequency division number M2 of the frequency divider 20
Is controlled by the microcomputer 100 according to the output frequency fo, for example, 45, 27, 15 ... With the count number of one cycle being 256, the pulse number N = 3, 5, 9 ...
On the other hand, the PWM reference signal of the modulation frequency can be easily obtained with high accuracy.

If the frequency division number of the feedback circuit of the PLL circuit 50 is variable, disturbance (vibration) will occur in the output of the PLL circuit 50 when that frequency changes,
Although this will cause a trip of the inverter, in the present embodiment, since the frequency division number of the feedback circuit does not change, this problem does not occur and it is practical as a reference signal generating circuit of the synchronous PWM inverter.

〔The invention's effect〕

As described above, since the present invention has a pure digital configuration using a programmable divider and a PLL circuit,
Compared with the conventional one, there is an effect that the cost can be reduced and the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a waveform diagram of a synchronous PWM signal, FIG. 2 is a diagram showing a relationship between a modulation reference frequency and an inverter output frequency, FIG. 3 is a block diagram of a conventional PWM reference signal generating circuit, and FIG.
The figure is a block diagram of an embodiment of the present invention. In the figure, 10 to 40 are programmable dividers, 50 ...
PLL circuit, 100 ... Microcomputer.

Claims (1)

[Claims] 1. A first programmable divider whose frequency division number is controlled by a microcomputer to divide an input reference clock into a frequency corresponding to an output frequency of an inverter, and an output of the first programmable divider. PLL circuit to input as a command value, the frequency division number is controlled by the microcomputer to the frequency division number according to the output frequency of the inverter, the output frequency of the PLL circuit is divided, the PWM reference signal of the inverter A second programmable divider that outputs, a reference signal for a synchronous PWM inverter that is equipped with a divider with a fixed frequency division number that is inserted into a feedback circuit that feeds back the output of the PLL circuit to the input of the PLL circuit. circuit.