JPH0681174B2 - Communication control device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a communication control device, and more particularly to a communication control device having a high-speed start-stop synchronization transmission / reception function.

[Conventional technology]

When communication is performed between the communication control device and a data terminal such as a character display device by the start-stop synchronization method, the communication control device or the data terminal generally requests the transmission stop request character Xoff when the communication device cannot receive a message from the partner device.
(Generally, a hexadecimal code "13") is transmitted, and when it is ready for reception, a transmission restart request character Xon (generally a hexadecimal code "11") is transmitted.

Here, when attention is paid to the communication control device, the processing required in the communication control device is divided into the following three types.

The process of temporarily storing the characters received from a data terminal in an input buffer with a capacity of multiple bytes.

The process of sending the contents of an output buffer with a capacity of multiple bytes to a data terminal.

Processes other than the above (for example, transferring the contents of the input buffer to the upper host).

The priority of these three types of processing is generally highest,
Is the lowest.

The communication control device transmits Xoff to the data terminal when the free space in the input buffer becomes less than or equal to a certain capacity (Q bytes) in the processing of. At this time, the data terminal receiving Xoff stops transmission of characters other than Xon and Xoff. In addition, the communication control device performs the process of transferring the contents of the input buffer to the upper host in the process while the data terminal stops transmitting the character, and the free space in the input buffer (R bytes) If the following occurs, Xon is sent to the data terminal. At this time, the data terminal receiving the Xon restarts character transmission. If the capacity of the input buffer of the communication control device is P bytes, the relationship of R, Q, and R is generally P>R>Q> 1.

Further, the communication control device stops the transmission when it receives Xoff in the communication with the data terminal, and restarts the transmission when it receives Xon. At this time, Xon and Xoff are removed from the received character string.

[Problems to be Solved by the Invention] In the conventional communication control device, the process of transferring the received character to the input buffer and the Xon,
Xoff detection, input buffer management, processing to remove Xon and Xoff by this, processing such as character transmission in the output buffer are all processed for each character by software such as a microprocessor, so the communication speed is several tens. It is less than a kilobit / second, and there is a problem that a communication speed of several hundred kilobits / second and several megabits / second, which is expected to appear in the future, cannot be realized.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a communication control device having a high-speed start-stop synchronization type function, by improving the above-mentioned drawbacks of the prior art.

[Means and Actions for Solving Problems]

The present invention, in a start-stop synchronous communication control device including a line adapter having a character buffer and a memory for performing block-unit data transfer with the line adapter, requests transmission stop of a line in the line adapter. A character, a character requesting a resumption of transmission, a detection means for detecting a character indicating the end of a message, and when the character detecting a request for a transmission stop and a character requesting a resumption of transmission are detected by the detecting means, these characters are removed from the received message. , When the character indicating the end of the message is detected, a means for generating an interrupt, a means for stopping the transmission of the message until the character for the transmission restart request is detected until the character for the transmission restart request is detected, and externally The character of the transmission stop request or the character of the transmission restart request is transmitted at any time by the instruction That means and together providing a further data is transferred to transmit character in the memory means for transferring data blocks to said line adapters, in blocks of received characters into the memory within the line adapter,
Moreover, by providing means for generating an interrupt each time a fixed character is transferred, software intervention is reduced and high-speed asynchronous communication is realized.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which a communication control device 1 includes a line adapter 2, a memory 3 for temporarily storing programs and received characters, a CPU 4 for controlling the device, and a memory 3. Between the line and line adapter 2
DMA to control A (Direct Memory Access) transfers
It is composed of a controller 5 and an interface unit 6 with an upper host. Transmission line 31 and reception line of the communication control device 1
It is connected to the display device (data terminal) 10 via 32, and is connected to a host (not shown) by a bus line 54. 43 is an interrupt signal line from the line adapter 2, 45 is a transmission character set request signal line from the line adapter 2 to the DMA controller 5, and 46 is a transmission character set completion from the DMA controller 5 to the line adapter 2. A signal line, 48 is a reception character acceptance request signal line from the line adapter 2 to the DMA controller 5, 49 is a reception character acceptance completion signal line from the DMA controller 5 to the line adapter 2, 47 is an internal bus,
Reference numeral 51 is a transmission side interrupt line of the DMA controller, and 52 is a reception side interrupt line of the DMA controller.

Fig. 2 shows an example of the internal configuration of the line adapter 2 in Fig. 1. 11 is a character with a 1-byte width converted to serial data, and start and stop bits are added to the data to obtain data at a predetermined communication speed. Is a parallel-serial conversion circuit for transmitting the. Reference numeral 12 is a serial-parallel conversion circuit that removes start and stop bits from the received data and converts it into a character of 1-byte width. Reference numeral 13 is a transmission buffer for temporarily holding the transmission character to the parallel-serial conversion circuit 11, and 14 is a reception buffer for temporarily holding the reception character from the serial-parallel conversion circuit 12.

If the parallel-serial conversion circuit 11 is empty, 15 transfers the character in the transmission buffer 13 to the circuit 11, turns on the transmission character request signal 33, and turns on the transmission character set signal 34.
Then, the transmission buffer control circuit stores the character on the bus 47 in the transmission buffer 13 and turns off the signal 33. If 16 characters are received by the serial-parallel conversion circuit 12, that character is transferred to the reception buffer 14 to turn on the received character take-up request signal 35, and when the received character take-over completion signal 36 is turned on, the signal 35 is turned on. It is a receive buffer control circuit that is turned off.

17 is Xon, Xo by signal 33, signal 37, signal 38, signal 46, signal 50
This is a transmission character control circuit that controls the transmission of ff, a transmission character request signal to the DMA controller 5, and the like.

18 is a register for storing a parameter for controlling the adapter 2, 19 is a register for storing Xon, 20 is a register for storing Xoff, 21 is a character indicating the end of the message (generally, "CR" and below the carriage return) Registers for storing (abbreviated), and 22 and 23 are 3-state gates each having a width of 1 byte.

Reference numeral 24 is a comparison circuit that compares the outputs of the registers 19, 20 and 21 with the output of the reception buffer 14, and when the output of the register 19 and the output of the buffer 14 match, the Xon reception signal 42
Is turned on, the Xoff reception signal 41 is turned on when the output of the register 20 matches the output of the buffer 14, and the CR reception signal 43 is turned on when the output of the register 21 matches the output of the buffer 1. 25 is a flip-flop in which the output (signal 38) turns on after the signal 41 turns on until the signal 42 turns on, and the output turns off (the signal 38) until the signal 41 turns on after the signal 42 turns on. is there.

26 is a reception character control circuit, which is a signal when the signal 35 is ON
If 44 is OFF (receives signals other than Xon and Xoff), the signal 48 to the DMA controller 5 is turned ON, and the signal 44 and DMA
The logical sum with the signal 49 from the controller 5 is output to the signal 36.

The operation of the communication control device will be described below with reference to FIGS. 1 and 2.

(1) Initial setting The CPU 4 initializes the line adapter 2 and the DMA controller 5. Register each code of Xon, Xoff and CR to register 19,2
Set it to 0,21.

(2) Transmission operation Normal operation The message to be transmitted is stored in the output buffer area of the memory 3 from the host by way of the host interface section 6. The operation of sending a message stored in the output buffer area is shown below.

The CPU 4 sets the start address of the output buffer area where the message to be transmitted is stored in the transmission address register (abbreviated as "TxAR" below) in the DMA controller 5, and the message length is the transmission count in the DMA controller 5. Set in a register (hereinafter abbreviated as "TxCQ").

The transmission buffer control circuit 15 turns on the signal 33 when the transmission buffer 13 is empty.

When the transmission character control circuit 17 detects that the signal 33 is turned on, the signal 38 is turned off (the initial state of the signal 38 is off), and the signal 45 is turned on to the DMA controller 5.

When the DMA controller 5 detects that the signal 45 is turned on, it acquires the right to use the bus 47, reads one character from the address of the output buffer area indicated by TxAR,
The character is set on the bus 47 (DMA transfer from the output buffer area to the line adapter 2) and the transmission character set signal 46 is turned on.

When the transmission character control circuit 17 detects that the signal 46 is turned on, it turns on the signal 34.

When the transmission buffer control circuit 15 detects that the signal 34 is turned on, it stores the character on the bus 47 in the transmission buffer 13 and turns off the signal 33.

When the transmission character control circuit 17 detects that the signal 33 is turned off, it turns off the signal 45.

When the DMA controller 5 detects that the signal 45 is turned off, it relinquishes the right to use the bus 47 and thus increments the content of TxAR by +1 and the content of TxCR by -1.

If the parallel-serial conversion circuit 11 is empty, the transmission buffer control circuit 15 transfers the contents of the transmission buffer 13 to the circuit 11.

The parallel-serial conversion circuit 11 adds start and stop bits to the transferred character and outputs the data serially from the transmission line 31.

The transmission buffer control circuit 15 turns on the signal 33 when the transmission buffer 13 is empty.

The operation after that is repeated.

When the content of TxCR becomes 0 In the above, when the content of TxCR of the DMA controller 5 becomes 0, the DMA controller 5 turns on the signal 51.

When the CPU 4 detects that the signal 51 is turned ON, it reads the status register (abbreviated as “SR” below) in the DMA controller 5 and knows that the transmission of the message has been completed, and performs a new message transmission operation. .

DMA controller 5 turns off signal 51 when SR is read
To

When Xoff is received If Xoff is received during operation from the above (signal 38
(When turned on), the transmission character control circuit 17 sends a signal 38
If is ON, signal 45 is turned ON even if signal 33 is turned ON.
I don't. (Stop transmission thereafter) When Xon is received When Xon is received during operation from the above (signal 38 is O
When it becomes FF), the transmission character control circuit 17 sends a signal 38
If is turned off, the signal 45 is turned on when the signal 33 is turned on.
To (The transmission is restarted thereafter.) (3) Receiving operation The length of the received message is unknown. Also, in order not to generate an overrun error, the receiving side performs DMA transfer (transfer from the line adapter 2 to the input buffer area in the memory 3).
The method uses the autoload function of the DMA controller 5. The autoload function is a function that automatically transfers the contents of the base address register to the address register and the contents of the base count register to the count register when the contents of the count register become 0.
By using this function, it is possible to transfer memory areas divided into multiple areas continuously, and CPU4 has enough time to write the start address and transfer count value of the next memory to each register. You can When the content of the count register becomes 0, the DMA controller issues an interrupt.

Normal operation When Xoff is transmitted when the free space of the input buffer area in the memory 3 becomes Q bytes or less, the CPU 4 adjusts the receive overrun error, so the DMA controller 5
In the receive base count register (hereinafter abbreviated as “RxBCR”), K (K is a value less than or equal to Q), and the start address (A) of the input buffer area in the receive base address register (hereinafter “RxBAR”) in the DMA controller 5. Abbreviated), and the DMA controller 5 is set to the DMA transfer enable state. Since the content of RxCR is 0 at this time, the content of RxBAR is stored in the receive address register (hereinafter abbreviated as “RxAR”) in the DMA controller 5 by the autoload function, The content of RxBCR is automatically transferred to "," and the DMA controller 5 generates a pulse in the signal 52.

When the CPU 4 detects the pulse of the signal 52, it sets K to RxBCR and A + K to RxBAR of the DMA controller 5.

The serial input data from the receiving circuit 32 is serial-parallel conversion circuit 12
Is converted into a parallel character by.

If a character is formed in the serial-parallel conversion circuit 12, the reception buffer control circuit 16 receives the character and stores it in the reception buffer.
When it is transferred to 14, the signal 35 is turned ON.

The reception character control circuit 26 turns on the signal 48 because the reception character (contents of the buffer 14) is other than Xon and Xoff (the signal 44 is OFF).

When the DMA controller 5 detects that the signal 48 is turned ON, it acquires the right to use the bus 47 and writes the character on the bus 47 to the address of the memory 3 indicated by RxAR (from the adapter 2 to the input buffer area). DMA transfer to),
Turn on signal 49.

When the reception character control circuit 26 detects that the signal 49 is turned on, it turns off the signals 48 and 36.

When the reception buffer control circuit 16 detects that the signal 36 is turned off, it turns off the signal 35.

When the DMA controller 5 detects that the signal 48 is turned off, it releases the right to use the bus 47 and sets the contents of RxAR to +1,
Decrement the contents of RxCR by -1.

The subsequent operation is repeated.

When the content of RxCR becomes 0 When the content of RxCR becomes 0 in the above, the DMA controller 5 transfers the content of RxBAR to RxAR and the content of RxBCR to RxCR by the overload function, and pulse to signal 52. To occur.

When the CPU 4 detects the pulse of the signal 52, the CPU 4 calculates the free capacity (E bytes) of the input buffer area on the memory 3, and performs the following operations depending on the value of E.

(A) The operation from E ≦ Q is performed.

(B) The operation from the time of Q <E <R is performed.

(C) Perform 26 operations from the time R ≦ Q.

The free capacity of the input buffer area is calculated from the contents of RxAR and the address of the input buffer area character to be transferred to the next host.

The CPU 4 turns on the Xoff transmission bit of the command register 18.

When the Xoff transmission bit of the command register 18 turns ON,
Signal 37 turns ON.

When the transmission character control circuit 17 detects that the signal 37 is turned ON, the signal 45 is transmitted when the next character can be transmitted.
Is turned off (DMA transfer is prohibited), and signals 34 and 40 are turned on.

When the transmission buffer control circuit 15 detects that the signal 34 is turned on, it stores the character (Xoff) on the bus in the transmission buffer 13 and turns off the signal 33.

When the transmission character control circuit 14 detects that the signal 33 is turned off, it sends a pulse to the signal 51. The circuit 17 does not turn on the signal 45 when the signal 37 is turned on.

The Xoff transmission bit of the command register 18 is turned off by the pulse of the signal 51, turning off the signal 37.

The subsequent operation is repeated.

The CPU 4 turns on the Xon transmission bit of the command register 18. If the Xon transmission bit has already been turned on, the operation from is repeated.

When the Xon transmission bit of the command register 18 turns ON,
Signal 50 turns ON.

When the transmission character control circuit 17 detects that the signal 50 has been turned ON, it sends a signal 45 when the next character can be transmitted.
Is turned off (DMA transfer is prohibited), and signals 34 and 39 are turned on.

When the transmission buffer control circuit 15 detects that the signal 34 is turned on, it buffers the character (Xon) on the bus 13
, And turn off the signal 33.

When the transmission character control circuit 17 detects that the signal 33 is turned off, it sends a pulse to the signal 51. The circuit 17 does not turn on the signal 45 when the signal 50 is turned on.

The Xon transmission bit of the command register 18 is turned off by the pulse of the signal 51, and turns off the signal 50.

The subsequent operation is repeated.

The comparator circuit 24 generates a pulse in the signal 43 because the received character (content of the buffer 14) is CR.

In the reception character control circuit 26, the signal 44 is OFF and the signal 35 is O
Since it is N, the signal 48 is turned on.

The following operations from above are performed.

When the CPU 4 detects the pulse of the signal 43, it recognizes that the last character of the electronic message has been received, and the R of the DMA controller 5
Characters up to the input buffer address of xAR contents-1 are transferred to the upper host.

(4) Other than transmission / reception operation In cases other than the above transmission / reception operation, the communication control device performs processing such as transferring the received character in the input buffer area to the host.

〔The invention's effect〕

As described above, according to the present invention, since software intervention is required for each transfer of a plurality of characters, it is possible to realize a communication control device having a high-speed start-stop synchronization function.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an internal block diagram of the line adapter of FIG. 1 ... Communication control device, 2 ... line adapter, 3 ... memory, 4 ... CPU, 5 ... DMA controller, 6 ... interface part with upper host, 10 ... character display device, 31 ... transmission Line, 32 …… Reception line, 43 …… Interrupt signal, 45 …… Send character set request signal line, 46 …… Send character set completion signal line, 48 …… Received character takeover request signal line, 49 …… Received character Pickup completion signal line.

Claims (1)

[Claims] 1. A start-stop synchronous communication control device comprising a line adapter having a character buffer, and a memory for transferring data in block units between the line adapter and a line adapter. A detection means for detecting the character of the transmission stop request, the character of the transmission restart request, and the character indicating the end of the message, and when the detection means detects the character of the transmission stop request and the character of the transmission restart request, these characters are received. If it is removed from the message and a character indicating the end of the message is detected,
A means for generating an interrupt, a means for stopping the transmission of a telegram from the detection of the character of the transmission stop request until the character of the transmission restart request is detected, and the character of the transmission stop request or the transmission restart request by an external instruction. Means for transmitting the character in the line adapter at any time, and means for transferring the data in the memory to the line adapter in block units, and for transmitting the received character in the line adapter to the memory in block units In addition, the communication control device is provided with means for generating an interrupt each time a fixed character is transferred.