JPH0679315B2 - Digital signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor (hereinafter referred to as DSP).

BACKGROUND ART An audio signal processing device capable of controlling a sound field to create a reverberant sound or a realistic sensation in a concert hall or a theater at home or in a car is known, for example, Japanese Patent Laid-Open No. 64-72615. It is shown in the official gazette. Such an audio signal processing device is provided with a DSP for performing sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. The DSP is an arithmetic unit for performing arithmetic operations such as four arithmetic operations, a data RAM for storing digital audio signal data supplied to the arithmetic unit, and digital coefficient signal data for multiplying the audio signal data (hereinafter, simply referred to as coefficient data). A memory such as a coefficient RAM for storing is provided. In the DSP, the signal data is transferred between the memories and from the memories to the arithmetic unit according to a predetermined program, and the arithmetic processing of the signal data can be repeatedly performed at high speed. The program is DS
It is written in a rewritable program memory such as RAM in P, and the program is changed by a microcomputer outside the DSP every time the sound field mode is switched by operation. That is, it is possible to create any acoustic space by changing the program.

In the conventional DSP, as shown in FIG. 2, buffer memories 1 and 2, a multiplier 3, an ALU 4 and an accumulator 5 are provided. Further, a signal data RAM 6 for storing the input digital signal data and a coefficient data RAM 7 for storing a plurality of coefficient data are provided. At the time of calculation, the signal data is read from the signal data RAM 6 and supplied to the buffer memory 1 via the bus 8 and held therein, and the coefficient data is sequentially read from the coefficient data RAM 7 at a predetermined timing and stored in the buffer memory 2. Supplied and retained. The value indicated by the data held in the buffer memories 1 and 2 is multiplied by the multiplier 3. The result of multiplication by the multiplier 3 is added to the value held in the accumulator 5 by the ALU 4, and is held in the accumulator 5. The ALU 4 and the accumulator 5 form an accumulating means. Also,
The hold output of the accumulator 5 is connected to the buffer memory 1 and the signal data RAM 6 via the bus 8 so that the hold data can be transferred.

In such a conventional DSP, an operation of multiplying two coefficient data values by a signal data value and accumulating May be done. Note that an is a coefficient that changes as the program progresses, and bn is a fixed coefficient. In this case, first, a ₁ x ₁ is calculated by the multiplier 3, and the calculated a ₁
x ₁ is transferred to the buffer memory 1 via the ALU 4, the accumulator 5, and the bus 8, and a ₁ x ₁ b ₁ is calculated by the multiplier 3. At this time, ALU4 sets the multiplication result of the multiplier 3 to 0.
The operation of adding is performed. The calculated a ₁ b ₁ x ₁ is held in the accumulator 5. Next, a ₂ x ₂ is multiplier 3
Then, the calculated a ₂ x ₂ is transferred to the buffer memory 1 via the ALU 4, the accumulator 5, and the bus 8, and the a ₂ x ₂ b ₂ is calculated by the multiplier 3. The a ₁ b ₁ x ₁ held in the ALU ₄ and the calculated a ₂ b ₂ x ₂ are added in the ALU 4 and held in the accumulator 5. By repeating such operation Is calculated.

However, in such a conventional DSP, As described above, in the case of the operation of multiplying the signal data value by a plurality of coefficients, there is a problem that the number of steps of the program is large and the processing time is long.

SUMMARY OF THE INVENTION [Object of the Invention] An object of the present invention is to reduce the processing time in the case of an operation for multiplying a signal data value by a plurality of coefficients.
Is to provide P.

[Structure of the Invention] The DSP of the present invention includes first and second arithmetic units each including a digital multiplication means for multiplying two digital signal data values and a digital accumulation means for accumulating output values of the multiplication means. A digital signal processor provided, characterized in that the output of the multiplication means of the second calculation section is connected to one input of the digital signal data of the multiplication means of the first calculation section.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

In the DSP which is one embodiment of the present invention shown in FIG.
Two arithmetic units are provided. The first calculation unit includes buffer memories 11 and 12, a multiplier 13, an ALU 14, and an accumulator 15. The outputs of the buffer memories 11 and 12 are connected to the multiplier 13, respectively. The output of the multiplier 13 is connected to one input of the ALU 14, and the output of the ALU 14 is connected to the accumulator 15. The accumulator 15 has two outputs,
One output is connected to one input of ALU 14 and the other output is connected to bus 10. The buffer memory 12
Has three inputs.

In addition, the second arithmetic unit includes buffer memories 16 and 17, a multiplier 18 and A.
It is composed of an LU 19 and an accumulator 20 and has the same configuration as the first arithmetic unit. However, the multiplier 18 of the second operation unit has two outputs, one output of which is connected to one input of the ALU 19 and the other output of which is connected to one input of the buffer memory 12.

The coefficient data RAM 21 stores coefficient data b ₁ , b ₂ , ..., Bn, and the output of the coefficient data RAM 21 is connected to the buffer memory 11. The signal data RAM 22 is connected to the other input of the buffer memory 12. Further, coefficient data RAM 23 stores coefficient data a ₁ , a ₂ , ...
The output of 3 is connected to the buffer memory 16. The signal data RAM 24 is connected to the buffer memory 17. Signal R
The AMs 21 and 24 and the buffer memories 12 and 17 are also connected to the bus 10.

Note that either one of the three inputs of the buffer memory 12, the two inputs of the buffer memory, the two outputs of the multiplier 18 and the accumulators 15 and 20, and the two outputs of the signal data RAMs 22 and 24 are selectively enabled. It is a thing. These are composed of, for example, a switching circuit including a plurality of 3-state buffers and the like.

The operation of reading coefficient data from the RAMs 21 and 23, the operation of reading signal data from the RAMs 22 and 24, the arithmetic operation of the ALUs 14 and 19, the output selection operation of the held data of the accumulators 15 and 20, the output selection operation of the multiplier 18, etc. The operation is controlled by a sequence controller (not shown) in the DSP.
The sequence controller operates according to a program written in a program memory (not shown) in the DSP.

In the DSP having such a configuration, the audio signal data xn supplied from the outside is written in a predetermined area of the signal data RAM 24. Operation of multiplying signal data values by two coefficient data values and accumulating In the first step, the signal data x ₁ is read from the signal data RAM 24 and supplied to the buffer memory 17. On the other hand, the coefficient data a ₁ is read from the coefficient data RAM 23 and supplied to the buffer memory 16. Therefore, the multiplier 18 calculates the signal data x ₁ and the coefficient data.
Multiplies the value with a ₁ . Value of the multiplication result by the multiplier 18 x ₁ a ₁
Is supplied to the buffer memory 12 from the other output in the second step, which is one step after the first step. In the second step, coefficient data is stored in the buffer memory 11.
The coefficient data b ₁ is read from the RAM 21 and supplied. Therefore, the multiplier 13 multiplies x ₁ a ₁ by the coefficient data value b ₁ .
The value a ₁ b ₁ x ₁ of the multiplication result by the multiplier 13 is held in the accumulator 15 via the ALU 14 in the third step.

Further, in the second step, the signal data x ₂ is read from the signal data RAM 24 and supplied to the buffer memory 17. On the other hand, the coefficient data a ₂ is read from the coefficient data RAM 23 and supplied to the buffer memory 16. Since the signal data and the coefficient data are sequentially read in each step, the reading of x ₂ and a ₂ is performed in the step subsequent to the reading step of x ₁ and a ₁ . The multiplier 18 multiplies the signal data value x ₂ by the coefficient data value a ₂ . This multiplier 18
The value x ₂ a ₂ of the multiplication result by is supplied to the buffer memory 12 from the other output in the third step. In this third step, the coefficient data b ₂ is read from the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies x ₂ a ₂ by the coefficient data value b ₂ . Multiplier 13
The value a ₂ b ₂ x ₂ obtained by multiplying by is supplied to the other input of the ALU 14. In synchronization with this supply, the data value a ₁ b ₁ x ₁ held in the accumulator 15 is supplied to one input of the ALU 14. Therefore, in the fourth step, ALU14 uses a ₁ b ₁ x ₁
Accumulation of + a ₂ b ₂ x ₂ is performed, and the value of this accumulation result is held in the accumulator 15. By repeating such operation Is calculated. For example, when n = 6, the eighth
The value of the accumulated result in the step Are stored in the accumulator 15. The coefficient data
From the RAM 23, the coefficient data a ₁ , a ₂ ... An are sequentially read from the RAM 23 for each step. From the coefficient data RAM 21, the coefficient data b ₁ , b ₂ ... Bn are sequentially processed from the second step. It is read every time.

In the above-mentioned embodiment, However, the present invention is not limited to this, and the present invention can be applied to other calculations.

As described above, the DSP according to the present invention has the first and second digital multiplication means for multiplying the values of two digital signal data and the digital accumulation means for accumulating the output values of the multiplication means, respectively. An arithmetic unit is provided, and the output of the multiplying unit of the second arithmetic unit is connected to one input of the digital signal data of the multiplying unit of the first arithmetic unit. Therefore, In the case of the operation of multiplying the signal data value by a plurality of coefficients as described above, it is not necessary to transfer the intermediate result data from the output of the accumulating means to the multiplying means via the bus during the operation, and Since the signal data and the coefficient data can be read from the memory every step for efficient data processing, the number of steps of the program can be made smaller than in the conventional case, and the processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a configuration of a conventional DSP. Explanation of symbols of main parts 3,13,18 …… Multiplier 4,14,19 …… ALU 5,15,20 …… Accumulator

Claims (1)

[Claims] 1. A digital signal processor comprising first and second arithmetic units each comprising a digital multiplication means for multiplying two digital signal data values and a digital accumulation means for accumulating output values of the multiplication means. The digital signal processor is characterized in that the output of the multiplying means of the second computing section is connected to the input of one digital signal data of the multiplying means of the first computing section.