JPH0678175A - Peak limiter circuit - Google Patents

Abstract

PURPOSE:To suppress the saturation of a white peak independently of an APL circuit or an ACL circuit. CONSTITUTION:An input signal is applied to a variable gain amplifier circuit 14 and a high frequency detecting circuit 16. Control voltage corresponding to the average brightness of a TV screen is outputted form the circuit 14 to the circuit 16. Only when the level of the input signal is higher than reference voltage and includes a high frequency component, the circuit 16 inputs a current from the circuit 12 to change the gain of the circuit 12. The gain is controlled by the control voltage impressed from the circuit 14. Thus the amplitude of an output signal can be suppressed and the saturation of a white peak can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak limiter circuit, and more particularly to a peak limiter circuit used for suppressing saturation of a white level of a TV signal.

[0002]

2. Description of the Related Art A conventional peak limiter circuit 1 shown in FIG.
Are arranged at the final stage of the signal path of the TV set. That is, before the output stage of the TV set, ABL (Automa
tic beam limiter circuit and ACL (Automatic Contrast)
Limiter circuit is arranged, but the peak limiter circuit 1 is arranged after the ABL circuit and the ACL circuit.

The peak limiter circuit 1 receives from a terminal 2 a -Y signal (an inverted version of the Y signal) processed by the ABL circuit and the ACL circuit as shown in FIG. The potential at point B when this −Y signal is input is A
When the potential is lower than the limiter potential determined by the bias of the point, the diode 3 becomes conductive and the -Y signal is subjected to the limiter processing.
At this time, for example, as shown in FIG. 5B, the capacitor 4 of 1000 PF limits the high frequency component of the -Y signal at a potential higher than that of the low frequency component, so that the -Y signal output from the terminal 5 is output. The limiter amount of the high frequency component of is larger than that of the low frequency component. That is,
As shown in FIG. 5C, the peak of the high frequency component of the Y signal is suppressed more than that of the low frequency component.

The above-described conventional peak limiter circuit 1 does not operate normally unless it is at the subsequent stage of the ABL circuit or the ACL circuit for the following reason. That is, the white peak of a small area is easily saturated on the TV screen only when the average brightness (APL: Average Picture Level) of the screen is low, and the saturation of the white peak is not a problem when the APL is high. However, in the TV set, if the peak limiter circuit 1 is arranged in the preceding stage of the ABL circuit or the ACL circuit, the high frequency component will always be generated regardless of the size of the APL (even if the white peak saturation is high and the APL is high). Is suppressed and the overall frequency characteristic is deteriorated.

[0005]

However, depending on the TV set, there is one in which the RGB circuit is arranged in the preceding stage of the ABL circuit or the ACL circuit. In this case, the conventional peak limiter circuit 1 is replaced with the ABL circuit or the ACL circuit. There was a problem that it did not function effectively even if it was placed in the latter stage. Therefore, a main object of the present invention is to provide a peak limiter circuit that functions effectively even if it is arranged in the preceding stage of an ABL circuit or an ACL circuit.

[0006]

DISCLOSURE OF THE INVENTION The present invention is directed to a brightness detecting means for detecting an average brightness from an input signal and outputting a control voltage according to the average brightness; A high frequency detecting means for outputting a gain control signal according to the control voltage when a high frequency component equal to or higher than a predetermined level exists, and a variable gain amplifying means for controlling the gain according to the gain control signal and receiving the input signal to extract the output signal. It is a peak limiter circuit provided.

[0007]

The input signal is given to the variable gain amplifying means, the brightness detecting means and the high frequency detecting means. The brightness detection means
When the DC component of the input signal is smaller than the first reference voltage, it is assumed that the APL of the input signal is low, and a control voltage according to the difference between the DC component and the reference voltage is given to the high frequency detecting means. On the other hand, the high-frequency detection means assumes that the brightness of the input signal is above a certain level when the level of the input signal is above the second reference voltage. Then, when the level of the input signal is equal to or higher than the second reference voltage and a high frequency component is present, a gain control signal for suppressing the white peak of the input signal is given to the variable gain amplifying means. At this time, the magnitude of the gain in the variable gain amplifying means is adjusted by the control voltage from the brightness detecting means. In this way, the amplitude of the output signal is suppressed and the saturation of the white peak is suppressed only when the APL is low, the brightness of the input signal is equal to or higher than a certain level, and the input signal includes a high frequency component.

[0008]

According to the present invention, an ABL circuit and an ACL are provided.
APL is detected by the luminance detecting means regardless of the circuit, the amplitude of the output signal is suppressed under a certain condition, and the saturation of the white peak is suppressed. Therefore, it is possible to effectively perform the limiter processing without arranging the ABL circuit or the ACL circuit in the subsequent stage as in the conventional case.

The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0010]

1 and 2, a peak limiter circuit 10 of this embodiment is a current control type variable gain amplifier circuit 12 whose gain is changed by a current and an APL of a TV screen.
An APL detection circuit 14 and a high frequency detection circuit (High Frequency Detector) 16 for detecting Although these circuits 12, 14 and 16 are integrally formed, here, for convenience, FIG. 1 and FIG.
It is shown as connected by 0, 22, 24 and 26.

The variable gain amplifier circuit 12 is disclosed in Japanese Patent Application No. 4-43862 filed by the applicant of the present application on February 28, 1992, and therefore will be briefly described here.
Variable gain amplifier circuit 12 includes a differential pair 28 including transistors Q1 and Q2, a differential pair 30 including transistors Q3 and Q4, an impedance dividing circuit 32 including resistors R1 and R2, and an impedance including resistors R3 and R4. A dividing circuit 34 is included. Differential pair 28 and 30
Are driven by being supplied with a constant current from the current mirror circuit 36. Current mirror circuit 36 includes transistors Q5 and Q6 and resistors R5 and R6. The outputs of the transistor Q2 of the differential pair 28 and the transistor Q3 of the differential pair 30 are both fed back by the feedback circuit 38. That is, the feedback circuit 38 includes a transistor Q7 and a constant current source 40 that outputs an output current I _out , the outputs from the collectors of the transistors Q2 and Q3 are given to the base of the transistor Q7, and the output from the emitter of the transistor Q7 is supplied to the transistor Q2. And is returned to the base of Q3. Note that Ia
Is the sum of the emitter currents of the transistors Q1 and Q2 of the differential pair 28, that is, the current flowing through the constant current source 42,
Ib is the sum of the emitter currents of the transistors Q3 and Q4 of the differential pair 30, that is, the sum of the current flowing through the constant current source 44 and the current drawn into the transistor Q23. Further, an input signal is given from the signal source V _{in, an} output signal is taken out from the connection point 46, and a DC bias V _DC is given to the differential pair 30 via the resistor R3.

Here, the gain A of the variable gain amplifier circuit 12 is
Is determined by A = Ia / (Ia + Ib) and changes with the currents Ia and Ib. Therefore, as will be described later, the current Ib is increased by drawing the current into the transistor Q23 of the high frequency detection circuit 16, and the gain A is suppressed. Further, the input signal from the signal source V _in is given to the APL detection circuit 14. The APL detection circuit 14 includes an LPF 4 having a large time constant including a resistor R7 and a capacitor C1.
8 and a comparator 50. Therefore, the signal source V
Input signals from the _in is, LPF 48 of APL detecting circuit 14
Is smoothed and processed by the comparator 50.

Comparator 50 includes a differential pair 52 including transistors Q8 and Q9, compares the input signal from LPF 48 with reference voltage V _THR, and if the DC component of the input signal is smaller than reference voltage V _THR , APL becomes A control voltage corresponding to the difference is applied from the collector of the transistor Q9 to the transistor Q12 via the current mirror circuit 54 including the resistors R8 and R9 and the transistors Q10 and Q11 to determine the base voltage of the transistor Q12. To do. That is, the APL detection circuit 14 is a current source that changes according to APL, and the base voltage of the transistor Q12 fluctuates according to the difference between the DC component of the input signal compared by the differential pair 52 and the reference voltage V _THR, and the base voltage of the transistor Q12 changes. The base voltage passes through the terminal 20 and the high frequency detection circuit 1
Given to 6.

At this time, the base voltage of the transistor Q12 becomes the base voltage of the transistors Q23, Q24 and Q25, so that the respective transistors Q23, Q2.
4 and Q25 conductivity, and current values I and I1
To decide. That is, the output current Io is determined. Therefore, by the control voltage from the APL detection circuit 14,
The high frequency detection circuit 16 determines the value of the current taken out from the variable gain circuit 12, and as a result, the gain A of the variable gain amplification circuit 12 is controlled. On the other hand, when the DC component of the input signal is equal to or higher than the reference voltage V _THR , the transistor Q12 is not turned on and the high frequency detection circuit 16 is not activated. Note that I2
Is a current flowing through the constant current source 56.

The input signal from the signal source V _in is given to the high frequency detection circuit 16 via the terminal 24. The input signal is compared with a reference voltage V1 by a differential pair 58 including transistors Q16 and Q17, and when the level of the input signal is equal to or higher than the reference voltage V1, it is assumed that the input signal has a brightness equal to or higher than a certain level, and the transistor Q16 is turned on. The input signal is the capacitor C2, the resistors R10 and R11.
Is applied to the HPF 60 including only the high frequency component and the resistance R
A transistor Q1 of a differential pair 62 which is resistance-divided by 10 and R11 and includes transistors Q18 and Q19.
8 bases are entered. The transistor Q18 is not turned on when there is no high-frequency component that passes through the HPF 60 in the input signal.

That is, the high frequency detection circuit 16 is activated by the control voltage from the APL detection circuit 14, the level of the input signal is equal to or higher than the reference voltage V1, and the input signal is H level.
Only when there is a high-frequency component that passes through the PF 60, the transistor Q18 of the differential pair 62 turns on. The current flowing through the transistor Q18 is the resistance R12,
Most of it becomes the output current Io via the current mirror circuit 64 including the R13 and the transistors Q20 and Q21. The output current Io is given to the current mirror circuit 60 including the resistors R14 and R15 and the transistors Q22 and Q23, and when the transistor Q23 is turned on, a current is drawn from the variable gain amplifier circuit 12 and the current Ib of the variable gain amplifier circuit 12 is drawn. Is increased to suppress the gain A.

On the other hand, the DC component of the input signal is the reference voltage V1.
Although larger, the transistor Q16 turns on when the high frequency component does not exist in the input signal, but the transistor Q16 turns on.
18 does not turn on, and the transistors Q18 and Q of the differential pair 62 are
Balances with 19. Therefore, the current I1 flowing through the resistor R16 flows through the transistor Q16, and as a result, the current I1 / 2 flows through the transistors Q18 and Q19.
Flow through the current mirror circuit 64, the output current Io becomes a current I1 / 2 flowing through the transistor Q18. However, in this case, since the output current Io is not desired to flow, the resistors R17, R18, Q24 and Q
By providing a current mirror circuit 68 including 25,
The current flowing through the transistor Q18 is canceled so that the output current Io does not flow through the transistors Q20 and Q21. In this way, when there is no high-frequency component in the input signal and the transistors Q18 and Q19 are in balance, the output current Io is not passed and the current is not drawn from the variable gain amplifier circuit 12.

That is, the level of the input signal is higher than the reference voltage V1 only when the comparator 50 of the APL detection circuit 14 detects that the DC component of the input signal is smaller than the reference voltage V _THR , that is, when the APL of the input signal is low. When the input signal includes a high frequency component, the output current Io is output and the current is drawn from the variable gain amplifier circuit 12. Then, the gain A of the variable gain amplifier circuit 12 is suppressed, the peak of the high frequency component of the output signal extracted from the variable gain amplifier circuit 12 is suppressed, and the saturation of the white peak is suppressed.

A block diagram of this embodiment shown in FIGS. 1 and 2 is shown in FIG.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the remaining part of the embodiment of the present invention.

FIG. 3 is a block diagram showing the embodiment shown in FIGS. 1 and 2.

FIG. 4 is a circuit diagram showing a conventional technique.

FIG. 5 is a waveform diagram showing a processing result according to a conventional technique.

[Explanation of symbols]

 10 ... Peak limiter circuit 12 ... Variable gain amplification circuit 14 ... APL detection circuit 16 ... High frequency detection circuit

Claims (1)

[Claims] 1. Brightness detecting means for detecting an average brightness from an input signal and outputting a control voltage according to the average brightness, wherein the brightness of the input signal is equal to or higher than a certain level and a high frequency component equal to or higher than a predetermined value is included in the input signal. A peak, which is provided with a high frequency detecting means for outputting a gain control signal according to the control voltage when present, and a variable gain amplifying means for controlling the gain according to the gain control signal and receiving the input signal to extract an output signal; Limiter circuit.