JPH0677806A - Output circuit for semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a level of a power supply voltage itself as an output level and to reduce an output noise by providing plural bootstrap capacitors and selecting a capacitor with a laser blow. CONSTITUTION:Capacitors 4a, 4b for bootstrap are connected to a gate of an N-channel MOS transistor (TR) 1 through laser blow use wires 4c, 4d and have almost the same capacitance. Furthermore, the other terminal of the capacitors 4a, 4b is connected to an input node for a control signal phi1 via a delay circuit 5. In order to optimize the bootstrap capacitance, the capacitance of the two bootstrap capacitors 4a, 4b depends on an on-resistance of the NMOS TR 1 and an impedance of an output load. Thus, overshoot due to the mismatching of the output impedance is suppressed by cutting off either one of the layer blow use wires 4c, 4d to select either one of the capacitors 4a, 4b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit for amplifying and outputting a signal inside a semiconductor memory device, and more particularly to an output circuit capable of improving overshoot of an output signal.

[0002]

2. Description of the Related Art FIG. 10 is a circuit diagram showing an output circuit of a conventional semiconductor memory device. In the figure, 1 and 2 are power supply Vcc
An NMOS transistor 3 connected in series between the ground and the ground is connected between the gate of the NMOS transistor 1 and the input terminal of the control signal φ1, and an NMOS transistor 4 whose gate is connected to the power supply Vcc is connected. A capacitor for bootstrap that is connected between the gate of the NMOS transistor 1 and the output of the delay circuit 5 and has a capacitance value of, for example, 5 to 6 pF. Reference numeral 5 is a delay circuit for delaying the control signal φ1, for example, four stages of inverters,
That is, it has a delay time of about 3 to 4 ns. N is NMOS
The transistors 1 and 3 and the capacitor 4 are commonly connected, and M is a node to which the output of the delay circuit 5 and the capacitor 4 are commonly connected. The control signal φ2, which is an inverted signal of the control signal φ1, is input to the gate of the NMOS transistor 2. Note that this control signal φ1,
Specifically, φ2 is a pair of data consisting of normal data from a memory cell inside the semiconductor memory device and data with its logic level inverted.

Next, the operation of the circuit of FIG. 10 will be described with reference to the timing chart of FIG. At time t1, the signal φ
1 rises from 0V to Vcc. In response to this, the node N also rises from 0V, but since the gate level of the NMOS transistor 3 is Vcc, it rises only to the Vcc-Vth level. On the other hand, the node M maintains the state of 0V by the delay circuit 5 and becomes 0V only at the time t2.
Rises to Vcc. Then, the node N is brought to a voltage higher than Vcc + Vth (hereinafter, this will be referred to as Vcc + α) due to the bootstrap effect of the capacitor 4, and then drops to Vcc. Therefore, the output Dout is after time t3,
It has a potential of Vcc level.

In the above operation, the signal φ1 changes from 0V to V
The case where the signal φ1 rises to cc has been described.
Needless to say, when the signal φ2 rises from 0V to Vcc while maintaining V, the output Dout outputs the ground level.

[0005]

Since the output circuit of the conventional semiconductor memory device is configured as described above, if the signal φ 1 is directly connected to the gate of the transistor 1,
The problem that only the level of Vcc-Vth can be obtained at the output node Dout is solved, and the level of Vcc itself can be obtained at the output Dout by the bootstrap action of the capacitor 4. However, there is a problem that the output level instantaneously rises to Vcc or more due to the impedance mismatch of the output section, which causes noise and causes a problem to the system.

The present invention has been made in order to solve the above problems, and an object is to obtain an output circuit of a semiconductor memory device which can obtain the level of Vcc itself as an output level and reduce output noise. Has an aim.

[0007]

An output circuit of a semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, and the capacitors can be selected by laser blow.

Further, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, and the capacitors can be selected in the Al wiring step in the wafer process.

Further, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, and the output level is obtained stepwise by using a delay circuit.

Further, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, and the capacitors can be selected by an internal control signal.

Furthermore, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors and output transistors, and the output level is obtained stepwise by using a delay circuit.

[0012]

Since the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, the size of the capacitors can be selected by laser blow, and the boosting capability can be adjusted according to various output impedances. As the level, Vcc level can be obtained.

Further, since the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, the size of the capacitors can be selected in the Al wiring step in the wafer process, and it can be selected according to various output impedances. Adjust the boost ability, and Vcc as the output level
You get a level.

Since the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors and the delay circuit is used to obtain the output level stepwise,
As the output level, the Vcc level is obtained stepwise, and the occurrence of output overshoot is further suppressed.

Further, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors and is stepwise using a delay circuit whose activation and deactivation can be controlled by using signals inside the semiconductor memory device. Since the output level is obtained, the size of the capacitance can be selected, the boosting ability is adjusted according to various output impedances, and the Vcc level is obtained stepwise as the output level.

Further, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors and output transistors, and the delay circuit is used to obtain the output level stepwise. By setting the value, the output level is Vcc
The level is obtained in stages, and at that time, the slope of the output level that rises in stages can be adjusted, and the occurrence of output overshoot is further suppressed.

[0017]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an output circuit of a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 and 2 are NMOSs connected in series between a power supply Vcc and ground.
Transistors 3 are connected between the gate of the NMOS transistor 1 and the control signal φ1, and NMOS transistors whose gates are connected to the power supply Vcc, 4a and 4b are NMOS.
Capacitors connected to the gate of the transistor 1 for bootstrap, both having substantially the same capacitance value. 4c and 4d are capacitors 4a and 4b and NMOS
Laser blow wirings 5 respectively connected to the gate of the transistor 1 are delay circuits for delaying the control signal φ1 and have a delay time of, for example, about 3 to 4 ns.

Next, the operation will be described with reference to the timing chart of FIG. At time t1, the signal φ1 is 0
Rise from V to Vcc. In response to this, the node N also becomes NM
The level of φ1 is transmitted by the OS transistor 3, but since its gate level is Vcc, it rises only to the level of Vcc-Vth. On the other hand, the node M maintains the state of 0V by the delay circuit 5 and rises from 0V to Vcc only at the time t2. In response to this, node N
Rises to Vcc + α level due to the bootstrap effect. When the node N reaches Vcc + α, the output Dout can rise to the Vcc level. Note that α is α <
It has a value of Vth, and the value is, for example, 1V. Further, the capacitance of the node N is CN (including the gate capacitance of the transistor 1), the capacitance value of the capacitance 4a is Ca, and the capacitance 4b.
Let Cb be the capacitance value of

(Vcc−Vth) · CN + αCa + αCb ≧ Vcc · (CN + Ca + Cb)

The values of Ca and Cb may be set so that the following is satisfied.

However, ".gtoreq." Is a little larger than "=", so it is considered that the calculation may be performed with "=". The values of Ca and Cb are both 5 to 5, for example.
It is 6 pF.

In this embodiment, the bootstrap capacitance is set to 2 in order to optimize the bootstrap capacitance.
(4a, 4b) are prepared and the capacity value is NMO.
It can be determined by the on resistance of the S transistor 1 and the impedance of the output load connected to the output node Dout. Therefore, the output impedance mismatch can be eliminated by cutting one of the laser blow wirings 4c and 4d in order to select one of them according to the type of output load. You can suppress the shoot,
The generation of noise can be significantly reduced.

Further, the laser blow wiring may be provided at both ends of the capacitance, or the same switching as in the embodiment of FIG. 1 is realized by providing two or more capacitances and providing the laser blow wiring at at least one end thereof. it can.

Example 2. In the above embodiment, the laser blow wiring is provided between the bootstrap capacitors 4a and 4b and the node N, but as shown in FIG. 3, only the wiring 4c is provided with Al wiring during the wafer process. ,
4d may be disconnected, and wiring may be provided at this disconnected position as required.

With this structure, in addition to the same effect as that of the embodiment shown in FIG. 1, there is an effect that the number of steps is reduced because it is not necessary to perform laser cutting. It is also possible to make several kinds of broken wires and select the most suitable one.

Further, both ends of the capacitors 4a and 4b may be insulated without being connected to the nodes M and N, and wiring may be provided at this disconnection point if necessary. The embodiment of FIG. The same effect as can be obtained.

Also, in the case where the number of capacitors is two or more, one or both ends of at least one capacitor may be disconnected, and wiring may be provided at this disconnection point if necessary. The same effect as the embodiment of FIG. 3 is obtained.

Example 3. FIG. 4 is an output circuit of a semiconductor memory device showing another embodiment of the present invention. In this embodiment, the laser blow wiring in the embodiment of FIG. 1 is eliminated, and a delay circuit 5b is added between one end of the capacitor 4b and the output of the delay circuit 5a corresponding to the delay circuit 5 of FIG. is there. The delay circuits 5a and 5b are both 3-4, for example.
It has a delay time of about ns.

Next, the operation will be described with reference to the timing chart of FIG. .phi.1 changes from 0V to Vcc at time t1 and both delay circuits 5a, 5 have the same delay time.
The node M and the node P change from 0V to Vcc at the times t2 and t3 by b. At this time, the node N becomes V at time t2.
Only the level up to cc-Vth rises, but at times t3 and t
When it reaches 4, it gradually rises to Vcc + α. In response to this, the potential of Dout rises and is output up to Vcc, and no overshoot occurs.

Thus, according to the embodiment of FIG. 4, Dou
The output potential of t is increased in two steps, and the increase in the second step is made to rise more gently than the increase in the first step. Therefore, the occurrence of overshoot is prevented more reliably than in the embodiment of FIG. It is possible to further prevent the generation of noise.

It should be noted that one end of the delay circuit 5b may be connected to φ1 instead of being connected to the node M, and the same effect as that of the above embodiment can be obtained.

Further, in the above embodiment, the delay circuit and the capacitance are 2
The delay circuit and the capacitance are respectively provided by providing a series circuit of another delay circuit and the capacitance between the connection point of the delay circuit 5b and the capacitance 4b and the gate of the transistor 1. It goes without saying that three or more may be provided.

Example 4. FIG. 6 shows an output circuit of a semiconductor memory device according to still another embodiment of the present invention. This embodiment is different from the embodiment of FIG. 1 in that the capacitor 4b and the delay circuit 5a are provided.
, A series circuit of a 2-input NAND 6 and an inverter 7 whose sum of delay times is substantially equal to the delay time of the delay circuit 5a is provided, and the control signal φ3 is input to one of the 2-input NAND 6 to boot the capacitor 4b. Whether to use as a strap capacitance is controlled by using the control signal φ3, and this control signal φ3
The capacitor 4b is also selected when 3 is at "H" level, and only the capacitor 4a is selected when .phi.3 is at "L" level.

The control signal φ 3 is CAS (Column A
It can be created by delaying a ddress strobe) signal or an OE (Output Enable) signal.

Next, the operation will be described with reference to the timing chart of FIG. φ1 changes from 0V to Vcc at time t1, and the node N changes from 0V to Vcc-Vth level.
Further, the delay circuit 5a changes the node M from 0V to 5V at time t2. Therefore, the bootstrap effect is activated by the capacitance 4a, and the node N changes from the Vcc-Vth level to the boosted Vcc + α level. When φ3 is at Vcc level, NAND gate 6 and inverter 7
Since the serial circuit of FIG. 6 delays the signal of the node M and applies it to one end of the capacitor 4b similarly to the delay circuit 5b of FIG. 6, a Vcc level is obtained at the output pin Dout.

As described above, according to the embodiment of FIG. 6, the activation and deactivation of the series circuit of the NAND gate and the inverter corresponding to the delay circuit can be controlled by the control signal inside the semiconductor memory device. The capacitance value of the bootstrap capacitance can be increased or decreased by controlling this series circuit as necessary.

The control signal φ3 may be fixed to "L" by wire bonding to disconnect the capacitance.

Further, in the above embodiment, the 2-input NAND and the inverter are provided only for the capacitor 4b, but the capacity is further increased and the 2-input NAND is provided for these.
It goes without saying that an inverter may be provided.

Example 5. FIG. 8 shows an output circuit of a semiconductor memory device according to still another embodiment of the present invention. In this embodiment, NMOS transistors 1b and 3b are added to the embodiment of FIG.

Next, the operation will be described with reference to the timing chart of FIG. .phi.1 changes from 0V to Vcc at time t1, and the nodes N and P change from 0V to Vcc-Vth level. Further, the delay circuits 5a and 5b having the same delay time respectively cause the node M and the node Q to operate at the time t.
2 and t3 change from 0V to 5V. Therefore, capacity 4
The bootstrap effect is activated by a and 4b, and the levels of the nodes N and P are boosted to Vcc + α1 and Vcc + α2,
The level of Vcc itself is obtained at the output pin Dout.
Where α1 and α2 are α1 and α2 <Vth and α1 + α2 ≧
There is a relationship of Vth, and for example, both values are 1V.

The capacity of the node N is CN (including the gate capacity of the transistor 1a), and the capacity of the node P is Cp.
(Containing the gate capacitance of the transistor 1b), the capacitance value of the capacitance 4a is Ca, and the capacitance value of the capacitance 4b is Cb.

(Vcc−Vth) · (CN + Cp) + αCa + αCb ≧ Vcc · (CN + Ca + Cb)

The values of Ca and Cb may be set so that the following is satisfied.

However, ".gtoreq." Is a little larger than "=" and therefore, it is considered that the calculation may be performed with "=". The values of Ca and Cb are both 5 to 6 for example.
pF.

As described above, according to the embodiment of FIG. 8, since the output pin Dout has two output transistors (1a, 1b) for outputting Vcc, the transistor 1
By changing the sizes of a and 1b and the values of the capacitors 4a and 4b, it is possible to adjust the slope of the potential that rises in two steps. Note that the transistor size and the capacitance value may be increased to make the gradient steep.

In the above embodiment, the delay circuit, the capacitance, the bootstrap transistor, and the output transistor are two.
Although it is arranged to provide one each, it goes without saying that the potential may be increased in three or more stages by providing three or more each.

[0047]

As described above, the output circuit of the semiconductor memory device according to the present invention has a plurality of bootstrap capacitors, and the capacitors can be selected by laser blow. The boosting ability can be adjusted according to various output impedances, and the output level can be the Vcc level.

Further, according to the output circuit of the semiconductor memory device of the present invention, since a plurality of bootstrap capacitors are provided and the capacitors can be selected in the Al wiring process during the wafer process, the size of the capacitors can be determined by the wafer process. There is an effect that it can be selected in the Al wiring process at that time, the boosting ability can be adjusted according to various output impedances, and the output level can be the Vcc level.

Further, according to the output circuit of the semiconductor memory device of the present invention, since it has a plurality of bootstrap capacitors and the delay circuit is used to obtain the output level stepwise, the output level is the Vcc level. Is obtained in stages,
Moreover, there is an effect that the occurrence of output overshoot can be further suppressed.

Further, according to the output circuit of the semiconductor memory device of the present invention, since a plurality of bootstrap capacitors are provided and the capacitance can be selected by the internal control signal, the capacitance can be selected by using the signal inside the semiconductor memory device. Can be selected, the boosting ability can be adjusted according to various output impedances, and the Vcc level can be obtained stepwise as the output level.

Further, according to the output circuit of the semiconductor memory device of the present invention, the bootstrap capacitor and the output transistor are provided in plural, and the delay circuit is used to obtain the output level stepwise. By appropriately setting the size and the capacitance value, the Vcc level can be obtained stepwise as the output level, and at that time, the gradient of the output level that rises stepwise can be adjusted, and the occurrence of output overshoot can be further suppressed. There is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an output circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is a circuit diagram showing an output circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing an output circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of another embodiment of the present invention.

FIG. 6 is a circuit diagram showing an output circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of another embodiment of the present invention.

FIG. 8 is a circuit diagram showing an output circuit of a semiconductor memory device according to another embodiment of the present invention.

FIG. 9 is a timing chart for explaining the operation of another embodiment of the present invention.

FIG. 10 is a circuit diagram showing an output circuit of a conventional semiconductor memory device.

FIG. 11 is a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

 1 NMOS transistor 1a NMOS transistor 1b NMOS transistor 2 NMOS transistor 3 NMOS transistor 3a NMOS transistor 3b NMOS transistor 4a capacitor 4b capacitor 4c laser blow wiring 4d laser blow wiring 5 delay circuit 5a delay circuit 5b delay circuit 6 2 input NAND 7 inverter

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 17/06 C 9184-5J 17/16 H 9184-5J 6741-5L G11C 11/34 354 A

Claims (5)

[Claims] 1. A first field effect element connected between a power supply potential and an output node, and a first field effect element connected between a control electrode and a first control signal input node. A second field effect element, a delay circuit having one end connected to the input node of the first control signal, and a second circuit connected between the other end of the delay circuit and the control electrode of the first field effect element. Connection selection that makes it possible to select connection or non-connection by laser blow between the plurality of capacitive elements, each of the plurality of capacitive elements, the other end of the delay circuit and the control electrode of the first field effect element. And an output circuit of a semiconductor memory device. 2. The output circuit of a semiconductor memory device according to claim 1, wherein the selection by the connection selection means is performed in a wiring process in a wafer process, instead of the selection by the laser blow. 3. A first field effect element connected between a power supply potential and an output node, and a control electrode of the first field effect element and an input node of the first control signal. A second field effect element, a first delay circuit having one end connected to the input node of the first control signal, the other end of the first delay circuit and the first field effect element. A capacitive element connected between the control electrode and a second delay circuit, one end of which is connected to a connection point between the other end of the first delay circuit and the control electrode of the first field effect element; An output circuit of a semiconductor memory device, comprising: a capacitive element connected between the other end of the second delay circuit and a control electrode of the first field effect element. 4. The output circuit of a semiconductor memory device according to claim 3, wherein activation and deactivation of said second delay circuit can be selected by a second control signal. 5. A first and second field effect element connected between a power supply potential and an output node, an input node of a first control signal, and control electrodes of the first and second field effect elements. Third and fourth field effect elements connected between the first delay circuit and one end of the first delay circuit connected to the input node of the first control signal, and the other end of the first delay circuit. A capacitive element connected between the control electrode of the first field effect element, a second delay circuit having one end connected to the other end of the first delay circuit, and a second delay circuit of the second delay circuit. An output circuit of a semiconductor memory device, comprising: a capacitive element connected between the other end and a control electrode of the second field effect element.