JPH067753B2 - Motor phase control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor phase control circuit suitable for application to a motor that drives a rotating body such as a drum or a capstan of a video tape recorder.

Background Art and its Problems For example, in a phase control circuit of a drum motor, a vertical synchronizing signal of a television signal is used as a reference signal during recording, and phase control is performed so that the rotation phase of the drum motor matches this phase. However, recently, there is a device which uses an internally generated reference pulse instead of the external reference signal as the reference signal.

FIG. 1 is a system diagram showing an example thereof. A reference clock from a reference clock generation source (1) is supplied to a counter (2) for generating an internal reference pulse, and the reference clock is divided at a predetermined ratio. To be done. In this example, the reference clock is divided into 1 / n to form a 60 Hz reference pulse P _C1 (FIG. 2B),
This is further supplied to the 1/2 frequency divider (3) and the reference pulse P
_C2 (FIG. 2C) is formed.

Since the counter (2) is reset by the external vertical synchronizing pulse VD (FIG. 2A), the second reference pulse P _C2 is
The vertical synchronizing pulse VD is output as being phase-clocked. This reference pulse P _C2 phase-clocked with the vertical synchronizing pulse VD is supplied as a reference pulse of the phase control system (10).

The phase control system (10) has a phase comparator (4) as well known,
The rotation phase pulse P _G output corresponding to the rotation of the drum motor (5) is supplied to this, and the phase is compared with the reference pulse P _C2 . After this is smoothed in the low pass filter (6), it is driven. It is supplied to the circuit (7) to control the rotation speed and thus the rotation phase of the drum motor (5).

Incidentally, (8) an alien by a detector to obtain a pulse P _G synchronized from the drum motor (5) in its rotation, in this example a pulse generator is used.

Also with this configuration, the rotation phase of the drum motor (5) can be clocked to the phase of the vertical synchronizing pulse VD. Further, according to this configuration, even if the vertical synchronizing pulse VD is missing, for example, when the electric field is weak, the counter (2) is 60 Hz.
Since it is self-propelled, the reference pulse P _C2 is not lost.
Therefore, even if the vertical sync pulse VD is missing, the phase control system (1
Disturbance of 0) does not occur.

However, in the configuration shown in FIG. 1, the counter (2) is reset by the vertical synchronizing pulse VD, so that the vertical synchronization in the channel after switching can be achieved even when the channel is switched, for example. Pulse V
Control is performed so as to lock in the D phase. For example, as shown in FIG. 2D, even if the phase of the vertical synchronizing pulse VD itself significantly changes by switching the channel, the phase control is performed so as to lock to the phase of the vertical synchronizing pulse VD. The rotation of the drum motor (5) suddenly fluctuates.

Since the phase of the vertical sync pulse of the television signal is not specified between broadcasting stations, the phase of each vertical sync pulse of the television signal of the previous channel and the television signal of the channel to be received from now on is In some cases, it is preferable that the phase pull-in of the phase control system (10) is not abrupt because the phase pull-in of the phase control system (10) is often large.

Therefore, in the present invention, even when the phase itself of the external reference signal is significantly disturbed as described above, the rotational phase control system (10) is configured to be soft-locked. It is designed so as not to follow suddenly.

SUMMARY OF THE INVENTION Therefore, according to the present invention, the phase of the external reference signal is discriminated, and when the phase of the external reference signal itself is largely deviated from the previous one, such as when switching channels, a phase comparator is used.
(4) It is configured to change the phase of the supplied internal reference pulse.

Embodiment Next, an example of applying the phase control circuit according to the present invention to the phase control circuit of the drum motor of the video tape recorder as described above will be described with reference to FIG.

According to the present invention, as shown in FIG. 3, the counter (2) is not directly reset by the vertical synchronizing pulse VD which is an external reference signal, but a plurality of reset pulses having different phases are formed in advance. , Vertical sync pulse V
A reset pulse forming circuit (20) for the counter (2) is provided so that the counter (2) can be reset by a different reset pulse when the phase of D is deviated by a predetermined amount or more. .

It should be noted that (9) is a circuit for waveform shaping, which outputs the reference pulse P _C3 of FIG.

FIG. 4 shows a specific example of the reset pulse forming circuit (20), which has means (21) for forming a window pulse P _W (FIG. 5C) formed on the basis of the output of the counter (2). .

A decoder is used as the forming means (21) in this example, and a decode output including at least the vertical synchronizing pulse VD is used as shown in FIGS. In this example, a decode output that becomes a window pulse including a certain period from the rising to the falling of the vertical synchronizing pulse VD is used.

The window pulse P _W and the vertical synchronizing pulse VD which is the external reference signal are respectively supplied to the reset pulse forming means (22), and the first synchronizing pulse VD is synchronized with the vertical synchronizing pulse VD as shown in FIGS. A second reset pulse synchronized with the falling or rising of the reset pulse P _RR and at least the window pulse P _W , in this example, second and third reset pulses P _RF obtained in synchronization with the rising and falling, respectively. , P _RB are formed.

These first to third reset pulses P _{RR to} P _RB are supplied as reset pulses for the counter (2) after one of them is selected by the reset pulse selection means (23). The selecting means (23) is constituted by switching means (23R), (23F) and (23B) as shown in the drawing, respectively, and these switching means (23R) to (23B) are control means (25) thereof.
Is controlled as desired.

The control means (25) selects the second or third reset pulse P _RF , R _RB when the period of the vertical synchronizing pulse VD fluctuates by more than the pulse width of the window pulse P _W , and otherwise selects the first pulse. The reset pulse P _RR is selected.

Therefore, in this example, a comparison circuit (26) for detecting whether or not the vertical synchronizing pulse VD is within the pulse width of the window pulse P _W is provided, and the vertical synchronizing pulse VD is inside the window pulse P _W. At this time, the internal pulse P _in is output from this, which causes the first switching means.
(23R) is controlled. That is, while the internal pulse P _in is obtained, the switching means (23R) is closed and the counter (2) is reset by the first reset pulse P _RR . Therefore, this state is exactly the same as the conventional phase control state.

When the vertical synchronizing pulse VD is not inside the window pulse P _W, the comparison from the circuit (26) outputs an external pulse P _out, second or third switching means when the external pulse P _out is output ( 23F) and (23B) are controlled. In this case, the reset pulse to be used differs depending on whether the vertical synchronizing pulse VD is included in the first half or the second half of the vertical cycle.

In this example, as shown in FIGS. 5A and 5B, when the vertical synchronizing pulse VD is in the latter half of the vertical cycle, the second switching means (23F) is closed and the second reset pulse P _RF is set to the counter (2 ). Therefore, when the vertical synchronizing pulse VD is in the first half of the vertical cycle, the third switching means (23B) is controlled so that the counter (2) is reset by the third reset pulse P _RB. To be done.

Therefore, this control means (25) has a pulse position discrimination circuit (27).
Is provided. This discrimination circuit (27) has a counter (2)
The first reference pulse P _C1 and the vertical synchronization pulse VD output from the first reference pulse P _C1 are supplied, and when the vertical synchronization pulse VD is in the high level section of the first reference pulse P _C1 , the second switching pulse When P _F is output and is in the low level section, the third switching pulse P
_B is output.

However, unless the external pulse P _out is output, the second and third switching pulses P _F and P _B are controlled so as not to be output.

Therefore, if the phase of the vertical synchronizing pulse VD is changed from the state of FIG. 6A to the state of B by switching the channel, for example, the vertical synchronizing pulse VD is changed to the window pulse P _W before the channel switching. The internal and external pulses P _in and P _out shown in FIGS. 6E and F are output from the comparison circuit (26) because they are distributed inside the circuit, and as a result, only the first switching means (23R) is closed, As described above, the counter (2) is reset by the reset pulse P _{RR of} 1 (Fig. 6G), but the phase of the vertical synchronizing pulse VD is changed as shown in Fig. 6 by switching the channel. In this case, since the vertical synchronizing pulse VD does not exist within the pulse width of the window pulse P _W , the comparator circuit 26 outputs the external pulse P _out .

Then, in this case, the vertical synchronizing pulse VD is present in the latter half of the first reference pulse P _C1 , and as a result, the second switching pulse P _F is output from the discriminating circuit (27). As a result, the second switching means (23F) is closed.

By the way, the window pulse P _W is the first reference pulse P _W
Since it is obtained after a predetermined period of time has elapsed from the rise of _C1 , that is, at the time when T has elapsed, as shown in FIGS. 6C and 6D, when the period of T arrives, the window pulse P
_W is generated. As a result, reset pulse forming means (22)
From which a second reset pulse P _RF is obtained, which is
It is supplied as a reset pulse to the counter (2) via the switching means (23F).

Therefore, the channel switching is performed by the first reset pulse P
Counter with the second reset pulse P _RF instead of _RR
(2) will be reset.

Here, the case of being reset by the first reset pulse P _RR formed based on the vertical synchronizing pulse VD after the channel switching and the case of being reset by the second reset pulse P _RF are the latter. The reset timing is delayed by T ₁ as shown in FIG.

The resetting of the counter (2) by the second reset pulse P _RF is continuously performed until the vertical synchronizing pulse VD falls within the window pulse P _W. Then, in this reset section II, the cycle of the second reset pulse P _RF is shorter than the cycle of the vertical synchronizing pulse VD by W _a, so that the delay of the reset timing is reduced by W _a for each cycle, and FIG. As described above, the timing is shortened from T ₁ to T ₄ , and the rising timing of the second reset pulse P _RF gradually approaches the falling timing of the vertical synchronizing pulse VD after switching.

Therefore, in the next section III, the vertical synchronizing pulse VD finally comes to exist within the pulse width of the window pulse P _W. Therefore, when reaching the reset section III, the internal pulse P _in is generated from the comparison circuit (26) this time. As a result, the generation of the second switching pulse P _F is stopped, and instead of this, the first switching means (23R) is controlled by the internal pulse P _in , so that the vertical synchronizing pulse V
Counter by first reset pulse P _RR based on D
(2) is reset. Since the first reset pulse P _RR is a pulse corresponding to the falling edge of the vertical synchronizing pulse VD, the reset operation similar to that before the channel switching is repeated by reaching the reset section III.

In this way, the vertical synchronization pulse V
By detecting the fluctuation range of D and resetting it by the second reset pulse P _RF when it is equal to or larger than a predetermined value,
A state in which the rising timing of the window pulse P _W is gradually approached to the vertical synchronization pulse VD after the channel switching so that the vertical synchronization pulse VD is completely within the pulse width of the window pulse P _W. Then, as usual, the counter is turned on by the first reset pulse P _RR.
It is designed to control (2).

As a result, the phase control system (10) does not perform abrupt phase control due to channel switching, and enters the soft lock state.

When the phase shift of the vertical synchronizing pulse VD is further advanced than in the case of FIG. 6 and is in the low level period of the first reference pulse P _C1 , the second reset based on the rising edge of the window pulse P _W. The phase is locked earlier based on the third reset pulse P _RB formed based on the trailing edge of P _W than the pulse P _RF . Therefore, in such a case, the determination circuit (27) may control the third switching means (23B) by the switching pulse P _B. Note that this explanation is omitted because it is the same as the above.

Although the pulse width of the window pulse P _W described above is arbitrary, if the width is made wider than that described above, the soft lock is further achieved.

The present invention can also be applied to a capstan and other phase control circuits for rotating bodies.

According to the configuration of the present invention described above, when the phase of the vertical synchronizing pulse VD fluctuates due to channel switching or the like, when the fluctuation width is within the pulse width of the window pulse P _W , , The counter (2) is reset by the first reset pulse P _RR , and in other cases, the second or third reset pulse P _RF , P _RB depending on the phase of the vertical synchronizing pulse VD. Since the counter (2) is reset by means of the internal reference pulse P in the phase inversion control system (10), the internal reference pulse P has a more gradual phase variation than the vertical synchronizing pulse VD.
_{Since C3} is supplied, closed phase control is performed so that the phase is locked to the internal reference pulse P _C3, and as a result, the phase inversion control system (10) is soft locked. Therefore, it is possible to eliminate various effects due to the abrupt phase lock.

[Brief description of drawings]

FIG. 1 is a system diagram showing an example of a conventional motor phase control circuit, FIG. 2 is a waveform diagram for explaining the operation thereof, and FIG. 3 is a motor phase control circuit according to the present invention for a drum motor control system. FIG. 4 is a system diagram showing an example when applied, FIG. 4 is a system diagram showing an example of a pulse forming circuit, and FIGS. 5 and 6 are waveform diagrams for explaining the operation thereof. (2) is a counter for generating an internal reference pulse, (10) is a phase control system, (20) is a reset pulse forming circuit, (21) is a window pulse P _W forming means, and (22) is a reset pulse P. _RR
To P _RB forming means, (23) pulse selecting means, (25) controlling means thereof, and P _{C1 to} P _C3 are first to third internal reference pulses.

Front Page Continuation (72) Inventor Kenji Nakano 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa Soni-Atsugi Plant (56) References JP-A-54-114691 (JP, A)

Claims (1)

[Claims] 1. A counter (2) for dividing a reference clock, a rotation phase control system (10) for a motor (5) which uses the counter output of this counter (2) as an internal reference pulse, and the counter (2). ) Reset pulse forming circuit (20)
The reset pulse forming circuit (20) includes a window pulse forming means (21) formed on the basis of the counter output, and the external vertical synchronizing pulse from the window pulse and the external vertical synchronizing pulse. Reset pulse formation for obtaining a first reset pulse generated in response to a pulse and at least a second reset pulse and a third reset pulse generated in the vicinity of the rising or falling of the window pulse in response to the window pulse Means (22) and reset pulse selecting means (23) for selecting one of the plurality of reset pulses and supplying it to the counter (2)
And when the external vertical sync pulse is not within the pulse width of the window pulse, the second or third reset pulse is selected according to the position of the vertical sync of the external vertical sync pulse, and otherwise the above Means for controlling the reset pulse selecting means (23) so as to select the first reset pulse
(25) A motor phase control circuit having: