JPH0677251B2 - Slave processor control system - Google Patents

Description

The present invention relates to a control system for a slave processor, and more particularly to a control system for detecting a connection state between a master processor and a slave processor.

<Prior Art> In a microprocessor formed on a single chip as a large-scale integrated circuit (LSI), there is a limit to the number of elements that can be integrated in the chip, so high-performance instructions such as floating-point arithmetic are executed. It is difficult. Therefore, a method is widely used in which the instruction set is divided into a basic instruction and a high-performance instruction that requires a large-scale arithmetic circuit, and the basic instruction is executed by a master processor and the high-performance instruction is executed by a slave processor. There is. A master processor is a processor that can operate as a central processing unit (CPU) by itself. The slave processor is a processor that executes, in place of the master processor, high-performance instructions that cannot be executed by the master processor. The master processor and the slave processor are each composed of a one-chip LSI. In order to reduce the connections between chips and minimize the number of terminals on each chip, the data bus between the master processor and the main memory is It is usually shared with slave processors.

NS32332 and NS32081 are examples in which a master processor and a slave processor are realized by one chip. The interface and communication procedure between the master processor NS32332 and the slave processor NS32081 are described in "NS32332 32-Bit Advanced Microprocessor with Vir.
tual Memory, 1985 National Semiconductor Corporati
on ”.

A hardware configuration of a conventional example is shown in FIG. The master processor 110 functions as the central processing unit of the system,
Slave processor 120 executes the extension instructions of master processor 110. Memory 130 is the master processor 110
Is a main storage device accessed by. address·
Data bus 144 consists of master processor 110, slave
A bus for transmitting and receiving data between the processor 120 and the memory 130, the bus status 143 is driven by the master processor 110, and the address data bus 1
Address / data senders and receivers on 44 are used to designate master processor 110, memory 130, or slave processor 120. The slave processor present flag 115 is included in the master processor 110 and indicates whether or not the slave processor 120 is connected to the master processor 110. The master processor 110 can branch the flow of control according to the value of the slave processor present flag 115. The end signal 153 is a negative logic signal indicating the end of execution of the operation on the slave processor 120 with a low level pulse, and is open-drain connected to the slave processor 120 and is not driven. At this time, it is kept at a high level by the pull-up resistor 152.
The master processor 110 is supplied with the end signal 153 and can branch the control flow according to the level of the end signal 153.

Master processor 1 with instructions for slave processor 120
A flowchart illustrating the operation of master processor 110 when 10 is decoded is shown in FIG. The instruction executed in FIG. 6 is a binary operation such as A + B → B. The A is called the first operand and the B is called the second operand. First, the master processor 110 checks the slave processor present flag 115 (601), and if the slave processor 120 is connected to the master processor 110, the procedure described below is performed. Meanwhile, slave processor 12
If a 0 is not connected to master processor 110, master processor 110 does not perform the procedure described below and issues an undefined instruction exception (610).

When the slave processor present flag 115 indicates the presence of the slave processor 120, the master processor 1
10 is the instruction code of the instruction for the slave processor 120,
The bus status 143 and the address / data bus 144 are operated to transfer to the slave processor 120 (602).
Next, the master processor 110 transfers the data of the first operand from the memory 130 to the bus status 14 (if necessary).
3 and address data bus 144 to operate the slave
Transfer to processor 120 (603) and likewise transfer the second operand (if necessary) to slave processor 120 (604). When all the instruction codes and data necessary for executing the slave processor instruction have been transferred, the slave processor 120 starts executing the operation, and after the execution of the operation ends, the end signal 153 is shifted to the low level for a certain period.
The master processor 110 waits until the operation of the arithmetic unit 121 is completed by checking the end signal 153 (605). After that, the master processor 110
A value indicating the status (status) is input from the processor 120 via the address data bus 144 (606), the status value is checked (607), and if the status value indicates normal end, The bus status 143 and the address / data bus 144 are operated to read the operation result from the slave processor 120, and the second result on the memory 130 is read.
Write to the operand (608) and end the instruction. In the status check (607), if the status value indicates that an exceptional event has occurred in the operation, the master processor 110 issues a slave processor operation exception (609).

FIG. 7 shows a time chart from the writing of the instruction code (602) to the reading of the status (606) among the steps shown in FIG. The transfer of operands (603, 604) is omitted when it is not necessary.

When the master processor 110 controls to write the instruction code to the slave processor 120 (timing 701
(602)), bus status 143, address data
Bus 144 is driven to perform a write bus cycle to command port 122. After the end of the bus cycle (timing 702), the slave processor 120 starts the arithmetic operation in the arithmetic unit 121, and the master processor 110 waits until the end signal 153 becomes low level (605). When the arithmetic operation in the slave processor 120 is completed (timing 703), the end signal 153 becomes low level for a certain period, and the master processor 110 shifts to the next processing (606).

Then slave processor 120 becomes master processor 1
The case where it is not connected to 10 is described.

In FIG. 6, the master processor 110 is a slave
The processor present flag 115 is checked (601), and if the slave processor 120 is not connected to the master processor 110, the master processor 110 does not execute the instruction execution procedure and generates an undefined instruction exception (610). The master processor 110 allows the slave processor 12 to write an exception handler routine with an undefined instruction exception.
0 can be emulated in software.

If the slave processor 120 is not connected but the slave processor presence flag 115 indicates the presence of the slave processor 120 (which is an abnormal use), the following problems occur. At this time, the end signal 153 is kept at the high level by the pull-up resistor 152. Therefore, the master processor 110 checks the end signal 153 (605) in the flowchart of FIG.
Can't get out of the waiting state and falls into an infinite waiting state. The above indicates that the slave processor present flag 115 is indispensable.

Next, consider a computer system in which a plurality of slave processors are connected to the master processor 110. The hardware configuration is shown in FIG.

Slave processors 811, 812, 813 are equivalent to slave processor 120 of FIG. Slave processor presence flags 821, 822, 823 are equivalent to the slave processor presence flag 115 of FIG.
Indicates whether slave processors 811, 812, 813 are connected to master processor 110, respectively. For example, when executing an instruction for slave processor 812, master processor 110 checks slave processor present flag 822 and executes the instruction if slave processor 812 is shown to be present. This means that the number of slave processor present flags does not mean how many slave processors are connected to the master processor 110, but how many slave processors can be connected to the master processor 110. Indicates that it will be decided.

<Problems to be Solved by the Invention> However, the conventional system including the master processor and the slave processor had the following two problems. That is, the first problem is that the instruction execution time increases because the slave processor present flag 115 must first be checked by the slave processor instruction execution means (FIG. 6). Although this check is effective in the computer system to which the slave processor 120 is not connected, it only reduces the operation speed and increases the instruction execution time in the computer system to which the slave processor 120 is connected. The second problem is that when a plurality of slave processors can be connected to the master processor 110, the same number of slave processor presence flags as the maximum number n of slave processors connectable to the master processor 110 are required. That is.
Therefore, when the maximum number n of slave processors that can be connected is large, a large number of slave processor present flags must be formed for slave processors that are less frequently connected to the master processor 110.
The burden on the hardware was increasing. However, one slave processor presence flag is used for multiple n
When the presence / absence of the slave processor is attempted to be expressed, the undefined instruction exception is not correctly executed unless n slave processors are connected or no slave processors are connected at all.

In order to solve such a problem, it is desirable to check the presence / absence of a slave processor in the slave processor instruction execution procedure without preparing the slave processor presence flag. Therefore, in the slave processor instruction execution procedure of FIG. 6, a step of reading the status (606) and its check is provided, and if the status value is an abnormal value, it is determined that the slave processor does not exist. In this method, the slave processor present flag is not necessary, so the above two problems are solved. This method is based on the document “MC68020 32-Bit MICROPRO
CESSOR User's Manual ",
According to this document, since the master processor knows the end of operation of the slave processor by checking the status instead of the end signal, a new problem that the data bus is occupied by reading the status during the operation of the slave processor Dots occur. In order not to cause such a new problem, it is absolutely necessary to notify the end of calculation by the end signal.

Therefore, although the above-mentioned conventional example has an advantage that the data bus is not occupied by the reading of the status during the operation of the slave processor, it has the above-mentioned problems and the master processor 110 When the slave processor instruction execution procedure of FIG. 6 is executed from the instruction code transfer (602) when the slave processor 120 is not connected to the master processor 110, the end signal 153 remains at high level and the master processor 110 waits indefinitely. There is also the problem of falling into a state.

<Means, Actions and Effects for Solving Problems> The present invention is a slave which shares a data bus with a master processor functioning as a central processing unit and is controlled by the master processor to expand the function of the master processor. First means capable of supplying data necessary for execution of an operation by a slave processor via the data bus and determining the state of the slave processor as a processor control system A second means for discriminating the use state of the data bus for supplying data by the first means; and a third means for discriminating that the slave processor is executing an arithmetic operation by the state notifying means. And the master processor has the slave means by the first means.
After causing the processor to start executing an operation, detecting the end of use of the data bus by the first means by the second means, and confirming by the third means that the slave processor is not executing an operation, It is characterized in that whether or not the slave processor and the master processor are connected is discriminated based on the state of the slave processor discriminated by one means. Therefore, according to the control method of the slave processor according to the present invention, the flag for confirming the presence / absence of the slave processor becomes unnecessary, the instruction execution speed is improved, and the hardware is reduced. And the master processor can effectively identify the slave processor's unconnection.

<Example> Next, the Example of this invention is described with reference to drawings.

FIG. 1 is a block diagram showing a hardware configuration of a slave processor control system according to an embodiment of the present invention. The master processor 150 is a central processing unit, the slave processor 160 is a slave processor that executes the extended instructions of the master processor 150, and the memory 170 is the master processor.
A main storage device accessed by the processor 150. The data bus 182 is a bus for receiving data between the master processor 150, the slave processor 160 and the memory 170, and the address bus 181 is the master processor 1
It is a bus driven by 50 and for designating addresses of the memory 170 and the slave processor 160.

The master processor 150 includes an instruction decode unit 153 that decodes instructions executed by the master processor 150 and the slave processor 160, an effective address calculation unit 154 that calculates an operand address of the instruction,
A memory 17 that controls an execution unit 151 and a address bus 181 and a data bus 182 that are controlled by a micro program that controls the entire master processor 150 to execute instructions.
0 and a bus control unit 152 for accessing the slave processor 160.

Slave processor 160, slave processor 160
Unit 161, which executes the calculation of instructions for
Command port 162 that inputs the instruction code of the instruction executed by arithmetic unit 161 from bus 182, status port 1 that outputs the state of arithmetic unit 161 to data bus 182
63, the operand port 164 for inputting the data necessary for the operation of the operation unit 161, and outputting the operation result, and the command port 16 by decoding the value of the address bus 181
2. Status port 163 and address decode 165 for selecting the operand port 164.

The busy signal 190 is a negative logic signal that indicates at low level that the arithmetic unit 161 of the slave processor 160 is executing. The busy signal 190 is driven by the open drain from the slave processor 160, and is pulled up when not driven. It is kept at a high level by 192. The execution unit 151 of the master processor 150 uses the busy signal
190 and a bus status signal 191, which indicates whether the bus control unit 152 is executing a bus cycle, and signals 190, 19
A value of 1 allows the control flow to branch.

The operation of the execution unit 151 when the instruction decoding unit 153 decodes the instruction for the slave processor 160 is shown in a flowchart in FIG. The instruction executed in FIG. 2 is a binary operation such as A + B → B.
The operand B is called the second operand.

First, the execution unit 151 controls the bus / control unit 152 to transfer the data of the first operand from the memory 170.
Write to operand port 164 via bus 182 (20
1), similarly, write the second operand to the operand port 164 (202). Next, the execution unit 151 converts the instruction code input from the instruction decoding unit 153 into a bus code.
Control unit 152 to write to command port 162 via data bus 182 (203). The command
When a bus cycle for writing to the port 162 is performed, the arithmetic unit 161 of the slave processor 160 starts executing an arithmetic operation, and drives the busy signal 190 at a low level during the arithmetic operation. The master processor 150 waits until the write bus cycle is complete by checking the bus status signal 191 (204) and then the busy signal 1
By checking 90, the operation unit 161 waits until the operation is completed (205). Thereafter, the execution unit 151 inputs the value (status) of the status port 163 of the slave processor 160 via the bus control unit 152 and the data bus 182 (206) and checks the status value (207). ), If the status value indicates normal termination, the operation result is read from the operand port 164 via the bus / control unit 152 and the data bus 182 and written to the second operand on the memory 170 (208), Finish the instruction. In the status check (207), if the value of the status indicates that an exceptional event has occurred in the operation, the execution unit 151 issues a slave processor operation exception (209). If the status value shows an abnormal value other than the specified value, the execution unit 151 determines that the slave processor 160 is not connected to the master processor 150, and
Generate a processor out exception (210).

FIG. 3 shows a time chart from the writing (203) to the command port 162 to the reading (206) of the status port 163. When the execution unit 151 instructs the bus control unit 152 to write the instruction code to the command port 162 (301), the bus control unit 15
2 drives address bus 181, data bus 182,
Perform a write bus cycle to command port 162. Bus status signal during the bus cycle
191 is high and execution unit 151 is waiting (204). After the end of the bus cycle (302), the slave processor 160 starts the operation in the operation unit 161, and simultaneously drives the busy signal 190 to the low level, and the execution unit 151 waits until the busy signal 190 becomes the high level ( 205). When the calculation in the calculation unit 161 is completed (303), the busy signal 190 becomes high level, and the execution unit 151 moves to the next process (206).

Then slave processor 160 becomes master processor 1
The case when not connected to 50 is described.

At this time, the busy signal 190 is kept at the high level by the pull-up resistor 192. Also, the master processor 150
When a bus cycle that reads the status port 163 is executed, since there is nothing that drives the data bus 182, all high level values or all low level values are input. Therefore, the master processor 150 checks the busy signal 190 (2
05) does not enter the waiting state, and the status value check (207) generates a slave processor absence exception because the status values are all 0 or 1 as an abnormal value. The master processor 150 uses the exception handler routine description in the slave processor absent exception to
The slave processor 160 can be emulated in software.

As described above, in the present embodiment, after the writing to the command port, the operation start in the slave processor 160 is not confirmed, but only the operation end is confirmed. Therefore, even if the slave processor 160 is not connected,
Processor 150 never goes into an infinite wait state.

Further, by detecting (206) and checking (207) the status port to detect the non-connection of the slave processor 160, it is not necessary to prepare a flag as in the conventional example. Check the status (207)
Are necessary for finding an arithmetic exception in the arithmetic unit 161, and the execution of the slave processor instruction is not delayed due to the detection of the slave processor non-connection.

Next, consider a computer system in which a plurality of slave processors are connected to the master processor 150. The hardware configuration is shown in FIG. Slave processors 411, 412, 413 are slave processors 1 in FIG.
It is equivalent to 20.

Command port 162, status port 163, operand port 16 of slave processors 411, 412, 413
Since 4 is placed in its own address space, multiple ports cannot be accessed at the same time.
The busy signal 190 is also driven by the slave processor that is executing the operation. This means that, regardless of the number of slave processors controlled by the master processor, execution of instructions for the slave processor may occur between the master processor 150 and the executing slave processor.
It shows that it is done in one-to-one.

For example, when executing instructions for slave processor 411, master processor 110 may
Since only the 11 ports are accessed and the busy signal 190 is driven by the slave processor 411, the slave processor control procedure of FIG. 2 is executed normally. If the slave processor 411 is not connected, the busy signal 190 remains high because it is not driven, and the read status is an abnormal value of all 1s or all 0s. An exception occurs.

As described above, in this embodiment, even if the number of slave processors that can be connected to the master processor increases, the increase in hardware as described in the conventional example does not occur,
It is possible to realize a slave processor disconnection detection method with a wide range of applications.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a flow chart of one embodiment, FIG. 3 is a timing chart of one embodiment, and FIG. Block diagram when a processor is connected, No. 5
FIG. 6 is a block diagram of a conventional example, FIG. 6 is a flowchart of the conventional example, FIG. 7 is a timing chart of the conventional example, and FIG.
The figure is a block diagram when a plurality of slave processors are connected in the conventional example. 150 …… master processor, 151 …… execution unit, 152 …… bus control unit, 153 …… instruction decode unit, 154 …… instruction address calculation unit, 160 …… slave processor, 170 …… memory, 182 …… Data bus, 190 ... busy signal, 191 ... bus status signal.

Claims (1)

[Claims] 1. A master processor that shares a data bus with a master processor functioning as a central processing unit and is controlled by the master processor to expand the functions of the master processor, thereby providing a slave processor control system, The processor is capable of supplying data necessary for execution of an operation by the slave processor via the data bus and is capable of discriminating the state of the slave processor; and a first means (163); Second means (191) for determining the use state of the data bus for supplying data by means, and means for notifying the state of the slave processor determine that the slave processor is executing an operation. Third means (190), wherein the master processor has the slave means by the first means. The processor is made to start executing the operation, the second means detects the end of use of the data bus by the first means, and the third means confirms that the slave processor is not executing the operation. After that, the control of the slave processor is characterized in that whether or not the slave processor and the master processor are connected is identified based on the state of the slave processor determined by the first means. method.