JPH0675337B2 - Digital data recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a DAT (digital audio tape recorder), a VT.
The present invention relates to a data recorder such as an R (video tape recorder) which realizes time-axis (input / output speed) conversion of input / output data by using a digital recording type data recorder using a rotary head as a recording / reproducing device.

[Conventional technology]

Conventionally, for data recorders that can arbitrarily convert the time axis,
An analog data recorder can be mentioned.
There are FM and DR type recorders as analog type data recorders, which can easily convert the input / output data to the time axis by changing the tape speed and the modulation / demodulation time according to the tape speed. For example, data recorded over 10 hours can be reproduced in 10 minutes, or data recorded in 1 second can be reproduced in 10 minutes.
Since the recording time and playback time can be set separately, when such a data recorder is built into a measuring device,
There is an advantage that data conversion can be performed according to the object of data measurement and the convenience of the processing system.

However, the analog data recorder has an SN ratio of 30-
It is about 50 dB, and there are various problems such as low reliability of data due to the influence of noise, and various unstable factors due to the analog method.

[Problems to be solved by the invention]

By the way, compared to analog data recorders,
A PCM data recorder is a digital data recorder that significantly improves the reliability of data. However, in the rotary head type tape recorders such as R-DAT and VTR, the variable range of the input / output speed of data that can be accurately recorded and reproduced is limited to an extremely narrow range (about ± 10%). It is impossible to make a significant time-axis conversion such as.

Further, the fixed head type tape recorder is capable of a large time axis conversion like an analog data recorder, but has a drawback that the recording density is low because of the fixed head.

Therefore, the present invention realizes a time axis conversion equivalent to that of a conventional analog data recorder by using a tape recorder of a rotary head type having high reliability of data as a recording / reproducing means.

[Means for solving problems]

The digital data recorder according to the present invention stores a digital signal up to a predetermined storage capacity temporarily (memory 6A, 6B), and records the data read from this storage means, or records it by itself. Recording / reproducing means (recording / reproducing device 4) of a magnetic tape recording / reproducing system using a rotary head for outputting reproduction data to the storage means, and when recording input data, the input data is sequentially transferred to the storage means at the data speed. In addition to writing the data to the recording means, the data is read from the storage means at a speed corresponding to the unique recording speed of the recording / reproducing means and intermittently recorded in the recording / reproducing means, and at the time of reproducing the output data, The data reproduced from the recording / reproducing means is sequentially written into the storage means at the reproduction speed unique to the recording / reproducing means, and the data is recorded. Data is read out from the storage means as output data of the apparatus at an arbitrary speed not exceeding the writing speed, and the output is made continuous data in time. When recording the read data in the recording / reproducing means, the first margin area is recorded before recording the data,
Next, a write / read control unit (write / read control unit 10) for recording the data and then for recording the second margin area is provided.

[Action]

The storage means (memory 6A, 6B) is a recording / reproducing means (record
Installed on the input / output side of the playback device 4), input / output data Di,
Do is temporarily stored up to a predetermined storage capacity, and from the viewpoint of the recording / reproducing means, it is controlled by the writing / reading control means (writing / reading control unit 10) and is a special time axis conversion means. It functions as a buffer memory.

Writing / reading control means (writing / reading control unit 10)
At the time of data recording, the input data Di is sequentially written into the storage means (memory 6A, 6B) at the data speed, and the data is compatible with the unique recording speed of the recording / reproducing means (recording / reproducing device 4). Then read from the storage means and record
When the data is reproduced, the data reproduced from the recording / reproducing means is sequentially written into the storing means at the time of intermittently recording the data in the reproducing means, and the data is continuously recorded from the storing means. Control operation to read out as output data Do.

Therefore, while the recording / reproducing means always records and reproduces the data with a fixed time axis, the storage means controls the time axis arbitrarily by the writing / reading control means to measure the data (data acquisition target). It is possible to change the time axis corresponding to the side receiving the data supplied from the recording / reproducing means (the data receiving side).

Therefore, the digital data recorder of the present invention can perform time axis conversion equivalent to that of the conventional analog data recorder, and can further function as a data recorder capable of following the data receiving side with high accuracy.

〔Example〕

FIG. 1 shows an embodiment of a digital data recorder of the present invention.

The terminal 2 is provided as an input / output terminal for adding input data to be recorded or extracting reproduction output data.

A recording / reproducing device 4 is installed as recording / reproducing means for recording data and reproducing recorded data. Record
The reproducing device 4 is, for example, an R-DAT, VTR, PCM processor or the like, which can record and reproduce digital data by utilizing a rotary head, and has a variable range of input / output speed of data that can be accurately recorded and reproduced. Is extremely narrow (about ± 10
%) A device such as an analog data recorder that is not capable of significant time axis conversion is used.

The data input / output unit of the recording / reproducing apparatus 4 has a recording / reproducing function.
Two memories 6A and 6B are installed as storage means for storing the input data to be recorded in the reproducing device 4 and storing the reproduced data reproduced from the recording / reproducing device 4.
Data input / output units 8A and 8B are installed on the external input / output side of data for A and 6B and on the data input / output side of the recording / reproducing apparatus 4.

Each of the data input / output units 8A, 8B and each of the memories 6A, 6B has a writing / reading control unit 10 installed as a writing / reading control unit that writes the input data Di and the output data Do to the memories 6A, 6B. Read from 6B. Each data input / output unit 8A, 8B is shown with equivalent switches S ₁ , S ₂ for writing and reading data.

Recording and reproducing operations in such a configuration will be described.

In FIG. 1, an arrow P indicated by a solid line indicates a direction of the input data Di, and an arrow Q indicated by a broken line indicates a direction of the reproduction output data Do.

At the time of data recording, the input data Di digitized by the A / D converter is input from the terminal 2 and a fixed amount (N samples) is stored in the memories 6A and 6B via the contacts a and b of the switch S _1. Alternately and continuously written. That is, in a specific section, the switch S ₁ is connected to the memory 6A.
, The input data Di is stored in the memory 6A.
Written as sample data. Then switch S ₁
Is closed at the contact b on the memory 6B side, and the input data Di is written in the memory 6B as N sample data. By repeating such an operation, the input data Di for every N samples is written in the memories 6A and 6B without interruption.

Then, while the input data Di is being written in the memory 6A, the switch S ₂ is closed to the contact point d side to read N samples of the data stored in the memory 6B, input the data to the recording / reproducing apparatus 4, and record the data. That is, the input data Di is stored in the memory 6A as N
While writing the sample, N samples of data are read from the memory 6B and recorded in the recording / reproducing apparatus 4. Next, while writing N samples of the input data Di into the memory 6B, the switch S ₂ is closed to the contact c side, and the memories 6A to N
The operation of reading the sample data and recording it in the recording / reproducing apparatus 4 is repeated. Therefore, recording of data for each N samples in the recording / reproducing apparatus 4 is performed intermittently.

FIG. 2 shows an operation sequence during such data recording.

In FIG. 2, a is input data Di, b is writing N sample data to the memory 6A, c is writing N sample data to the memory 6A, d is reading N sample data from the memory 6A, and e is memory. Reading of N sample data from 6B, f shows recording of N sample data in the recording / reproducing apparatus 4.

That is, the input data Di is written alternately in each of the memories 6A and 6B over a time period of T ₁ every N samples. By assigning numbers to the data sets of N samples, n, n + 1, n + 2, ..., While the input data Di is being written to one memory 6A, the data is written from the other memory 6B at the previous time T _1. The data of N samples is read over the time T ₃ and recorded in the recording / reproducing device 4. Recording / playback device 4
Is activated each time the writing of N samples of data to each memory 6A, 6B is completed, and while recording the identifiers indicating the dummy data and Mie data areas at time T ₂ ,
Enter stable operation state. Then, after recording the data of the N samples for the next time T _3, and stops recording an identifier indicating the dummy data and the dummy data area on the time T _4. T ₅ is a free time until the next activation.

The dummy data area recorded at time T ₂ is called a pre-margin area, and the dummy data area recorded at time T ₄ is called a post-margin area.

Here, T ₂ + T ₃ + T ₄ ≦ T ₁ (1), and the left side is always less than a certain value.

The times T ₂ and T ₄ slightly fluctuate due to the mechanical fluctuation of the response speed of the recording / reproducing apparatus 4, but they do not exceed a certain maximum value. The time T ₃ depends on the predetermined data recording speed of the recording / reproducing apparatus 4 and the number N of data samples, and is constant. The time T ₁ can be set arbitrarily within a range that satisfies the relationship of the expression (1).

Next, in the reproduction mode, the output data Do supplied to the D / A converter or the like is continuously read out alternately from the memories 6A and 6B by a fixed amount (N samples) via the switch S ₁ , It is output from 2. Ie switch
S ₁ is closed to the contact a side, it reads out and outputs data of N samples from the memory 6A. Next, switch S ₁ has contact b
It is closed to the side, and the operation of reading and outputting N samples of data from the memory 6B is repeated. Therefore, the output data Do can be read from the memories 6A and 6B without interruption.

In such a reproducing operation, the switch S ₂ is closed to the contact d side while reading the data from the memory 6A, and N samples of data reproduced from the recording / reproducing device 4 are written in the memory 6B. That is, while reading and outputting N samples of data from the memory 6A, recording / recording is performed.
N samples of data are reproduced from the reproducing device 4 and stored in the memory 6B.
Write in. Next, while reading and outputting N samples of data from the memory 6B, the switch S ₂ is closed to the contact c side, the next N samples of data are reproduced from the recording / reproducing device 4, and written in the memory 6A. The operation is repeated. Here, the reproduction of data for each N samples from the recording / reproducing apparatus 4 is intermittently performed.

FIG. 3 shows an operation sequence during such reproduction.

In FIG. 3, a is output data Do, b is N sample data read from the memory 6A, c is N sample data read from the memory 6B, d is N sample data write to the memory 6A, and e is memory. Writing of N sample data to 6B, and f indicates reproduction of N sample data from the recording / reproducing device 4.

That is, the output data Do is alternately read from the memories 6A and 6B over a time period T ₆ for each N samples. In this case, n, n + 1, n + 2, ...
・ ・ And number. While the one memory 6A is reading the output data Do, the data of N samples reproduces over T _'3 time from the recording and reproducing apparatus 4 writes the other memory 6B. The recording / playback device 4 has a memory
6A, the reading of data N samples from 6B is started every time the ends, enters a stable operating state while reproducing the dummy data of the pre-margin area to the time T _'2. Then, 'after playing data of N samples _3, time T' next time T stop playing the dummy data post margin area _4. T ₇ is the free time until the next activation.

Here, T ′ ₂ + T ′ ₃ + T ′ ₄ ≦ T ₆ (2), and the left side is always below a certain value.

Recording and reproducing apparatus 4 mechanical time T by variations in the response speed _{'2, T' 4} is slightly changed, it does not exceed a certain maximum value. Further, this maximum value is regarded as the same value during recording and reproduction. Time T _'3 is dependent on a predetermined data reproduction speed of a recording and reproducing apparatus 4 and the number of data samples N, T ₃ =
T _'is a ₃ a is a constant. Therefore, T ₂ + T ₃ + T ₄ ≤T ₆
T ₆ can be set arbitrarily within the range that satisfies.

As described above, since T ₂ + T ₃ + T ₄ ≦ T ₁ , T ₆ ,
The input data rate during recording (T ₁ per N sample) and the output data rate during playback (T ₆ per N sample) are set independently and independently of each other within the range of formula (2) without any restrictions. It has been shown that the time axis conversion of input / output data in recording and reproduction is possible.

Then, in the process of recording and reproducing, the recording / reproducing device 4
The data recording speed and the data reproducing speed are constant speeds that are unique to the recording / reproducing device 4 and are constant.
The speed of writing the input data Di from the terminal 2 to 6A and 6B and the speed of reading the output data Do from the memories 6A and 6B and outputting from the terminal 2 are independent and can be set arbitrarily. That is, the speed of the input data Di at the time of recording and the speed of the output data Do at the time of reproducing can be set independently, which allows the time axis conversion of the input / output data.

Although two sets of memories 6A and 6B are used in the embodiment, the number of sets of this memory is arbitrary. For example, when three sets of memories are used, the switches S ₁ and S ₂ may be switched at three points respectively, and the switches may be sequentially switched so that the write and read memories do not overlap.

Next, FIG. 4 shows a concrete embodiment of the digital data recorder of the present invention.

In this embodiment, a rotary head type digital audio tape recorder (R) is used as the recording / reproducing apparatus 4 of the above embodiment.
-DAT) 40 is used. The recording / reproducing data input / output of the R-DAT 40 uses digital input / output of the signal processing unit 41 instead of analog input / output. And this R-DAT40
Includes a rotary head 402, a signal processing unit 401, and a mechanism control unit 403, and the signal processing unit 401 and the mechanism control unit 403 are controlled by the write / read control unit 10 including a system control microcomputer or the like.

Two sets of memory 6 for recording N samples of data
A and 6B are installed, and the memory switching clock CK ₁ that inverts every N samples of external input / output data Di and Do is the external input / output data timing control unit 80 of the data input / output units 8A and 8B.
Made by 1, which allows the reading of memories 6A, 6B,
The write state (RD / WR) is reversed. That is, when one of the memory 6A is in a WR state, the memory 6A is WR data D _WR is written into the address AD is set at WR address counter 805, this time, the other memory 6B in RD state
RD data D _RD is read from the address AD set by the RD address counter 806. Memory switching clock C
RD / WR address selectors 807, 809, RD / WR control selectors 808, 810, WR data three-state buffer 81 to switch the RD / WR settings of the memories 6A and 6B by K ₁ .
1, 812 and RD data memory selector 813 are installed.

At the time of recording, the external input data Di is written in the memories 6A and 6B, and the data read from the memories 6A and 6B is R-DAT4.
It is input to the signal processing unit 401 of 0 and recorded on the tape 404.

At the time of reproduction, the reproduction data from the tape 404 is R
-The data output from DAT40, written to memories 6A and 6B, and read from memories 6A and 6B is the external output data Do.
Becomes

The recording / reproducing memory access control unit 803 and the recording / reproducing data flow control unit 8 are provided to switch the writing / reading control of the memories 6A and 6B and the flow of data by recording / reproducing.
04 is installed.

The operation of the above configuration will be described.

At the time of recording, as shown in FIG. 5, WR address counter 805
The counter control is performed by the external input / output data timing control unit 801 together with the supply of the clock CK ₂ to the WR control signal from the data clock CK ₂ to the memories 6A and 6B in the recording / reproducing memory access control unit 803. To be done.
The data clock CK ₂ is a signal synchronized with one sample of the external input data Di. The memory switching clock CK ₁ is inverted every N data clocks CK ₂ . Since the memory switching clock CK ₁ and the data clock CK ₂ are completely synchronized, the external input data Di is not interrupted even at the changing point of the memory switching clock CK ₁ .
The data is written in the memories 6A and 6B alternately.

In this case, as shown in FIG. 5, the RD address counter 80
The data clock CK ₂ of the R-DAT 40 is supplied to the clock of 6, and the counter control is performed by the R-DAT input / output data counter control unit 802. From the data clock CK ₂ , the recording / reproducing memory access control unit 803 stores the memory. RD to 6A, 6B
A control signal is created. This data clock CK ₂ is R
-This signal is synchronized with one sample of recorded data to DAT40. The data clock CK ₂ has a frequency unique to the R-DAT 40, and is 96 kHz, for example.

At the time of recording, as shown in FIG. 6, the external input data Di becomes the WR data D _WR to the memories 6A and 6B, and the memory 6
The RD data D _RD from A and 6B becomes the recording data to the R-DAT 40.

Next, during playback, as shown in Figure 7, WR
Data clock CK from R-DAT40 to address counter 805
₂ is supplied to the R-DAT input / output data counter control unit 80
The control is performed at 2, and the RD address counter 806 is supplied with the data clock CK ₂ from the external input / output data timing control unit 801 and is also controlled. WR control signal is R-DAT4
The RD control signal from the data clock of 0 is generated from the data clock CK ₂ of the external input / output data timing control unit 801.

The data clock CK ₂ is a signal synchronized with one sample of the external output data Do, and the memory switching clock CK ₁ is inverted every N data clocks CK ₂ . Since the memory switching clock CK ₁ and the data clock CK ₂ are completely synchronized, the external output data Do is not interrupted even at the change point of the memory switching clock CK ₁ without any interruption.
It is read from 6A and 6B. By the way, the data clock CK ₂ of the R-DAT 40 is the same and fixed during recording and reproduction.

During reproduction, as shown in FIG. 8, the reproduction data from the R-DAT 40 becomes the WR data D _{WR to} the memories 6A and 6B, and the RD data D _RD from the memories 6A and 6B is the external output data D.
It becomes o.

The external input / output data timing control unit 801 divides the data clock of the R-DAT 40 to generate the data clock CK ₂ of the external input / output data Di, Do. The frequency of this data clock CK ₂ is variable, and it is 48kH against 96kHz of R-DAT40.
z, 24kHz, 12kHz, etc. can be set by the write / read controller 10. By setting different frequencies for recording and reproducing, time axis conversion becomes possible.

Memory switching clock CK ₁ is made from the data clock CK _2, inverted every N data clock CK _2. Each time the memory switching clock CK ₁ is inverted, the address AD of the WR address counter 805 is cleared at the time of recording and the address AD of the RD address counter 806 is cleared at the time of reproduction to return to 0.

The R-DAT input / output data counter control unit 802 uses the R-DAT40
Controls the counter for input / output of data on the side. Data recording / reproduction is handled as one frame of R-DAT40 (2880 data of two tracks) as one unit.
The address counters 805 and 806 are controlled (cleared and count enabled / disabled) in synchronization with the frame clock CK ₃ of the DAT 40.

In this embodiment, the margin area and the data area are distinguished by R.
-It is assumed that the sub-code SC provided in DAT40 is used. Since the subcode SC can be recorded and reproduced for each track and the signal processing of the R-DAT 40 is performed for each frame, it is convenient to handle the data for each frame in this embodiment. Therefore, the previous N
The number of samples also needs to be an integral multiple of the number of data in one frame.

The writing / reading control unit 10 controls recording / reproduction, external input / output data clock setting, R-DAT 40 mechanism, and subcode input / output control.

Next, FIG. 9 shows a recording sequence.

In FIG. 9, a shows the write timing of the external input data to the memories 6A and 6B, and b shows the write timing of the read data from the memories 6A and 6B to the R-DAT 40. In a, a ₁ is the memory switching clock CK ₁ and a ₂ is the writing of the external input data Di to the memories 6A and 6B, and a ₃ is the external input data Di.
The memory WR address WRAD, a ₄ indicates clearing of the WR address WRAD. In b, b ₁ is a read from the memories 6A and 6B, b ₂ is a memory RD address RDAD of recording data to the R-DAT 40, b ₃ is a clear RD address RDAD, and b ₄ is an RD address.
RDAD count permission or prohibition, b ₅ indicates input of recording data to the R-DAT 40, and b ₆ indicates operation of the R-DAT 40. Note that P
rM is the pre-margin recording, D is the actual data recording (N
Sample), RoM represents the post margin record.

WR address WRAD to memory 6A, 6B of external input data Di
Is cleared each time the memory switching clock CK ₁ is inverted, and the WR address WRAD counts up to (N-1) until the next inversion, and N samples of data are not interrupted in the memories 6A and 6B. Written alternately.

The R-DAT 40 is activated each time the memory switching clock CK ₁ is inverted. First, after recording the pre-margin for a predetermined number of frames, the memory RD address RDAD is cleared, counting is permitted, and N samples of data are read from the memories 6A and 6B and recorded in the R-DAT 40. After that, the count is prohibited and the post margin is recorded for a predetermined number of frames, and then the R-DAT 40 is stopped.

Next, FIG. 10 shows a sequence during reproduction.

In FIG. 10, c is the memory 6A, 6B for the external output data Do.
, D represents the timing of writing the reproduction data of the R-DAT 40 into the memories 6A and 6B. In c, c ₁ is the memory switching clock CK ₁ , c ₂ is the reading of external output data Do from the memories 6A and 6B, and c ₃ is the external output data.
Memory RD address RDAD, c ₄ of Do indicates clearing of RD address RDAD. Further, in d, d ₁ is writing to memories 6A and 6B, d ₂ is memory WR address WRAD of reproduction data from R-DAT 40, d ₃ is clearing WR address WRAD, and d ₄ is counting enable of WR address WRAD. Or prohibition, d ₅ indicates output of reproduction data from the R-DAT 40, and d ₆ indicates operation of the R-DAT 40.

RD address RDAD from memory 6A, 6B for external output data Do
Is cleared each time the memory switching clock CK ₁ is inverted, and the RD address RDAD counts up to (N-1) until the next inversion, and N samples of data are not interrupted from the memories 6A and 6B. It is read out alternately.

The R-DAT 40 is activated each time the memory switching clock CK ₁ is inverted. First, the pre-margin is reproduced to stabilize tracking. When the start of the data area is detected, the memory WR address WRAD is cleared, the count is enabled, and the reproduction data of the R-DAT40 is N samples, the memory 6
Write to A, 6B. After that, the count is prohibited, the post margin is reproduced, and when the start of the next pre-margin is detected, the R-DAT 40 stops.

Next, setting and identification of these margin area and data area will be described.

The recording / reproducing device 4 needs to be able to simultaneously record and reproduce not only actual data but also an identification signal for identifying data and the like. The R-DAT 40 used in this embodiment is suitable for realizing the present invention because it can record and reproduce additional information called subcode in addition to normal data.

Table 1 shows the contents of the normal data part and subcode part in the margin area and the data area.

Each area has a size of an integer number of frames, and since a predetermined number of frames are recorded while counting the number of frames by the microcomputer at the time of recording, the border between the margin area and the data area may not come in the middle of the frame. Absent. The number of frames in the data area is large enough to accommodate N samples of data. The number of frames in the pre-margin area needs to be equal to or longer than the time required for the tracking of the rotary head 402 to be stable after the R-DAT 40 is activated during reproduction. The post margin area is provided because if the R-DAT 40 is stopped immediately after the data area, the last recorded data may be destroyed. Rotary head 40
The R-DAT 40 is stopped after recording the post-margin area until the 2 is located sufficiently far from the data area on the tape 404.

Next, FIG. 11 shows a state of data recording on the tape 404.

When R-DAT40 is used, the 11th pattern is typically recorded on the tape 404.
Recorded as shown. That is, 405 is a pre-margin area, 406 is an actual data area, 407 is a post-margin area, and X is the running direction of the tape 404.

Next, FIG. 12 shows a control sequence during recording on the R-DAT 40 side.

During recording, each time the memory switching clock CK ₁ is inverted, the write / read controller 10 controls the R-DAT 40 and R-D 40
Control of the AT input / output data counter control unit 802 is started.

That is, in step (1), the memory switching clock CK ₁
Is reversed, the process moves to step (2) to activate the R-DAT 40, and the pre-margin area is recorded in step (3).

Next, in step (4), it is determined whether or not the premargin has recorded a predetermined number of frames, and if the predetermined number of frames has not been recorded (No), the process returns to step (3). If the recording of the proper number of frames is performed in step (4) (Yes), the process proceeds to step (5) and the memory R
After the D address RDAD is cleared and the address count is permitted, the process proceeds to step (6) and the data read from the memories 6A and 6B is recorded on the tape 404 by the R-DAT 40.

Next, in step (7), it is judged whether or not N sample data is recorded. If N sample data is not recorded (No), the process returns to step (6), and N sample data is recorded. Is recorded (Yes), the process proceeds to step (8) to inhibit the counting of the memory RD address RDAD, and then proceeds to step (9) to record the post margin area.

Next, in step (10), it is determined whether or not the post margin has recorded a predetermined number of frames, and if the predetermined number of frames has not been recorded (No), the process returns to step (9),
If the recording of the proper number of frames is performed in step (10) (Yes), the process proceeds to step (11) and RD
Stop AT40.

By repeating such an operation, the external input data Di is recorded on the tape 404 by the R-DAT 40 every N samples.

Next, FIG. 13 shows a control sequence during reproduction on the R-DAT 40 side.

Even during playback, every time the memory switching clock CK ₁ is inverted,
R / DAT 40 control and R by the write / read controller 10
Control of the DAT input / output data counter control unit 802 is started.

That is, in step (1), the memory switching clock CK ₁
When is reversed, the process moves to step (2) to activate the R-DAT 40, and the pre-margin area is reproduced in step (3).

Next, in step (4), it is judged whether or not the beginning of the data area is detected, and if it is not detected (N
o), return to step (3). If it is detected in step (4) (Yes), the process shifts to step (5) to clear the memory WR address WRAD and the address count is permitted. Then, the process shifts to step (6) and the memory 6A, 6B
Write the playback data to.

Next, in step (7), it is determined whether or not N samples of data have been written to the memories 6A and 6B. If N samples of data have not been written (No), the process returns to step (6), and N If sample data is being written (Yes), move to step (8) and set memory WR address W
After the RAD count is prohibited, the process moves to step (9) to reproduce the post margin area.

Next, in step (10), it is determined whether or not the beginning of the next pre-margin is detected. If it is not detected (No), the process returns to step (9), and step (10)
When it is detected (Yes), the process proceeds to step (11) to stop the R-MAT40.

By repeating such an operation, the recorded data is reproduced from the tape 404 on the R-DAT 40 every N samples and output on an arbitrary time axis.

Next, FIG. 14 shows an application example of the digital data recorder of the present invention.

This embodiment shows a configuration example of a 4-channel data recorder capable of time-axis conversion of recording and reproducing data.
Denoted at 34 are analog signal input terminals for each channel.

During recording, the signals input from these input terminals 31-34 are the low-pass filters (LPF) 41-44, sample and hold circuits (S / H) 51-54, analog / digital converter (A /
D) Converted to digital data via 61-64. The digital data of each channel is sequentially selected by the input changeover switch circuit 71, and the first data is selected via the switch 73.
It is input to and recorded in the digital data recorder DDR as the recording / reproducing time axis converting means shown in the figure.

Digital data reproduced from the digital data recorder DDR is output through the switch 73 to an output changeover switch circuit.
Input to 72, select the data of each channel sequentially,
Supply to the digital-analog converter (D / A) 65-68. The outputs of the D / A 65 to 68 are output from the analog signal output terminals 35 to 38 via the S / Hs 55 to 58 and the LPFs 45 to 48.

Thus, by using the digital data recorder DDR having the time axis conversion function, the input data having an arbitrary time axis can be changed to the same or an arbitrary time axis. For example, in the analog data recorder, the tape speed can be changed. Thus, the time axis conversion of input / output data for recording and reproduction can be performed by a digital data recorder so as to switch.

〔The invention's effect〕

As described above, according to the present invention, the time axis conversion of input / output data can be performed by using the rotary head type recording / reproducing apparatus in which the recording / reproducing speed is fixed or can be changed only in an extremely narrow range. Therefore, it is possible to realize a highly reliable digital data recorder having a time axis conversion function equivalent to that of a conventional FM or DR analog data recorder.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital data recorder of the present invention, FIG. 2 is a diagram showing an operation sequence during recording of the digital data recorder shown in FIG. 1, and FIG. 3 is shown in FIG. FIG. 4 is a diagram showing an operation sequence during reproduction of the digital data recorder, FIG. 4 is a block diagram showing a concrete embodiment of the digital data recorder of the present invention, and FIG. 5 is a recording / reproducing memory access shown in FIG. FIG. 6 is a diagram showing the operation of the control unit during recording, FIG. 6 is a diagram showing the operation of the recording / reproducing data flow control unit at the time of recording of the digital data recorder shown in FIG. 4, and FIG. 7 is shown in FIG. And FIG. 9 is a diagram showing the operation of the recording / reproducing memory access control unit at the time of reproduction, and FIG. 8 is a diagram showing the operation of the recording / reproducing data flow control unit at the time of reproduction of the digital data recorder shown in FIG. Is FIG. 10 is a diagram showing a recording operation of the digital data recorder shown in FIG. 1, FIG. 10 is a diagram showing a reproducing operation of the digital data recorder shown in FIG. 1, and FIG. 11 is a diagram showing recording of data on a tape. Fig. 12 and Fig. 12 are R of the digital data recorder shown in Fig. 1.
FIG. 13 is a flow chart showing the recording operation on the −DAT side, and FIG. 13 shows R of the digital data recorder shown in FIG.
FIG. 14 is a block diagram showing an application example of the digital data recorder of the present invention. 4 ... Recording / reproducing device (recording / reproducing means) 6A, 6B ... Memory (storage means) 10 ... Writing / reading control section (writing / reading control means)

Claims (1)

[Claims] 1. Storage means for temporarily storing a digital signal up to a predetermined storage capacity, data recorded from the storage means, or output of its own reproduction data to the storage means. Recording / reproducing means of magnetic tape recording / reproducing system using a rotary head, and at the time of input data recording, input data is sequentially written into the storing means at the data speed, and the data is recorded / reproducing from the storing means. The recording / reproducing means is intermittently recorded by reading at a speed corresponding to the recording speed unique to the recording / reproducing means, and at the time of reproducing the output data, the recording / reproducing means is reproduced at the reproduction speed unique to the recording / reproducing means.
The data reproduced from the reproducing means is sequentially written into the storage means, and the data is read out from the storage means as output data of the device at an arbitrary speed not exceeding the writing speed, and further, the output is temporally. In order to make the data continuous, when recording the data read from the storage means in the recording / reproducing means at the time of recording the input data, the first margin area is recorded prior to the recording of the data, and then the first margin area is recorded. A digital data recorder comprising: write / read control means for recording data and then for recording a second margin area.