JPH0671075B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a Schottky barrier diode circuit in an integrated circuit.

[Conventional technology]

Recently, with the development of applications such as IC cards, various methods of supplying IC operating power without directly connecting an external DC power supply to an LSI chip have been studied.

For example, there is a method of rectifying AC power with a built-in diode bridge in a silicon gate MOS type LSI of 5V system, which is advantageous for high integration and multifunction.

In this case, a low forward rise voltage and an excellent reverse characteristic are required for the diode characteristic with good rectification efficiency.

Therefore, the Schottky barrier diode (hereinafter referred to as SBD) has attracted attention, and a manufacturing technique for adding an SBD circuit to a silicon gate MOS type LSI has become necessary.

FIGS. 2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.

As shown in FIG. 2 (a), phosphorus ions are implanted into the surface of the p-type semiconductor substrate 1 and heat-treated in nitrogen gas at a high temperature of 1200 ° C. to form an n-well 2, and a contact formation region is formed by a well-known LOCOS technique. And the SBD formation area have a thickness of about 1
A field oxide film 4 of μm is formed, and a thickness of about 20 nm is formed on the surface of the n-well 2 surrounded by the field oxide film 4.
To form the first oxide film 3.

Next, arsenic ions were accelerated with an acceleration voltage of 70 keV and a dose of 1.0 × 10 ¹⁶
/ Cm ² to form an n ⁺ diffusion layer 5 to be an n-well power supply, and boron ions are implanted into the SBD formation region at an acceleration voltage of 50 ke
V, performed in a dose of 1.0 × 10 ¹³ / cm, a low impurity concentration p ^-
The diffusion layer 6 and the p ⁺ diffusion layer 7 having a high impurity concentration are formed.

Next, a boron phosphorus silicate silicate glass (hereinafter referred to as BPSG) layer 8 which is a phosphorus-containing glass having a film thickness of about 1.2 μm is deposited on the entire surface by a CVD method, and then a step of the BPSG film 8 is subjected to a steam treatment at about 900 ° C. The surface of the part is flattened.

As shown in FIG. 2B, in order to connect the n ⁺ diffusion layer 5 and the like, holes are formed in the contact portion forming region of the BPSG film 8 by anisotropic etching to form contact opening portions 9 '. .

Next, the polycrystalline silicon layer 13 is thinly grown on the entire surface.

As shown in FIG. 2 (C), after removing the polycrystalline silicon layer 13 on the SBD formation region, isotropic etching is performed using a hydrofluoric acid-based solution, so that the bottom portion of the p ^{+ -type} diffusion layer 7 is approximately the same. A plate-shaped SBD hole 15 is formed so as to expose half.

As shown in FIG. 2 (d), aluminum is vapor-deposited on the entire surface of the semiconductor chip to form metal wiring layers 14 and 14 ', and then aluminum-silicon alloy treatment is performed in hydrogen gas to form the metal wiring layer 14 A Schottky barrier junction 19 is formed between the n-well 2 and the n-well 2.

FIG. 3 is a plan view corresponding to FIG. 2 (d).

FIG. 2D corresponds to a sectional view taken along the line AA ′ of the semiconductor chip in FIG. The metal wiring layer 14 is formed from the groove 18 to the BPSG film 8
Has a constricted part 17 which is deposited along the inclined part at the end of the opening part and whose thickness is partially thinned on the corner part 16 thereof.

The forward characteristics of the SBD are determined by the Schottky barrier junction between the metal wiring layer 14 and the n-well 2, and its reverse breakdown voltage is p ⁺
The p-type diffusion layer 6 is not necessary in the low breakdown voltage SBD, which is determined by the junction between the p-type diffusion layer 7, the p-type diffusion layer 6 and the n-well 2.

Here, the reason why anisotropic dry etching is not used for forming the SBD hole 15 is that if anisotropic etching is performed, then heat treatment for smoothing the corners of the periphery of the hole is performed. It is necessary, there is a possibility that the corners hang inward in an eaves-like shape, which is a cause of step breakage of the metal wiring layer, and if high-temperature heat treatment or oxidation treatment after dry etching is not performed, N of SBD formation area
This is because the surface of the well 2 remains damaged and the reverse leakage current of the SBD increases.

[Problems to be solved by the invention]

In the conventional method for manufacturing a semiconductor device described above, when forming the SBD apertures in the phosphorus-containing glass layer, the corners 16 are formed in the peripheral edge using only isotropic etching. There has been a problem that a narrowed portion 17 is widely formed in the metal wiring layer to be formed, and a step break is likely to occur.

Also, for side etching by isotropic etching
Since the p ^{+ -type} diffusion layer is large, there is a problem that it is difficult to miniaturize.

An object of the present invention is to provide a method for manufacturing a semiconductor device having a highly reliable metal wiring layer that does not cause step disconnection and having a Schottky barrier diode that can be miniaturized.

[Means for solving problems]

According to the method of manufacturing a semiconductor device of the present invention, (A) a well of opposite conductivity type is formed on one main surface of a semiconductor substrate of one conductivity type, and an element formation region and a contact portion are selectively defined on the surface of the well. Forming a field oxide film and forming a first insulating film on the surface of the well surrounded by the field oxide film; (B) phosphorus-containing glass on the entire surface of the field oxide film and the first insulating film A step of depositing a layer, (C) isotropically etching the phosphorus-containing glass layer on each of the element forming region and the contact portion until the thickness thereof becomes about half, and then, the remaining phosphorus-containing glass layer is formed. Anisotropically removing to form an opening having a cup-shaped cross section; (D) removing the first insulating film exposed on each of the element forming region and the contact portion by isotropic etching. Process (E) a step of oxidizing the surface of the well of the opposite conductivity type exposed on each of the element formation region and the contact portion by dry oxygen gas to form a second insulating film; A step of treating the phosphorus-containing glass layer in nitrogen gas and reflowing it to smooth the periphery of the opening, (G) by selectively isotropic etching the second insulating film on the contact portion. After the removal, a step of forming a thin polycrystalline silicon layer on the entire surface, (H) a step of selectively removing the polycrystalline silicon layer on the element forming region by anisotropic etching, (I) the element forming region A step of removing the second insulating film exposed to the surface by isotropic etching; (J) After depositing aluminum on the entire surface, a metal wiring layer is formed by photolithography technique and anisotropic etching. Step, and is configured to form at the same time includes a Schottky barrier diode and a semiconductor integrated circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1F are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

The method of manufacturing the semiconductor chip shown in FIG. 1 (a) is the same as the method of manufacturing the conventional semiconductor chip shown in FIG. 2 (a).

As shown in FIG. 1B, the contact formation region and the SBD
Corresponding to the formation region, the BPSG film 8 is isotropically etched to about half the film thickness to form an arc-shaped cross section.

Next, the remaining BPSG film 8 is anisotropically dry-etched with, for example, a CF ₄ —H ₂ -based gas, and the remaining thin oxide film 3 is isotropically etched with a hydrofluoric acid-based solution. The SBD opening 9 having the cup-shaped portion 10 and the contact opening 9'are formed at the same time.

As shown in FIG. 1 (c), dry oxidation is performed in a high temperature furnace at, for example, about 900 ° C. to form a second oxide film 12 in the SBD opening 9 and contact opening 9 '.

Subsequently, heat treatment is performed at the same temperature in nitrogen gas to smooth the peripheral portions of the openings 9 and 9 '.

Next, as shown in FIG. 1 (d), the second oxide film 12 on the SDB opening 9 is left and the second oxide film 12 on the other contact opening 9'is isotropic. After removal by etching 5), a polycrystalline silicon layer 13 having a film thickness of about 50 nm is grown on the entire surface by the low pressure CVD method.

Next, as shown in FIG. 1 (e), the polycrystalline silicon layer 13 on the surface of the second oxide film 12 of the SBD opening 9 and the surrounding BPSG film 8 is made of a CF ₄ —O ₂ system. It is removed by anisotropic etching with a gas.

Next, as shown in FIG. 1 (f), the second part of the SBD opening 9
After removing the oxide film 12 by isotropic etching, aluminum having a film thickness of about 1.0 μm is deposited on the entire surface by sputtering.

Next, a predetermined resist is patterned by a well-known photolithography technique, and aluminum is anisotropically dry-etched with a gas of CCl ₄ --CF ₄ --BCl ₃ system to form metal wirings 14 and 14 '.

Next, alloy treatment is performed in an atmosphere of N ₂ —H ₂ at a temperature of about 450 ° C. to form a Schottky barrier junction 19 between the aluminum group and the n well.

In this embodiment, the reason why anisotropic dry etching can be used to form the SBD hole 9 is that a cup-shaped portion is formed on the periphery of the SBD hole 9 and then BPSG is formed.
This is because the gentle slope 11 is formed by the heat treatment of the film 8 so that no constriction is generated in the metal wiring layer 14 and there is no risk of disconnection.

Even if the dry etching is excessive and damages the surface of the n-well 2, the damaged layer enters the second oxide film 12 by the post-process of dry oxidation at about 900 ° C. and heat treatment in nitrogen gas. That portion is removed by etching.

〔The invention's effect〕

INDUSTRIAL APPLICABILITY As described above, the present invention provides a phosphorus-containing glass film with SBD.
By using an isotropic method up to about half and an anisotropic two-step etching process for the rest, the cross-section of the periphery of the opening forms a cup-shaped portion. Since the upper half of the step is made very gentle by the subsequent heat treatment, the metal wiring layer does not have a step disconnection and is highly reliable, and it can be miniaturized as compared with only the isotropic etching.
There is an effect that a semiconductor device having an SBD circuit can be manufactured.

[Brief description of drawings]

1 (a) to 1 (f) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are conventional semiconductor device manufacturing methods. Sectional views of the semiconductor chip shown in the order of steps for explaining one example,
FIG. 3 is a plan view corresponding to FIG. 2 (d). 1 ... Semiconductor substrate, 2 ... n well, 3 ... first oxide film, 4 ... field oxide film, 5 ... n ^{+ type} diffusion layer, 6 ...
… P ^{− type} diffusion layer, 7 …… p ^{+ type} diffusion layer, 8 …… BPSG film, 9 ・ ・ ・
… SBD opening, 9 '... Contact opening, 10 ... Cup, 11 ... Inclined, 12 ... Second oxide film, 13 ... Polycrystalline silicon layer, 14, 14' ...... Metal wiring layer.

Claims (1)

[Claims] (A) A well of opposite conductivity type is formed on one main surface of a semiconductor substrate of one conductivity type, and a field oxide film for selectively partitioning an element forming region and a contact portion is formed on the surface of the well. And forming a first insulating film on the surface of the well surrounded by the field oxide film, (B) depositing a phosphorus-containing glass layer on the entire surfaces of the field oxide film and the first insulating film (C) the phosphorus-containing glass layer on each of the element forming region and the contact portion is isotropically etched until its thickness is reduced to about half, and then the remaining phosphorus-containing glass layer is removed by anisotropic etching. And (D) removing the first insulating film exposed on each of the element forming region and the contact portion by isotropic etching, (E) ) Device formation A step of oxidizing the surface of the well of the opposite conductivity type exposed on each of the region and the contact portion with a dry oxygen gas to form a second insulating film; A step of smoothing the periphery of the opening by treating the inside with reflow, and (G) removing the second insulating film on the contact portion selectively by isotropic etching, and then arranging a large amount on the entire surface. Forming a thin crystalline silicon layer; (H) selectively removing the polycrystalline silicon layer on the element formation region by anisotropic etching; (I) the second part exposed in the element formation region A step of removing the insulating film by isotropic etching, and a step of (J) depositing aluminum on the entire surface and then forming a metal wiring layer by photolithography and anisotropic etching. Method of manufacturing a semiconductor device and forming step of forming a key barrier diode and the semiconductor integrated circuit at the same time, the includes a Schottky barrier diode and a semiconductor integrated circuit at the same time.