JPH0669044B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION [Overview] A base extraction electrode of a bipolar transistor is formed by selective growth of metal or metal silicide.

[Industrial application field]

The present invention is a method of manufacturing a semiconductor device, and more specifically,
The present invention relates to a method for manufacturing a bipolar transistor having excellent high frequency characteristics.

[Conventional technology]

FIG. 2 is a sectional view of a main part of a conventionally proposed bipolar transistor. In the figure, 1 is the collector region N
-Shaped silicon substrate, 2 is its main surface, 3 is a P-type base region,
Reference numeral 4 is an N-type emitter region, 5 is a base extraction electrode made of a polycrystalline silicon layer containing P-type impurities, 6 and 7 are SiO ₂ films, 8 is a base electrode, and 9 is an emitter electrode. In this bipolar transistor, the base electrode 8 is connected by the base lead electrode 5 made of polycrystalline silicon.
The area on the main surface 2 of the base region 3 can be reduced as compared with the case where the base region 3 is directly connected to the base region 3 without the base lead electrode 5 interposed therebetween.

However, also in this bipolar transistor, the base extraction electrode 5 made of a polycrystalline silicon layer is formed by etching the polycrystalline silicon layer formed on the entire surface of the base region 3, the emitter region 4 and the SiO ₂ film 6. Since the base extraction electrode 5 occupies a relatively large area on the base region 3, the area of the base extraction electrode 5 is relatively large. Further, the area occupied by the SiO ₂ film 7 on the regions 3 and 4 must be relatively large for the same reason. Therefore, a method for manufacturing a bipolar transistor has been proposed in which self-fabrication is promoted by utilizing the good workability of polycrystalline silicon to solve these problems (Japanese Patent Publication Nos. 55-26630 and 57-32511).
(See the official gazette).

[Problems to be solved by the invention]

The reason why the base extraction electrode is made of polycrystalline silicon in the bipolar transistor is that polycrystalline silicon is excellent in workability, so that fine patterning is possible, and that it is excellent in compatibility with the self-aligning process. Because it was. However, although it is possible to give conductivity to polycrystalline silicon by introducing impurities at a high concentration, the conductivity is still lower than that of metal or the like. There is a problem that the base resistance becomes somewhat large. Further, it is necessary to introduce a high concentration of impurities in order to make the polycrystalline silicon conductive, so that the impurities diffuse from the conductive polycrystalline silicon to the semiconductor substrate in contact with it during the subsequent heat treatment. There is a problem that impurities in the region are always high in concentration, which is not preferable in terms of device characteristics.

[Means for solving problems]

In order to explain the above problem, the base extraction electrode is formed by the selective growth method of metal or metal silicide.

An insulating layer is formed on the first conductivity type semiconductor substrate, an opening for measuring a base contact region surrounding an emitter region (island shape) to be formed in the insulating layer is formed, and the insulating layer is formed on the insulating layer. A predetermined pattern that extends outward from the outer edge of the opening (forms a pattern for the base extraction electrode together with the opening)
Forming a layer having This last layer is a layer (hereinafter, referred to as a "seed layer") that becomes a seed for selective growth of metal or metal silicide to be performed in a later step, and may be a seed (nucleus) for growth in terms of material. Any material may be used, and at least the same material as that of the substrate may be a seed for growth. Further, a second conductivity type dopant is introduced into the base contact region from the main surface side of the substrate based on the pattern of the opening.

In this state, if a metal or metal silicide is grown under a specific growth condition, the metal or metal silicide is selectively grown on the substrate (base contact region) below the opening and on the seed layer, and the insulating layer is formed. It is possible to prevent growth on the exposed parts of the layer. As a result of this selective growth, the metal or metal silicide growing on the base contact region and the metal or metal silicide growing on the seed layer are integrated, and the metal or metal silicide that is a good conductor forms the base extraction electrode. It

Then, an insulating layer is formed on the exposed surface of the base lead electrode. This insulating layer can be preferably formed by anodic oxidation of the base extraction electrode, but it may be formed from the beginning or additionally by depositing and patterning the insulating layer. Then, using the insulating layer and the base extraction electrode as a mask, the main surface is formed in a region surrounded by the insulating layer, that is, a region in the semiconductor substrate below a region corresponding to the island-shaped region inside the opening. A second conductivity type dopant is introduced from the side to form an active base region connected to the base contact region, and a first conductivity type dopant is introduced into the active base region to form an emitter region.

Other steps may be the same as the conventional bipolar transistor manufacturing method, and may be modified in various ways.

Thus, according to the present invention, specifically, on the first conductivity type semiconductor substrate, the first insulating film and the layer (hereinafter, referred to as “lamination”) that serves as a seed of metal or metal silicide growth, which will be described later, are formed. A step of forming an island-shaped second insulating film in at least a region to be an emitter, a step of forming a third insulating film in a region excluding the peripheral region of the second insulating film,
Seed layer and the first insulating film and the third insulating film as a mask
Etching the insulating film to open the base contact window, forming a second conductivity type base contact diffusion region in the opening, and forming only the first insulating film in the island region on the base contact window. A step of increasing a first insulating film and a seed layer in a predetermined pattern in the circumscribing region, and a metal or metal silicide is selectively grown on the base contact region exposed under the opening and on the seed layer to form a base extraction electrode. Forming a fourth insulating film on the surface of the base electrode, and in the semiconductor substrate below the region surrounded by the base lead electrode and the fourth insulating film, from the main surface side thereof, A second connecting with a base contact region of two conductivity type
A conductive type active base region and a step of forming a first conductive type emitter region in the active base region, and a region contacting the active base region of the first conductive type semiconductor substrate on the outside is a collector region. A method for manufacturing a semiconductor device is provided.

[Action]

In this manufacturing method, since the base extraction electrode is made of metal or metal silicide, its conductivity is high and the base resistance can be reduced.

In addition, the base contact region is formed in self-alignment with the pattern of the opening (base contact window) formed in the insulating layer on the semiconductor substrate first, and the base contact window is self-aligned to the outside of the window. Since the base extraction electrode is formed on the extending seed layer, there is no need to unnecessarily increase the area of the base contact region for making the base contact.

Further, since the emitter region and the emitter electrode can be formed in self-alignment with the inner edge of the base extraction electrode formed by the selective growth method, the area between the base contact region and the emitter region or the base extraction electrode and the emitter region can be formed. There is no need to unnecessarily increase the area for insulation separation between the electrodes.

Thus, according to the method of the present invention, it is possible to form the base extraction electrode and the emitter electrode by using the metal or the metal silicide with the required minimum area of the base region and the emitter region. Therefore, it is possible to obtain a transistor having a very high frequency characteristic with reduced safety capacitance and parasitic resistance.

〔Example〕

 An embodiment of the present invention will be described in detail with reference to FIG.

Referring to FIG. 1A, a single crystal silicon semiconductor substrate 11 having a main surface 12, an n ^{+ type} buried layer 13, an n ^{− type} epitaxially grown single crystal silicon layer 14, an isolation selective oxide film 15, an n ^{+ type} collector contact. Each region 16 is formed by a conventional bipolar transistor manufacturing method. In addition, 11, 13, 14 and 16
An oxide film 17 having a thickness of about 0.1 μm is also formed on the surface of the silicon semiconductor body not containing the selective oxide film 15 including the oxide.
The oxide film 17 may be formed by oxidizing the surface of the silicon substrate or by a CVD method.

After depositing a polycrystalline silicon layer 18 having a thickness of 0.1 to 0.3 μm on the oxide films 15 and 17 by a CVD method and further depositing a silicon nitride layer 19 having a thickness of about 0.3 to 0.5 μm thereon, patterning the silicon nitride layer 19 Then, leaving the emitter forming portion (20 in FIG. 1F),
The formation part of the base extraction electrode that surrounds it (2 in FIG. 1F)
1) is removed. The silicon nitride layer (22 in FIG. 1F) around the base lead electrode forming portion 21 is left. Emitter formation part
The size of 20 is, for example, 1.0 μm square.

Next, for example, the PSG layer 23 is formed on the entire surface of the silicon nitride layer 19 and the polycrystalline silicon layer 18 by plasma CVD or low pressure CVD.
Is deposited to a thickness of about 0.3 to 0.5 μm, the coverage in the step portion of the underlying pattern is poor.
Depressions or constrictions 24 in layer 23 along the edges of the pattern
You can

Referring to FIG. 1B, a gradual wet etch of layer 23 using, for example, buffer hydrofluoric acid results in layer 23
When the etching progresses from the surface of the layer 23 and the thickness of the layer 23 gradually decreases, the etching is performed on the other portion 23 ′ of the recess 24, that is, the outer edge portion of the emitter forming portion 20 and the outer edge portion of the base extraction electrode forming portion 21. By proceeding further deeper, the surfaces of the silicon nitride layer 19 and the polycrystalline silicon layer 18 are exposed only there. That is, the opening 24 is formed. The opening width of the opening 24 is determined by the thickness of the silicon nitride layer 19, the formation conditions of the layer 23, the etching conditions of the layer 23, the etching thickness of the layer 23, etc., but when the etching of the layer 23 is finally stopped. By appropriately selecting, the opening 24 having a desired opening width can be formed within a certain range. For example, in this example, the opening width is 0.2 to 0.3 μm.

Referring to FIG. 1C, when the polycrystalline silicon layer 18 is etched using the remaining layer 23 'as a mask, only the portion 25 under the opening 24 is selectively etched. The layer 23 'is then removed, with the result that the parts of the oxide films 15, 17 exposed by the previous etching of the polycrystalline silicon layer 18 are also etched. This is because the layer 23 'is PSG and the oxide films 15 and 17 are SiO ₂ . Then, when boron ions (B ⁺ ) are implanted into the entire surface, the silicon nitride layer 19 and the polycrystalline silicon layer 18 act as masks in the n ⁻ -type epitaxial layer 14 to form the emitter formation portion.
20 is a base contact area below the opening 25 along the outer edge
Boron ions are selectively implanted only into 26, and at the same time, the boron nitride ions are selectively implanted into the base extraction electrode forming portion 21 by the silicon nitride layer 19 acting as a mask in the polycrystalline silicon layer 18. . The driving conditions are, for example, 30
It is about 40 keV and 1 × 10 ¹⁴ cm ^-2 .

Referring to FIG. 1D, after removing the silicon nitride layer 19 by etching, a polycrystalline silicon layer is formed using potassium hydroxide.
When 18 is etched, since the etching rate of the portion where boron ions are selectively implanted in the above step is reduced, the polycrystalline silicon layer 18 is formed on the base extraction electrode forming portion (2
1) Only remain selectively.

The structure shown in FIG. 1D thus obtained has an insulating layer (oxide film) 17 on the main surface 12 of the n ⁻ -type epitaxial silicon layer 14 on which an emitter region and a collector region are to be formed, and the insulating layer 17 is an island. The emitter forming portion (20) having an opening 25 surrounding the emitter forming portion (20) and surrounding the opening 25, and a predetermined pattern extending outward from the outer edge of the opening 25 on the insulating layer 17 (a base extraction electrode should be formed). Pattern) layer (polycrystalline silicon layer) 18. And the monocrystalline silicon and layers of region 26
Eighteen polycrystalline silicon is a material that becomes a seed for selective growth such as tungsten described later. No tungsten or the like grows on the SiO ₂ layers 15 and 17. The method of the present invention is characterized in that the base extraction electrode is formed by selective growth of a metal or a silicide by using such a structure as a starting point. Therefore, the series of steps described above with reference to FIGS. 1A to 1D is merely an example of steps for obtaining the structure shown in FIG. 1D. However,
In this series of steps, a base contact region or a base contact window is obtained on the submicron order adjacent to the pattern of the emitter formation portion, and the pattern of the silicon nitride layer 19 in FIG. It has the advantage that a self-aligned process results in the structure shown in FIG. 1D.

Next, referring to FIG. 1E, metal or metal silicide is selectively grown on the epitaxially grown single crystal silicon 26 (14) exposed under the opening 25 and on the polycrystalline silicon layer 18. For example, it is possible to selectively grow tungsten from a mixed gas of tungsten fluoride (WF ₆ ) and argon or hydrogen by CVD at a low temperature of 250 to 500 ° C. and a low pressure of 0.1 to 5 Torr [e.g. Broadbent, C. L. Miller, "Selective Low Pressure CVD of Tungsten," Journal of Electrochemical Society, Solid State Chemistry and Technology 1984 6
Mon, pp. 1427-1433]. Also, for example, from a mixed gas of trichlorotitanium (TiCl ₄ ) and trichlorosilane (SiHCl ₃ ) in hydrogen (H ₂ ) as a carrier gas, titanium silicide (TiSi ₄ ) at a pressure of 100 Torr or less at a temperature of 600 to 900 ° C.
₂ ) can be selectively grown [eg Japanese Patent Application No. 6
0-23480]].

Thus, for example, when tungsten is selectively grown on the base contact region 26 and the polycrystalline silicon layer 18, the tungsten grown on these two regions is finally integrated to form the base extraction electrode 27. At this time, the thickness of the tungsten layer or the base extraction electrode 27 is, for example, 0.3 to
It is about 0.5 μm.

FIG. 1F is a plan view of FIG. 1E. In the figure, the shaded area 27
Is the base extraction electrode, the broken line 28 is the outer edge of the base contact region 26, the broken line 29 is the outer edge of the n ⁻ -type epitaxial layer 14, and the broken line 30.
Is the outer edge of the n ^{+ -type} collector contact region 16, and the chain line 31 is the outer edge of the n ^{+ -type} buried layer 13.

Referring to FIG. 1G, the surface 32 of the base extraction electrode 27 made of metal or metal silicide is anodized to be insulated. Then, using the base extraction electrode 27 as a mask, boron ions (B ⁺ ) are selectively implanted into the active base region 33 under the conditions of 30 to 40 keV and 5 × 10 ¹³ cm ^-2 . At this time, although not shown, the collector contact region is masked with a resist in order to avoid implantation of ions.

Referring to FIG. 1H, the emitter diffusion may be performed immediately, but inside the inner edge of the insulating layer 32 of the desired width to avoid the outer edge of the emitter region from penetrating into the heavily doped base contact region. An insulating film 34 is provided. This insulating film 34
Can be formed, for example, by depositing SiO ₂ on the entire surface by CVD and then anisotropically etching it in a direction perpendicular to the main surface 12 by, for example, ion milling. As compared to above the planar insulating layer 32 and above the active base region 33, the portion attached to the vertical wall of the step has a greater thickness in the milling direction (perpendicular to the major surface 12), Even if the former part is removed by etching, SiO ₂ remains in the latter part. At this time, by controlling the amount of milling, the lateral thickness of the insulating film 34 can be adjusted. Also, the same operation can be repeated. After that, for example, a polycrystalline silicon layer doped with arsenic to about 10 ²⁰ cm ^-3
Arsenic diffuses from the doped polycrystalline silicon layer 35 through the main surface 12 by forming 35 inside the insulating film 34 on the epitaxial silicon layer 14 and performing heat treatment at 950 to 1000 ° C. for about 30 minutes, for example. And an emitter region with a depth of about 0.15 μm
36 is formed. During this heat treatment, the base regions 26, 3
The boron ions that were implanted in 3 are also activated at the same time. The base contact region 26 and the active base region 33 are integrated, and the active base region 33 has a depth of about 0.3 μm.

Referring to FIG. 1I, the insulating film is then formed by a conventional method.
37, an emitter electrode 38, a base electrode 39, and a collector electrode 40 are formed. As shown in the figure, the base electrode 39 is connected to the base extraction electrode 27.

As described above, in the series of steps after FIG. 1D, the outer edge of the base contact region 26 based on the outer edge of the opening 25, and hence the outer edge of the entire base region (26 + 33), and the base lead electrode.
The inner edge of 27 is self-aligned, and the inner edge of the base contact region 26 and the outer edge of the emitter region 36 are self-aligned based on the inner edge of the opening 25. Therefore, the area of the base region surrounding the emitter region is defined only by the pattern of the openings 25, so that the area can be easily reduced. Moreover, in combination with the process of FIG. 1A / D described above, the pattern of the opening 25 is accurately formed in the sub-micron order only from the pattern of the emitter forming portion of the silicon nitride layer 19, so that the base region The area can be set to the minimum required size.

Moreover, since the base extraction electrode of the bipolar transistor obtained by this method is made of metal or metal silicide rather than the conventional polycrystalline silicon, its conductivity is high, and therefore the resistance of the base extraction electrode deteriorates the transistor characteristics. The problem has also been resolved.

Further, according to this method, it is not necessary to perform mask alignment in order to form the base extraction electrode made of metal or metal silicide, and the metal or metal silicide etching step for the base extraction electrode is also unnecessary. This is an advantage of the method of the present invention in view of the poor etching controllability of metal or metal silicide.

The embodiments of the present invention have been described above, but the present invention can be modified in various ways. For example, the method of forming the opening provided in the insulating layer on the semiconductor body, the shape, and the dimension are arbitrary. The doping method (ion implantation or thermal diffusion) of the base contact region, the active base region, and the emitter region, the type of dopant, the forming conditions, and the order of forming the active base region and the emitter region are arbitrary. The materials of the insulating film and the growth seed layer during the selective growth may be appropriately selected according to the type of the selectively grown metal or metal silicide and the growth conditions thereof. The insulating layer on the surface of the base extraction electrode is formed by a method other than anodic oxidation, for example,
It can also be formed by the CVD method, etc.

〔The invention's effect〕

According to the present invention, the base lead-out electrode of the bipolar transistor is made of metal or metal silicide, and the base lead-out electrode, the base contact window, and the base contact diffused region are formed in a self-aligned manner. Can be minimized, and the resistance of the base extraction electrode can be reduced. Furthermore, since the emitter electrode and the emitter diffusion region can be formed in a self-aligned manner with respect to the base extraction electrode and the base contact diffusion region, respectively, the area of the base diffusion region and the emitter diffusion region can be reduced in this sense as well. Is. In this way, the parasitic capacitance and the parasitic resistance are significantly reduced, and a bipolar transistor having excellent high frequency characteristics can be obtained.

[Brief description of drawings]

1A to 1I are cross-sectional views of a main part of a bipolar transistor which is a main part of a process in an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a conventional bipolar transistor. 12 …… Main surface, 13 …… n type buried layer, 14 …… n ^{− type} epitaxial layer, 15 …… Selective oxide film, 16 …… n ^{+ type} collector contact region, 17 …… Oxide film, 18 …… Polycrystalline silicon layer, 19 ... Silicon nitride layer, 23 ... PSG layer, 24, 25 ... Opening area, 26 ... Base contact area, 27 ... Tungsten layer, 32 ... Insulating layer, 33 ... Active base Area, 35 ... Polycrystalline silicon layer, 36 ... Emitter area, 38, 39, 40 ... Electrodes.

Claims (1)

[Claims] 1. A step of forming a first insulating film and a layer (hereinafter, referred to as a “stack”) which is a seed of metal or metal silicide growth, which will be described later, on a first conductivity type semiconductor substrate, and at least an emitter. Forming an island-shaped second insulating film in a desired region, forming a third insulating film in a region other than the peripheral region of the second insulating film, the second insulating film and the third insulating film Etching the seed layer and the first insulating film with the film as a mask to open a base contact window; forming a second conductivity type base contact diffusion region in the opening; Leaving only the first insulating film in a region of the base contact window circumscribing the first insulating film and the seed layer in a predetermined pattern, and exposing the base contact region and the seed layer under the opening. Metal or metal A step of selectively growing a side to form a base lead electrode, a step of forming a fourth insulating film on the surface of the base electrode, and a step of forming a base insulating electrode under the region surrounded by the base lead electrode and the fourth insulating film. Forming a second conductivity type active base region connected to the second conductivity type base contact region in the semiconductor substrate from the main surface side thereof, and a first conductivity type emitter region in the active base region; And a region outside the first conductivity type semiconductor substrate that is in contact with the active base region as a collector region.