JPH0666963B2 - Color video signal playback device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reproduces a recording medium in which a luminance signal and a pair of component color signals time-compressed in one horizontal section are simultaneously recorded on separate tracks. The present invention relates to a color video signal reproducing apparatus.

BACKGROUND ART AND PROBLEMS In a recording / reproducing apparatus for color video signals such as integrated video,
There is one in which a color video signal is divided into a luminance signal and a pair of component color signals and simultaneously recorded on different tracks.

In this case, for the luminance signal S _Y as shown in FIG. 1A,
The pair of component color signals shown in FIGS. B and C, for example, the red and blue color difference signals RY and BY, and the color video signal, as shown in FIG. compressed by 0.5 sequentially compressed color difference signals are temporally alternately arranged in each horizontal period S _C 'is formed, the compressed color difference signals S _C'
And the luminance signal S _Y are simultaneously recorded on the adjacent tracks as shown in FIG. 2A.

In such a recording / reproducing apparatus, a luminance signal S _Y and a pair of compressed color difference signals reproduced simultaneously from different tracks during reproduction.
Since it is necessary to align the time axis with S _C ′, for example, as shown in FIG. 3, each of the luminance signal S _Y and the compressed color difference signal S _C ′ has a synchronization signal (in this example, a reference) of the time axis. Sync pulse) P _R1 and P _R2 are inserted. The first synchronizing signal P _R1 inserted in the luminance signal S _{Y is} in the latter half of the period of the horizontal synchronizing pulse P _H , as shown in FIG. And the second sync signal P _R2 of negative polarity is also inserted into the compressed color difference signal S _C ′ on the same time axis as the first sync signal P _R1 .

At the time of reproduction, the time axis of the color difference signal S _{C with} respect to the luminance signal S _Y is aligned on the basis of the pair of synchronization signals P _R1 and P _R2. The current situation is to insert a new time axis adjustment circuit. Therefore, in such a recording / reproducing apparatus, there is a drawback that the circuit scale of the time axis adjusting circuit increases.

Therefore, in the present invention, when the time axes of the two are aligned based on the pair of synchronization signals, the time axes of the both can be accurately aligned with a very simple configuration.

SUMMARY OF THE INVENTION Therefore, according to the present invention, the memory element for the compressed color difference signal provided in the reproduction system is written based on the second synchronization signal P _R2 inserted in the compressed color difference signal S _C ′. , Its reading is the first inserted in the luminance signal S _Y
This is done based on the synchronizing signal P _R1 . Further, specifically, the present invention, as shown in FIGS. 3, 4, and 5, includes a luminance signal S into which a first synchronizing signal P _R1 having a constant time relationship with the horizontal synchronizing signal P _H is inserted.
_Y and the second synchronization signal P _{R2 which} is in a fixed time relationship with the first synchronization signal P _R1 are inserted, and the compression ratio n is set in one horizontal section.
The luminance signal S _Y and the pair of component color signals S _C ′ are recorded from the recording medium in which the pair of component color signals S _C ′ compressed in the time axis (n = 2 in this example) are simultaneously recorded on different tracks. In a reproducing apparatus for reproducing a color video signal which reproduces a pair of component color signals S _R in synchronization with a second synchronizing signal P _R2 inserted in a pair of reproduced component color signals S _C ′.
_M multiplication in synchronization with the write start signal P _W delayed to the start position of _C ′ (the left end position of the compressed color difference signal represented by the symbol (RY) ′ in FIG. 3D) and the second synchronization signal P _R2 Write control signal generating means (27), (25) for generating a write control signal composed of a write clock having a frequency m _H (for example, 720 _H ), and a first control signal inserted in the reproduced luminance signal S _Y. The read start signal P delayed to the start position of the brightness signal S _Y (the left end position of the brightness signal represented by symbol Y in FIG. 3A) in synchronization with the synchronization signal P _{R1 of} 1.
Read control signal generating means for generating a read control signal consisting of _R and a read clock of m / n multiplication frequency (for example, 360 _H ) synchronized with the first synchronization signal P _R1.
(23), (24), and (25), by the write control signal, a pair of component color signal S _{C 'is} written by the read control signal, already written a pair of component color signals are S _C For reading a pair of component color signals S _C ′ whose time axis is extended from the memory means 21 and whose time axis is aligned with the luminance signal S _Y. It is the one. The frequency _H of the first synchronization signal P _R1 is
The frequency of the second sync signal P _R2 is different because there is a mounting error in the position of the head in compatible reproduction of the recording / reproducing apparatus.
It does not necessarily have the same value as _H.

Furthermore, as shown in FIG. 4, the memory means (21)
Has two pairs of CCD memories (21A) to (21D), write control signal generating means (27) and (25) and read control signal generating means
(23), (24) and (25) are two pairs of CCD memories (21A) to (21D).
Of the pair of CCD memories (21A) and (21B) in the writing state, the remaining pair of CCD memories (21C) and (21C)
The pair of CCD memories (21A) are provided with the write control signal and the read control signal so that D) is in the read state.
To (21D) and read control signal generating means (23), (24) and (25) from the pair of CCD memories (21C) and (21D) in the read state to the time axis. This is to obtain a pair of expanded component color signals S _C ′.

Furthermore, as shown in FIG. 8, a variable delay means (40) for supplying a pair of reproduced component color signals and for delaying the pair of component color signals S _C ′ to the memory means (21). , The phase difference between the second synchronization signal P _R2 inserted in the pair of delayed component color signals S _C ′ and the first synchronization signal P _R1 inserted in the reproduced luminance signal S _Y. Phase difference detection means (41) for detecting and supplying the phase difference detection output to the control input of the variable delay means (40)
And a pair of component color signals S _C ′ delayed by the delay amount corresponding to the phase difference detection output by the variable delay means (40) are supplied to the memory means (21). .

Operation The reproducing apparatus of the present invention will be described in detail with reference to the fourth and subsequent figures.

Luminance signal S _Y and compressed color difference signal S _C ′ to be recorded on the tape
Are synchronized signals P _R1 and P _R1 , respectively, as shown in FIGS. 3A and 3B.
_R2 is inserted and each is angle-modulated, for example, FM-modulated. Since the specific configuration of the recording system for providing such a signal form is not directly related to the present invention, its description is omitted.

In FIG. 4, (10) shows an example of a reproducing system (10) which is a main part of the reproducing apparatus according to the present invention.

The FM luminance signal S _Y -FM reproduced from the reproducing head H _Y is supplied to the FM demodulator (12) via the preamplifier (11) to demodulate the luminance signal S _Y , which is supplied to the mixer (13). As will be described later, the time axis is expanded and mixed with the color difference signal S _C whose time axis is aligned with the luminance signal S _Y , and a normal color video signal S _V is obtained from the terminal (14).

On the other hand, the FM compressed color difference signal reproduced from the reproduction head H _C
The S _C ′ -FM is supplied to the FM demodulator (17) via the preamplifier (16) to demodulate the compressed color difference signal S _C ′. The compressed color difference signal S _C ′ is supplied to the time axis expander (20).

The time axis expander (20) is provided with a memory element (21) for expanding the time axis of the compressed color difference signal S _C ′ to the original time axis. In this example, it is composed of two pairs of CCD memories (21A) to (21D). Writing and reading clocks for driving the memory element (21) will be described below.

The luminance signal S _Y is supplied to the sync separation circuit (22), from which the first sync signal P _R1 is separated, and the VCO (23) is controlled based on the first sync signal P _R1 to generate the first sync signal P _R1 . Sync signal P _R1
720H in this example (H is the horizontal frequency)
A clock having a frequency of .tau. Is formed, which is further divided by a half in the counter (24) to form a read clock of 360H, which read clock is supplied to the clock generator (2). The first synchronizing signal P _R1 is further supplied to the clock generator (25) as its reference signal to form a read zero pulse P _R as shown in FIG. 3D.

On the other hand, the demodulated compressed color difference signal S _C ′ is the sync separation circuit (26).
Second synchronization signals P _R2 is supplied is separated synchronized, this is clock is formed having a frequency of 720H synchronized with the second synchronizing signal P _R2 is supplied to the VCO (27), clock which as a write clock Supplied to the generator (25). Then, the second synchronization signal P, which is also synchronously separated,
_Based on this, _R2 is the write zero pulse P shown in FIG. 3D.
_W (in this example, same timing as read zero pulse P _R )
To a clock generator (25) to form

Next, the write and read operations of the compressed color difference signal S _C ′ will be described in the fifth step.
It will be described with reference to the drawings.

CCD memory among 2 pairs of CCD memory (21A) to (21D)
(21A) and (21C) are memories dedicated to writing and reading the red compressed color difference signal (RY) ', and other CCD memories (21B)
And (21D) are memories dedicated to writing and reading for the compressed blue color difference signal (BY) ', and are a pair of CCD memories.
When (21A) and (21B) are in the writing mode, the timing of sending the writing and reading clocks is controlled so that the other pair of CCD memories (21C) and (21D) are in the reading mode. Therefore, the timing charts of the CCD memories (21A) to (21D) are shown in FIGS. 5J to 5M, and the CCD memories (2
A clock generator (25) is provided so as to be supplied to 1A) to (21D).

In the horizontal blanking period, the color difference signals RY and BY
Does not exist, the line-sequential compressed color difference signal (R-
Y) 'and (B-Y)' have some non-signal sections (shown by hatching in FIG. 5C).

Now, the compressed color difference signal S _C ′ is synchronized with the write zero pulse P _W (B in the same figure) by the write clock of 720H, as shown in FIGS.
It is written in 1A) to (21D).

That is, in this example, the red compressed color difference signal (RY) 'in the n-1 line is written in the first CCD memory (21A) for a period of 0.5H (D in the figure), and the next 0.5H. In the section (2), the blue compressed color difference signal (BY) '(E in the figure) is similarly written in the n-1 line in the second CCD memory (21B). Then, the red compressed color difference signal (RY) 'in the n-line is written in the third CCD memory (21C) over a period of 0.5H in the first half (F in the same figure) and 0.5H in the latter half. Similarly, the blue compressed color difference signal (B-
Y) 'is written (G in the figure).

When the pair of CCD memories (21C) and (21D) in the latter half are in the write mode, the pair of CCD memories (21A) in the first half
And (21B) are controlled in the read mode. Therefore, when the pair of CCD memories (21C) and (21D) in the latter half are in the write mode, the pair of CCD memories (21A) and (21B) are simultaneously in the read mode in synchronization with the read zero pulse P _R (see FIG. D, E). In this case, the frequency of the read clock is 1/2 of the frequency of the write clock, so the time of the red and blue color difference signals RY and BY read from the CCD memories (21A) and (21B). The axis is stretched back to the time axis.

Similarly, when the pair of CCD memories (21A) and (21B) are in the write mode, the other pair of CCD memories (21C) and (21D) are in the read mode, respectively, as shown in FIGS. Red and blue color difference signals R- whose time axis is doubled
Y and BY are read.

These red and blue color difference signals RY, which have been expanded on the time axis,
BY is supplied to the corresponding switching means (31) and (32), respectively, the red color difference signal RY from one switching means (31) and the blue color difference signal from the other switching means (32). The switching control is performed so that BY is output respectively. Therefore, a switching pulse of 2H cycle is supplied from the clock generator (25).

In this way, in the time axis expansion circuit (20), the time axis compressed red and blue color difference signals (RY) 'and (BY)' are time axis expanded and sequentially converted into signals for output. , And these are supplied to the comb type filters (35) and (36) via the low-pass filters (33) and (34), respectively.

The comb type filters (35) and (36) are provided for different CCDs.
When the color difference signals output from the memory are serialized, line-to-line deviation (line crawling) caused by gain variations, linearity differences, output DC level differences, etc. in each CCD memory (21A) to (21D) Is to remove.

Red and blue color difference signals R-
Y and BY are supplied to an encoder (40) respectively, and after being subjected to encoding processing, the color difference signal S _C is supplied to a mixer (13) and is combined with a luminance signal S _Y to be a generally known color video signal.
Converted to S _V.

Thus writing at timing when the second synchronization signal P _R2 write zero pulses P _W formed on the basis of writing the compressed color difference signal S _'C in the memory device (21), also inserted in the luminance signal S _Y If read at the timing of the read zero pulse P _R formed based on the first synchronization signal P _R1 , the luminance signal S _Y
And the time axis of the color difference signal S _C whose time axis is extended can be perfectly matched.

By the way, the FIG. 5 A and write zero pulses P _W as shown in B and the read-zero pulses P _R is obtained at the same timing rotary magnetic head H _Y abutting on the magnetic tape as shown in FIG. 2 B, H It is obtained when the distance W _H between the gear gaps of _C is as designed. Therefore, if the gap W _H between gears fluctuates or jitter occurs between Y and C due to variations in manufacturing, the write zero pulse P _W and read zero pulse P _R cannot be obtained at the same timing. .
For example, when the gap between gears _WH is wider than the specified value, the reproduced luminance signal S _Y and the compressed color difference signal S ′ _C are reproduced.
And are as shown in Fig. 6A and B, and write zero pulse
The read zero pulse P _R is obtained before P _W in terms of time (C and D in FIG. 6).

On the other hand, since the read mode for the memory element (21) starts independently of the write mode, as shown in FIG. 6F, the read is started in the state where the write is not completed completely, or the read is completed completely. Writing may start before it is finished.

When the write clock frequency is selected to 720H as described above, the clock for writing the compressed color difference signal is approximately 341 clocks, and the number of read clocks is 682 clocks. Therefore, as shown in FIG. W2 and W3 are about 19 clocks, and the section W1 from reading to the next write operation is about 38 clocks.

Therefore, if the mechanical error between the heads H _Y and H _C or the jitter between Y / C is within the period W3, the error and the jitter can be absorbed. However, if the error or jitter is larger than that, the write and read operations are partially overlapped as shown in FIG. In order to prevent such overlapping of writing and reading, for example, as shown in FIG. 7, the reading zero pulse P _R is always generated with a time delay with respect to the writing zero pulse P _W , and The interval W _X may be controlled so as to always have a predetermined value. By providing the interval W _X , the write and read idle periods W _a and W _b are lengthened, so that even if a mechanical error of the rotating magnetic head or a jitter occurs between Y and C. , It is possible to remove a partial overlap between writing and reading. In this example, the interval W _X is selected such that the idle period W _a from the end of reading to the start of writing is equal to the idle period W _b from the end of writing to the start of reading.

When selecting the clock frequency as described above, since W _a corresponds to approximately 28.5 clocks, this results in approximately 2.
The rest time W _a is 5 μsec.

FIG. 8 shows an example for obtaining such a period W _a . In this example, the color delay signal system has a variable delay means.
(40) is provided. A CCD, for example, can be used as the variable delay means (40), and the delay amount is a delay amount corresponding to 1H + W _X.

In order to keep the period W _X constant regardless of the mechanical error of the rotating magnetic head and the jitter between Y / C, in this example, the first synchronization signal P _Y separated from the luminance signal S _Y is used. The second sync signal P separated from _R1 and the compressed color difference signal S _C
By supplying _R2 to the phase comparison circuit (41) and controlling the VCO (42) based on the phase error output, the frequency of the clock supplied to the variable delay means (40) is controlled.

According to this configuration, even if the mechanical error of the rotating magnetic head differs depending on the integrated video used, or the amount of jitter between Y / C differs, W _X is always held for the set period. Since the relationship between the two is controlled, it is possible to always form _a constant idle period W _a between the writing period and the reading period.

As described above, according to the present invention, the writing of the compressed pair of component color signals reproduced from the recording medium to the memory element is inserted into the reproduced compressed pair of component color signals. Since the writing is started in synchronism with the writing start signal delayed to the starting position in synchronism with the synchronizing signal, it is possible to write accurately from the starting position of the reproduction compression pair of component color signals, and to the second synchronizing signal. Since the writing is performed with the synchronized m-multiplication frequency clock, it is possible to always write up to the end position of the component color signal on a constant time axis.

On the other hand, the read from the memory element is performed in synchronization with the read start signal delayed to the start position in synchronization with the first synchronization signal inserted in the reproduction luminance signal reproduced from the recording medium. , The start position of the component color signal written in the memory element can be accurately read and started in accordance with the start position of the reproduction luminance signal, and the end position of the reproduction compressed color signal is synchronized with the first synchronization signal. Since the reading is performed by the m / n multiplied frequency clock, it is possible to read on the accurate time axis where the end position of the color signal expanded to n times and the end position of the luminance signal coincide with each other.

Therefore, the time axis of the reproduction luminance signal and the time axis of the color signal read out by extending the time axis from the memory element can be perfectly matched. In other words, the time axis of the chrominance signal with respect to the luminance signal can be perfectly aligned, and this can be achieved with a simple configuration.

Further, since two pairs of CCD memories are used as the above memory elements and when one pair of CCD memories is in the writing state, the other pair of CCD memories is controlled to be in the reading state. Readout can be performed continuously and smoothly.

Further, the phase difference between the reproduced first synchronizing signal and the reproduced second synchronizing signal is detected by the phase difference detecting means, and the delay amount corresponding to the detected phase difference is written in the memory element by the variable delay means. Since the above-mentioned reproduction compression of a pair of component color signals is given, a mechanical error in which the interval between separate heads for reproducing a luminance signal and a pair of component color signals from a recording medium fluctuates due to variations during manufacturing, Even when a jitter occurs between the luminance signal and the pair of component color signals, it is possible to match the timing of the write start signal and the read start signal of the pair of component color signals supplied to the memory element, Partial overlap of the write and read operations does not occur.

[Brief description of drawings]

1 to 3 are diagrams used for explaining the present invention, FIG. 4 is a block diagram showing an example of a reproducing system in a color video signal reproducing apparatus according to the present invention, and FIGS. FIG. 8 is a block diagram similar to FIG. 4 showing another example of the present invention. H _Y and H _C are rotating magnetic heads, S _Y is a luminance signal, S ′ _C is a compression color difference signal, (20) is a time axis expander, (21) is a memory element, (2)
1A) to (21D) are CCD memories, (25) are clock generators, (3
5), (36) are comb filters, (40) are encoders, P _R1 , P
_R2 is the first and second synchronization signals, and _SV is the color video signal.

Front page continuation (72) Inventor Makoto Ishidori 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References JP-A-57-118490 (JP, A) JP-A-50- 11322 (JP, A) JP-A-57-13882 (JP, A)

Claims (3)

[Claims] 1. A luminance signal in which a first synchronizing signal having a constant time relationship with a horizontal synchronizing signal is inserted, and a second synchronizing signal having a constant time relationship with the first synchronizing signal is inserted, and 1 Reproducing the luminance signal and the pair of component color signals with different heads from the recording medium in which a pair of component color signals time-compressed at the compression ratio n in the horizontal section are simultaneously recorded on different tracks. In a color video signal reproducing apparatus, a write start signal delayed to the start position of the pair of component color signals in synchronization with the second synchronization signal inserted in the pair of reproduced component color signals. Write control signal generating means for generating a write control signal composed of a write clock having an m-multiplied frequency synchronized with the second synchronization signal; The read start signal delayed to the start position of the brightness signal in synchronization with the first sync signal inserted in the generated brightness signal and the m / n multiplication frequency synchronized with the first sync signal A read control signal generating means for generating a read control signal including a read clock having the same; a pair of component color signals written by the write control signal; and a pair of components already written by the read control signal. A color video signal reproducing apparatus for obtaining a pair of component color signals whose time axis is extended from said memory means and whose time axis is aligned with said luminance signal. . 2. The memory means has two pairs of CCD memories, and the write control signal generating means and the read control signal generating means include a pair of CCs of the two pairs of CCD memories.
When the D memory is in the write state, the write control signal and the read control signal are set to the two pairs of CCs so that the remaining pair of CCD memories are in the read state.
A pair of component color signals which are supplied to a D memory and whose time axis is expanded from the pair of CCD memories in the read state by the read control signal generating means. An apparatus for reproducing a color video signal according to the item. 3. A variable delay means for supplying the pair of reproduced component color signals, delaying the delayed component color signals and supplying the delayed pair of component color signals to the memory means, and an output of the variable delay means. The second sync signal in the pair of component color signals delayed from the
Phase difference detecting means for detecting a phase difference between the synchronizing signal of 1) and the first synchronizing signal inserted in the reproduced luminance signal, and supplying the phase difference detection output to the control input of the variable delay means. The pair of component color signals delayed by the delay amount corresponding to the phase difference detection output by the variable delay means are supplied to the memory means. An apparatus for reproducing a color video signal according to the item.