JPH0666408B2 - Multilayer semiconductor device - Google Patents
Multilayer semiconductor deviceInfo
- Publication number
- JPH0666408B2 JPH0666408B2 JP30729587A JP30729587A JPH0666408B2 JP H0666408 B2 JPH0666408 B2 JP H0666408B2 JP 30729587 A JP30729587 A JP 30729587A JP 30729587 A JP30729587 A JP 30729587A JP H0666408 B2 JPH0666408 B2 JP H0666408B2
- Authority
- JP
- Japan
- Prior art keywords
- package
- circuit assembly
- external connection
- assembly
- lead piece
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000000712 assembly Effects 0.000 claims abstract description 23
- 238000000429 assembly Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 2
- 230000006355 external stress Effects 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は同一パッケージ内に複数枚の回路組立体を立
体的に並べて収設した多層形半導体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer semiconductor device in which a plurality of circuit assemblies are three-dimensionally arranged and housed in the same package.
まず第３図，第４図により従来における多層形半導体装
置の構造例を示す。第３図の例では配線基板１に回路部
品２を実装して成る各独立構成の第１の回路組立体３と
第２の回路組立体４を上下向かい合わせに組合せてパッ
ケージ５で封止した構造であり、上下に並ぶ第1,第２の
回路組立体３と４との相互間が各層の回路組立体3,4よ
り引出してパッケージ５内に封止した内部接続用リード
片６を介して接続され、さらに各回路組立体3,4にはパ
ッケージ５より外方に引出した外部接続用リード片７が
接続されている。ここで回路組立体3,4より引出した内
部接続用リード片６の相互間，および回路組立体3,4と
外部接続用リード片７との間はそれぞれ突き合わせ式に
はんだ突け接合されている。First, FIGS. 3 and 4 show an example of the structure of a conventional multi-layer semiconductor device. In the example shown in FIG. 3, the first circuit assembly 3 and the second circuit assembly 4 each having an independent structure in which the circuit component 2 is mounted on the wiring board 1 are vertically face-to-face combined and sealed with the package 5. The internal connecting lead piece 6 which has a structure, and which is arranged between the first and second circuit assemblies 3 and 4 which are vertically arranged is pulled out from the circuit assemblies 3 and 4 of each layer and sealed in the package 5. Further, an external connection lead piece 7 drawn out from the package 5 is connected to each of the circuit assemblies 3 and 4. The internal connecting lead pieces 6 drawn out from the circuit assemblies 3 and 4 and the circuit connecting bodies 3 and 4 and the external connecting lead pieces 7 are butt-jointed by soldering.
また第４図の例では、上蓋８付きパッケージ５の底部に
第１の回路組立体３を配備し、その基板上方に並べてパ
ッケージ内に収容した第２の回路組立体４との間を回路
組立体３から立ち上がる内部接続用リード片６で接続，
担持した構造であり、内部接続用リード片6,外部接続用
リード片７が第３図と同様にはんだ付け接合されてい
る。Further, in the example of FIG. 4, the first circuit assembly 3 is arranged at the bottom of the package 5 with the upper lid 8, and the circuit assembly is arranged between the second circuit assembly 4 which is arranged above the substrate and accommodated in the package. Connect with the lead piece 6 for internal connection that rises from the solid body 3,
It has a carried structure, and the lead pieces 6 for internal connection and the lead pieces 7 for external connection are soldered and joined in the same manner as in FIG.
ところで上述した従来の多層形半導体装置では、特に回
路組立体３と４の相互間で内部接続用リード片６をはん
だ付けするには回路組立体３と４とをパッケージ５に仮
組立した状態で行うことからそのはんだ付け工法に特別
な工夫を必要とし、そのためにコスト高となる他、構造
面から外部応力がはんだ付け接合部に加わるために十分
な信頼性が得られない欠点がある。By the way, in the above-described conventional multilayer semiconductor device, in particular, in order to solder the lead pieces 6 for internal connection between the circuit assemblies 3 and 4, the circuit assemblies 3 and 4 are temporarily assembled in the package 5. Therefore, the soldering method requires special measures, which results in a high cost and also has a drawback that sufficient reliability cannot be obtained because external stress is applied to the soldered joint portion from a structural viewpoint.
この発明は上記の点にかんがみ成されたものであり、そ
の目的は各層の回路組立体相互間の内部接続，および外
部接続用リード片との間の接続を特別な工法に頼ること
なく通常のボンディング法で容易に対応でき、しかも外
部応力にも強く高信頼性が得られるようにした多層形半
導体装置の構造を提供することにある。The present invention has been made in view of the above points, and an object thereof is to connect an internal connection between circuit assemblies of each layer to each other and a lead piece for external connection without relying on a special construction method. It is an object of the present invention to provide a structure of a multi-layered semiconductor device which can be easily dealt with by a bonding method and which is strong against external stress and has high reliability.
上記問題点を解決するために、この発明によれば、上面
開口の蓋付きパッケージ内の上下方向に段差部が設けら
れ、該パッケージ内の各段差部に上下段に並べて大きい
回路組立体が上段側となるように各層の回路組立体が収
設され、かつパッケージの横一方向に同一高さに組み込
まれた外部接続用リード片と異なる高さの前記各層の回
路組立体との間をボンディング法によるワイヤで接続す
るとともに、高さの異なる回路組立体相互間の内部接続
を前記同一高さのリード片を中継してボンディング法に
よるワイヤで接続して構成するものとする。In order to solve the above-mentioned problems, according to the present invention, a step portion is provided in the up-down direction in a package with a lid having an upper surface opening, and a large circuit assembly is arranged on each step portion in the package in a vertical direction. The circuit assemblies of the respective layers are housed so that they are on the side, and the lead pieces for external connection incorporated at the same height in one lateral direction of the package are bonded to the circuit assemblies of the respective layers of different heights. In addition to the connection by the wire by the bonding method, the internal connection between the circuit assemblies having different heights is configured by relaying the lead pieces of the same height and by the wire by the bonding method.
上記の構成において、半導体装置を組立てるには、まず
下層側の回路組立体をパッケージ内の段差底部に収設し
た上であらかじめパッケージの成形時に一体に同一高さ
で組み込まれたリードフレームの外部接続用リード片と
前記回路組立体との間で外部接続，およびリード片を中
継材として次に組み込まれる上層側の回路組立体との間
の内部接続をボンディング法によるワイヤで結線する。
次にパッケージ内の中段位置に上層側の回路組立体を収
設し、ここで前記と同様に外部接続用リード片との間で
外部接続，および内部接続をボンディング法によるワイ
ヤで結線し、最後にパッケージに上蓋を被せて封止す
る。なお内部接続の中継用に用いたリード片は外部接続
の必要がない場合にはパッケージ端面で切断して接続ト
ラブルを避けるようにする。In order to assemble the semiconductor device with the above configuration, first, the lower layer circuit assembly is housed in the bottom of the step inside the package, and then the lead frame externally connected to the package at the same height when the package is molded. An external connection between the lead piece and the circuit assembly and an internal connection between the upper layer circuit assembly to be incorporated next using the lead piece as a relay material are connected by a wire by a bonding method.
Next, the upper layer side circuit assembly is housed in the middle position of the package, where the external connection and the internal connection are connected with the wire by the bonding method between the external connection lead piece and the external connection lead piece as described above. The package is covered with an upper lid and sealed. The lead pieces used for relaying the internal connection should be cut off at the package end face to avoid connection problems if external connection is not required.
このようにワイヤボンディング法により結線されたワイ
ヤは柔軟性があって応力に強く、外力が加わった場合で
もワイヤ自身で吸収できるので接合部が剥離する等のト
ラブル発生のおそれなしに高信頼性が得られ、外部接続
用リード片や、回路組立体相互間の内部結線には従来の
ように特別なはんだ付け工法を用いることなく通常のワ
イヤボンディング設備で容易に対応できる。The wire connected by the wire bonding method in this way is flexible and resistant to stress, and can be absorbed by the wire itself even when external force is applied, so there is no risk of trouble such as peeling of the joint portion and high reliability. The obtained wire pieces for external connection and the internal connection between the circuit assemblies can be easily dealt with by ordinary wire bonding equipment without using a special soldering method as in the prior art.
第１図，第２図は本発明の実施例を示し、第１図は半導
体装置の構成断面図、第２図はパッケージの外観斜視図
であり、第３図，第４図に対応する同一部材には同じ符
号が付してある。1 and 2 show an embodiment of the present invention, FIG. 1 is a sectional view of the structure of a semiconductor device, and FIG. 2 is an external perspective view of a package, which are the same as FIGS. 3 and 4. The members have the same reference numerals.
まずパッケージ５は上蓋８付きの樹脂製容器であり、そ
の側面にはパッケージの成形時にリードフレームとして
の外部接続用リード片７が一体に埋設されている。なお
リードフレーム上に記したＸ−Ｘ鎖線はリードフレーム
の切断線を表している。またパッケージ５の内部中段に
は段付き部51があり、特にリード片７の配置側では段付
き部を形成するブロック52をリード片７が貫通してい
る。一方、かかるパッケージ５の内部には上下段に並べ
て回路組立体3,4が収設されており、かつ各層の回路組
立体3,4とリード片７との間で後述のように外部接続，
および回路組立体相互間の内部接続がワイヤボンディン
グ法によりワイヤ９を介して結線されている。First, the package 5 is a resin container with an upper lid 8, and an external connection lead piece 7 as a lead frame is integrally embedded in the side surface of the package during molding of the package. The XX chain line on the lead frame represents the cutting line of the lead frame. Further, the package 5 has a stepped portion 51 in the middle level, and particularly on the arrangement side of the lead piece 7, the lead piece 7 penetrates a block 52 forming the stepped portion. On the other hand, inside the package 5, the circuit assemblies 3 and 4 are housed side by side in the upper and lower stages, and the external connection is made between the circuit assemblies 3 and 4 of each layer and the lead piece 7 as described later.
And the internal connection between the circuit assemblies is connected via the wire 9 by the wire bonding method.
次に上記構成に成る半導体装置の組立順序を説明する。
まずパッケージ５に対して、パッケージ内の底部に下層
側の回路組立体４を接着し、ここで回路組立体４と外部
接続用リード片７との間でワイヤボンディング法により
外部接続，およびリード片７を中継材として次に組み込
まれる上層側の回路組立体３との間の内部接続の結線を
行う。次にパッケージ５内の中段に上層側の回路組立体
３を載せて接着し、ここで回路組立体３と外部接続用リ
ード片７との間で前記と同様にワイヤボンディング法に
より外部接続，および内部接続の残り半分の結線を行
い、最後に上蓋８を装着して組立が完成する。なお、回
路組立体３と４との間の内部接続中継材として使用した
リード片７については、特に外部接続の必要がない場合
にはパッケージ５の端面で切断して不要な接続トラブル
を避けるようにする。Next, the order of assembling the semiconductor device having the above structure will be described.
First, the lower-layer side circuit assembly 4 is adhered to the bottom of the package 5 with respect to the package 5. Here, the circuit assembly 4 and the external connection lead piece 7 are externally connected by a wire bonding method, and the lead piece is connected. 7 is used as a relay material to connect the internal connection with the upper layer side circuit assembly 3 to be incorporated next. Next, the upper layer side circuit assembly 3 is placed on the middle stage of the package 5 and adhered thereto. Here, the external connection is made between the circuit assembly 3 and the external connection lead piece 7 by the wire bonding method as described above, and The other half of the internal connections are connected, and finally the upper lid 8 is attached to complete the assembly. The lead piece 7 used as a relay material for the internal connection between the circuit assemblies 3 and 4 should be cut at the end face of the package 5 to avoid unnecessary connection troubles, especially when external connection is not required. To
以上述べたようにこの発明によれば、上面開口の蓋付き
パッケージ内に上下方向に段差部が設けられ、該パッケ
ージ内の各段差部に上下段に並べて大きい回路組立体が
上段側となるように各層の回路組立体が収設され、かつ
パッケージの横一方向に同一高さに組み込まれた外部接
続用リード片と異なる高さの前記各層の回路組立体との
間をボンディング法によるワイヤで接続するとともに、
高さの異なる回路組立体相互間の内部接続を前記同一高
さのリード片を中継してボンディング法によるワイヤで
接続して構成したことにより、従来構造のように上下に
並ぶ回路組立体相互間の内部接続に特別な部品又は特殊
構造や特別な工法で行うはんだ付け等が必要なく、通常
のワイヤボンディング設備を用いて簡単に全ての内部結
線を自動的に遂行できるので従来装置と比べて工数，製
造コストの低減化が図れる。しかもボンディングワイヤ
は柔軟性があって応力に強く、装置内部の結線に対して
高い信頼性が得られる。As described above, according to the present invention, the stepped portions are provided in the up-down direction in the package with the lid having the upper opening, and the large circuit assemblies are arranged in the vertical steps on the stepped portions in the package so that the large circuit assembly is on the upper side. Each layer of the circuit assembly is housed in the package, and a wire by a bonding method is used between the external connection lead piece installed at the same height in one lateral direction of the package and the circuit assembly of each layer of different height. With connecting
Since the internal connections between the circuit assemblies having different heights are configured by connecting the lead pieces of the same height by the wire by the bonding method, the circuit assemblies are vertically arranged as in the conventional structure. There is no need for special parts or a special structure for internal connection, or soldering performed by a special construction method, and all internal wiring can be automatically performed easily using ordinary wire bonding equipment. The manufacturing cost can be reduced. Moreover, the bonding wire is flexible and resistant to stress, and high reliability can be obtained for connection inside the device.
【図面の簡単な説明】 第１図は本発明実施例による半導体装置の構成断面図、
第２図は第１図におけるパッケージの外観斜視図、第３
図，第４図はそれぞれ従来における多層形半導体装置の
構成断面図である。各図において、 3,4:回路組立体、5:パッケージ、7:外部接続用リード
片、8:上蓋、9:ワイヤ。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention.
2 is an external perspective view of the package in FIG. 1, FIG.
FIG. 4 and FIG. 4 are cross-sectional views of conventional multi-layer semiconductor devices. In each figure, 3,4: Circuit assembly, 5: Package, 7: Lead piece for external connection, 8: Top cover, 9: Wire.
Claims (1)
を立体的に並べて収設した多層形半導体装置であって、
上面開口の蓋付きパッケージ内の上下方向に段差部が設
けられ、該パッケージ内の各段差部に上下段に並べて大
きい回路組立体が上段側となるように各層の回路組立体
が収設され、かつパッケージの横一方向に同一高さに組
み込まれた外部接続用リード片と異なる高さの前記各層
の回路組立体との間をボンディング法によるワイヤで接
続するとともに、高さの異なる回路組立体相互間の内部
接続を前記同一高さのリード片を中継してボンディング
法によるワイヤで接続したことを特徴とする多層形半導
体装置。1. A multilayer semiconductor device in which two or more circuit assemblies are three-dimensionally arranged and housed in the same package.
A step portion is provided in the up-down direction in the package with a lid having an upper surface opening, and a circuit assembly of each layer is housed in such a manner that a large circuit assembly is vertically arranged in each step portion of the package so that a large circuit assembly is on the upper side. In addition, the external connection lead pieces incorporated at the same height in one lateral direction of the package and the circuit assemblies of the respective layers having different heights are connected by wires by a bonding method, and the circuit assemblies having different heights are connected. A multi-layered semiconductor device characterized in that internal interconnections between them are relayed by lead pieces of the same height and connected by wires by a bonding method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30729587A JPH0666408B2 (en) | 1987-12-04 | 1987-12-04 | Multilayer semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30729587A JPH0666408B2 (en) | 1987-12-04 | 1987-12-04 | Multilayer semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01147850A JPH01147850A (en) | 1989-06-09 |
| JPH0666408B2 true JPH0666408B2 (en) | 1994-08-24 |
Family
ID=17967416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30729587A Expired - Lifetime JPH0666408B2 (en) | 1987-12-04 | 1987-12-04 | Multilayer semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666408B2 (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2780424B2 (en) * | 1990-03-22 | 1998-07-30 | 株式会社デンソー | Hybrid integrated circuit |
| JP2705368B2 (en) * | 1991-05-31 | 1998-01-28 | 株式会社デンソー | Electronic equipment |
| JP2765278B2 (en) * | 1991-05-31 | 1998-06-11 | 株式会社デンソー | Electronic device manufacturing method |
| US5646827A (en) * | 1991-05-31 | 1997-07-08 | Nippondenso Co., Ltd. | Electronic device having a plurality of circuit boards arranged therein |
| EP0516149B1 (en) * | 1991-05-31 | 1998-09-23 | Denso Corporation | Electronic device |
| JP3357220B2 (en) * | 1995-07-07 | 2002-12-16 | 三菱電機株式会社 | Semiconductor device |
| JP3396566B2 (en) * | 1995-10-25 | 2003-04-14 | 三菱電機株式会社 | Semiconductor device |
| US5856915A (en) * | 1997-02-26 | 1999-01-05 | Pacesetter, Inc. | Vertically stacked circuit module using a platform having a slot for establishing multi-level connectivity |
| US6026325A (en) * | 1998-06-18 | 2000-02-15 | Pacesetter, Inc. | Implantable medical device having an improved packaging system and method for making electrical connections |
| ES2169687B2 (en) | 1999-09-30 | 2004-10-16 | Denso Corporation | ELECTRONIC CONTROL UNIT WITH ACTIVATION ELEMENT AND CONTROL TREATMENT ELEMENT. |
| US6442027B2 (en) | 2000-02-23 | 2002-08-27 | Denso Corporation | Electronic control unit having connector positioned between two circuit substrates |
| US6466447B2 (en) | 2000-02-24 | 2002-10-15 | Denso Corporation | Electronic control unit having flexible wires connecting connector to circuit board |
| US7211884B1 (en) | 2002-01-28 | 2007-05-01 | Pacesetter, Inc. | Implantable medical device construction using a flexible substrate |
| JP6015508B2 (en) * | 2013-03-18 | 2016-10-26 | 富士通株式会社 | High frequency module |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5586354U (en) * | 1978-12-11 | 1980-06-14 | ||
| JPS58195445U (en) * | 1982-06-22 | 1983-12-26 | 三菱電機株式会社 | Semiconductor integrated circuit package |
-
1987
- 1987-12-04 JP JP30729587A patent/JPH0666408B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01147850A (en) | 1989-06-09 |
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