JPH066590A - Image signal processing unit - Google Patents

Abstract

PURPOSE:To obtain an image signal processing unit at a low cost by using an adder comprising less gates so as to realize a shading correction circuit. CONSTITUTION:Reference white level board data Sx by one line are inputted from an input terminal 1 and transformed into a Log Sx by a Log transformation means 8 sequentially and stored in a storage means 2. When original image data Ix are inputted from the input terminal 1, the Log transformation means 8 transforms the data into a Loglx when the original image data Ix are inputted from the input terminal 1, a storage means 2 reads reference white board data LogSx corresponding to the LOgIx from the storage means 2 and an adder means 9 calculates LogI'x=LogIx-LogSx=Log(Ix/Sx). Furthermore, the LogI'x is transformed into the I'x by an anti-Log transformation means 10 to obtain I'x=Ix/Sx. The I'x and a threshold level R are compared to binarize the value depending on the quantity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device for reproducing an original image in binary of black and white.
The present invention relates to a shading correction circuit of a facsimile device using a line scanner as a document reading device.

[0002]

2. Description of the Related Art Generally, a facsimile machine illuminates an original with a light source, receives the reflected light with a line scanner, converts the light and shade of the original into an electric signal, and converts this into black and white binary data by an image signal processing circuit. To reproduce the image. However, the image signal output from the line scanner is not uniform due to variations or unevenness of the light source, variations in characteristics between the bits of the line scanner, and the like. That is,
Even if you read a pure white manuscript, you cannot get a certain level of output. In order to correct this nonuniformity, shading correction is performed to normalize the original image data with the reference whiteboard data.

FIG. 2 is a block diagram showing a conventional shading correction circuit. In FIG. 2, reference numeral 1 is an input terminal for reference whiteboard data Sx and original image data Ix, 2 is reference whiteboard data storage means (hereinafter simply referred to as storage means) for storing reference whiteboard data Sx for one line, and 3 is reference whiteboard data. Reciprocal conversion means for obtaining the reciprocal of Sx, 4 is multiplication means for multiplying the reciprocal of the original image data Ix by the reference whiteboard data Sx, 5 is an input terminal for inputting the binarization threshold value R, and 6 is a multiplication result I ′. Binarizing means for binarizing the image data by comparing x = Ix / Sx with the threshold value R, and 7 is an output terminal for the binarized signal Px. Here, x means a coordinate in the main scanning direction.

Next, the operation of the conventional example will be described. First, the reference whiteboard data Sx for one line is input from the input terminal 1 and stored in the storage means 2. Next, when the original image data Ix is input from the input terminal 1, the reference whiteboard data Sx corresponding to Ix is read from the storage means 2, the reciprocal conversion means 3 calculates 1 / Sx, and the multiplication means 4 is used. I'x =
Ix * (1 / Sx) = Ix / Sx is calculated. By this operation, the original image data Ix is converted into the relative ratio I'x with respect to the reference whiteboard data Sx, and thereby the nonuniformity between dots is corrected. Then, the binarizing means 6 compares the value I′x with the threshold value R input from the input terminal 5 to obtain I′x.
When x <R, Px = 1 is output to the output terminal 7, and otherwise Px = 0 is output to the output terminal 7.

[0005]

However, the conventional shading correction circuit described above has a problem in that it requires a multiplier having a large number of gates, resulting in a large circuit scale.

The present invention solves this problem of the prior art. A shading correction circuit is realized by an adder having a small number of gates without using a multiplier having a large number of gates, and a low-cost image signal is realized. An object is to provide a processing device.

[0007]

In order to achieve the above object, the present invention provides a Log (logarithm) conversion means for inputting reference whiteboard data Sx and image data Ix to be binarized and outputting LogSx and LogIx, respectively. And the reference whiteboard data LogS
From the reference whiteboard data storage means for storing x, the LogIx output from the Log conversion means and the LogSx output from the reference whiteboard data storage means, LogI'x = LogIx-Log
A value obtained by normalizing the image data Ix from the log I'x with the reference whiteboard data Sx I'x =
An AntiLog (exact number) conversion means for obtaining Ix / Sx and a binarization means for comparing the normalized image data I′x with the binarization threshold value R and outputting binary data are provided. It will be configured.

[0008]

According to this structure, it is not necessary to use a multiplier, and the adder provided in its place has a small number of gates, so that the circuit scale is reduced and the cost is reduced.

[0009]

Embodiments will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an image signal processing apparatus according to an embodiment of the present invention. The same components as those in FIG. 2 or those having the same names are designated by the same reference numerals. However, 2 stores the reference whiteboard data Sx in FIG. 2, but stores the LogSx obtained by Log converting the reference whiteboard data Sx here. Further, 8 is Log conversion means, 9 is addition means, and 10 is AntiLog.
It is a conversion means. 2 is different from the configuration of FIG. 2 in that the reciprocal conversion unit 3 and the multiplication unit 4 are replaced with a Log conversion unit 8, an addition unit 9, and an AntiLog conversion unit 10.

The operation of the image signal processing apparatus in this embodiment will be described below. First, the reference whiteboard data Sx for one line is input from the input terminal 1, sequentially converted into the LogSx by the Log conversion unit 8, and stored in the storage unit 2. Next, when the original image data Ix is input from the input terminal 1, it is converted into LogIx by the Log conversion means 8, the reference whiteboard data LogSx corresponding to the LogIx is read from the storage means 2, and added by the addition means 9. LogI'x = L
ogIx-LogSx = Log (Ix / Sx) is calculated. Further, the LogI'x is converted into I'x by the AntiLog conversion means 10. By this operation, the relative ratio I'x = Ix / Sx can be obtained as in the conventional example shown in FIG. In the subsequent operation, as in the conventional example, the binarizing means 6 compares the value I′x with the threshold value R input from the input terminal 5, and when I′x <R, Px = 1 and otherwise Px = 0 is output to the output terminal 7.

Log conversion means 8 and AntiLog conversion means 10
Is a small capacity ROM or RAM, and Ix
Even if Sx and Sx are 8 bits, a capacity of 256 bytes is sufficient.

Further, as a modified example of the present circuit, the characteristic curve of the Log conversion may have an offset according to the characteristic of the scanner and the memory capacity. See also Anti
The characteristic curve of the Log transformation may be a curve in which a visual characteristic is corrected instead of the simple inverse function of the Log transformation.

[0013]

As described above, according to the present invention,
Since the adder having a small number of gates can be configured with a small-capacity memory, there is an effect that the circuit scale becomes small and IC can be easily made.

[Brief description of drawings]

FIG. 1 is a block diagram of an image signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional shading correction circuit.

[Explanation of symbols]

2 ... Reference whiteboard data storage means, 6 ... Binarization means,
8 ... Log conversion means, 9 ... Addition means, 10 ... AntiL
og conversion means.

Claims (1)

[Claims] 1. A Log conversion means for inputting reference whiteboard data Sx and image data Ix to be binarized and outputting LogSx and LogIx respectively, reference whiteboard data storage means for storing reference whiteboard data LogSx, and said Log conversion. From the LogIx output from the means and the LogSx output from the reference whiteboard data storage means, LogI'x = LogIx-Log
A value obtained by normalizing the image data Ix from the log I'x with the reference whiteboard data Sx I'x =
An AntiLog conversion means for obtaining Ix / Sx and a binarization means for comparing the normalized image data I′x with a binarization threshold value R and outputting binary data are provided. Image signal processing device.