JPH0659648A - Multi-media display control system for storing image data in frame buffer - Google Patents

Abstract

PURPOSE:To provide a display system which substitutes a part of display function with a normal display controller used for a main body in a portable computer adopting a TFT color LCD and the like. CONSTITUTION:An MPEG board is connected to a computer main body, wherein the board is equipped with an expansion circuit for image compression data of YUV 31 and a YUV/RGB conversion circuit 35 converting moving image data expanded. A display controller chip in the main body has a frame buffer converting display timing from that for CTR to that for monochromatic LCD. The moving image data of RGB form outputted is stored in the frame buffer 25. By using this the display timing is converted to that of monochromatic LCD from that of CRT, and moving image data is stored in the frame buffer, displaying the display data of VGA with a common display circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control system, and more particularly to a multimedia display control system for storing image data in a frame buffer.

[0002]

2. Description of the Related Art Conventionally, a VGA (Video Graphics Array) has been used as a graphics controller (video subsystem) for a portable computer.
s) is used. VGA has a mechanism to control the display display, resolution 640x480 pixels,
It has a display function of 250 colors. On the other hand, Win
Windows and OS / 2 presentation manager (P
M) and other graphical user interfaces have been developed. There is a user's desire to move such a GUI efficiently.

In order to solve such a problem, in addition to the graphic subsystem (display controller, RAMDAC, etc.) built in the computer body, a Featur is installed in an expansion slot of the computer body.
There are portable computers that are configured to allow connection of other display cards, for example display cards of higher resolution than the built-in graphics subsystem, through industry standard connectors called e-connectors. For example, a color CRT connected to a CRT connector provided as a standard on the body of a portable computer displays a screen of a display controller mounted as standard on the body, and a CRT on a display board inserted into an expansion slot of the portable computer. Display data from another display controller and display data from the display controller in the main body are switched and displayed on the CRT connected to the connector.

However, when switching and displaying the display data from the two different types of display controllers, the display device is conventionally limited to the CRT.

In order to solve this problem, a technique has been developed in which display data from two different types of display controllers are switched and displayed on a flat panel display. As such an example, for example, US ser
ial No. 07 / 953,152 (filling
date: September 29, 1992, In
Ventor: Hiroki ZENDA). According to this application, a connector for connecting a second graphic subsystem is provided in an expansion slot of a portable computer having a TFT color LCD and a first graphic subsystem. Further, the display data from the first graphic subsystem and the display data from the second graphic subsystem are switched to switch the color LC.
It has a switching circuit for supplying display data to the D controller. When the second graphics subsystem is not connected, the switching circuit transfers the display data and the control signal from the first graphics subsystem to the color LC.
Supply to D controller. As a result, the color LCD controller displays the display data from the first graphics subsystem on the color LCD. When the second graphics subsystem is connected through the connector, the control signal from the first graphics subsystem is blocked with a predetermined time difference. As a result, the display data and control data from the second graphics subsystem are color LC.
It is supplied to the D controller. As a result, color LCD
The controller displays the display data from the second graphics subsystem on the color LCD. As a result, a plurality of types of display controllers can be switched to display on a single flat panel display.

In recent years, with the development of portable computers, computers called multimedia personal computers have been developed. In this computer, in addition to text data and graphics data, image data such as moving images and still images can be displayed on the CRT. The image data is displayed in YUV, which has been used in televisions and videos.
Since it is performed using signals, text data and graphics data are displayed using the RGB display circuit built in the computer main body, and image data is displayed by connecting the option board to the computer main body. As such an option board, for example, US C-C
ube Microsystems CL-450 (R
Egged Trademark) Develo
There is a pment board. This board is MPEG
(Moving Picture Coding Exp
erts Group) video algorithm
MPEG compressed vid using m
The eo signal is expanded and the YUV signal is converted into an RGB signal and output. MPEG is an organization that promotes the standardization of color moving image storage encoding methods, and is jointly promoted by ISO (International Organization for Standardization) and IEC (International Electrotechnical Commission).
It is a subordinate organization of TCI (International Standardization Technical Committee on Information Processing). On the other hand, it may also refer to an encoding method for storing color moving images. MP for application to CD-ROM
There are EG-1 and MPEG-2 aiming for higher image quality. The transfer rates are 1.5 Mbit / sec or less and 5 respectively.
It is M-10 Mbit / sec.

In addition, DVI (Dig of Intel Corp.
Italic Video Interactive) boards are known. On this DVI board, a 82750PB chip for compressing / decompressing an image, a VRAM for storing image data, and a 827 for controlling display of image data.
A 50DB chip or the like is mounted.

[0008]

However, when such an option board is connected to the computer main body, there are two display subsystems, an RGB display sub-system incorporated in the computer main body and a YUV display sub-system on the option board. There will be two subsystems,
It has a drawback that the circuit configuration becomes redundant.

Further, with the development of laptop type portable computers, even in portable computers adopting a flat panel such as TFT color LCD, image data such as text data, graphics data, moving image data and still image data are displayed and It is desired to perform mixed display using a flat panel display.

An object of the present invention is to provide a TFT for a display device.
In a portable computer that adopts a flat panel display such as a color LCD, the display controller installed as standard in the main body is used to substitute a part of the display function of another display controller, so that graphics data and image data can be obtained. It is an object of the present invention to provide a display system capable of displaying and with a common display circuit.

[0011]

According to the first aspect of the present invention, a display control system in a portable computer equipped with a flat panel display unit is provided with R image data supplied from the outside to the portable computer. (Red), G (gree
n), means for receiving in B (blue) form; used for converting display timing for a CRT display device to display timing for the flat panel display, and used for storing the image data Frame buffer memory means;
Video memory means for storing text data and graphics data; palette means for color-converting display data output from the video memory means; image data output from the frame buffer means and output from the palette means Selecting means for selectively outputting the display data to be displayed; gradation control means for controlling the gradation of the display data output from the selecting means and outputting to the flat panel display unit; and outputting from the selecting means And D / A converter means for converting the displayed data into R, G, B analog signals.

According to a second aspect of the present invention, there is provided a multimedia display control system, comprising frame buffer means for storing decompressed image data; and decompressed image data provided before the frame buffer means. Based on the control information from the means for receiving the display control information of the image data; and a means for holding the control information for displaying the image data; And means for controlling the means for temporarily holding the expanded image data and writing the image data in the frame buffer means in real time.

According to the third aspect of the present invention, the still image data or the moving image data stored in the frame buffer is read out and enlarged or reduced to an arbitrary size and displayed at an arbitrary position on the screen to be displayed. A display controller for displaying, a means for holding a value indicating a size of data stored in the frame buffer, horizontal and vertical scale values indicating a reduction ratio, and a value indicating an area of a window to be displayed; Means for performing a reduction process by omitting specific dots of image data or moving image data; and determining whether or not the reduction ratio is such that the amount of data to be displayed is less than the amount of data to be omitted. If any, it is provided with means for changing the rate of omission so as to obtain the data to be displayed.

According to the fourth aspect of the present invention, the moving picture data display control system is supplied from the outside, R
GB Each n-bit expanded moving image data is converted into RGB m
Means for converting (n> m) -bit moving image data; means for superimposing moving image data and display data of the high-resolution graphic subsystem; n-bit display data from the high-resolution graphic subsystem or the superimposing means Means for converting the n-bit output from each of the RGB into m-bit color data of RGB; and an output from the means of converting into RGB m-bit moving picture data into n-bit color identification data, Means for converting the output from the means for converting to bit color data into n-bit color identification data; means for holding the n-bit color identification data obtained by converting the RGB m-bit color data; The n-bit color identification data obtained by converting each m-bit moving image data is compared with the color identification data held by the holding means. Color identification data also close values n
And a means for writing to the frame buffer as bit moving image data. .

[0015]

1 is a block diagram showing the entire multimedia display control system of the present invention. central
A processing unit (CPU) 1, a main memory 3, a video capture board 5, and a multimedia display controller 7 are connected to a CPU bus 9. The system bus controller 11 is connected to the CPU bus 9 and the system bus 13. System bus 1
3, a CD-ROM controller 15 is further connected, and the CD-ROM controller 15 has a CD-ROM.
17 is connected. The video decoder 19 is connected to the system bus 13, the frame buffer memory 21, and the multimedia display controller 7. Further, frame buffer memories 23 and 25, a flat panel display (FPD) 27, and a CRT 29 are connected to the multimedia display controller 7. The frame buffer memory 21 is used when decompressing compressed image data. The frame buffer memory 23 is used to store VGA display data, for example. The frame buffer memory 25 is used to store moving image data. The video capture board 5 compresses / decompresses the compressed image data stored in the CR-ROM 17, for example, and outputs it in YUV form or RGB form. The video capture board 5 is, for example, MPE.
G (Motion Picture Experts)
Group) board, and such a video capture board (hereinafter referred to as an MPEG board) is, for example, US C-CUBE MICROSYSTEMS.
"CL450 (R) Development
"Board" is applicable. For details of this board, refer to "CL450 MPEG VIDEO DECODE."
ER USER'S MANUAL "(released in 1992) and" C-CUBECL450DEVELOP "
MENT KIT USER'S GUIDE ”(19
1992 release). Video decoder 1
Reference numeral 9 converts the expanded moving image data output from the MPEG board into 8-bit RGB data, for example, and supplies it to the multimedia display controller 7. The multimedia display controller 27 can display still images, normal images, graphics data, still images,
Each display timing for displaying each moving picture or mixed display thereof, processing for superimposing, control of display area, enlargement / reduction processing, control of writing and reading of moving picture data to the frame buffer memory 25, and Performs processing such as memory address control. The frame buffer memory 25 stores MPEG video data and DV described later.
In addition to moving image data such as I-video data, JPEG (Joi
nt Photographic Experts G
It is also possible to store still images such as "group". Hereinafter, in the embodiment of the present invention, the image data includes moving image data and still image data. JPEG is an organization that promotes the standardization of color still image encoding methods, and is a joint organization of ISO (International Organization for Standardization) and CCITT (International Telegraph and Telephone Consultative Committee). On the other hand, it may also refer to a color still image encoding method.

FIG. 2 is a diagram showing the concept of storing moving image data supplied from an MPEG board in a frame buffer provided in the computer main body in the multimedia display control system shown in FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, CR
By storing the moving image data using the frame buffer 25 for converting the T display timing into the monochrome LCD timing, the redundancy of having the display timing conversion buffer from the CRT to the LCD and the moving image data storage frame buffer is provided. Eliminates and simplifies the circuit.

In FIG. 2, a graphic subsystem built in the computer main body is a display subsystem for displaying graphic software.
For example, VGA Video Graphics Arra
ys). On the MPEG board 5, a decompression circuit, a single port dynamic random access memory (DRAM) 21, and a YUV / RGB conversion circuit 35.
Has been implemented. The decompression circuit 31 has a function of decompressing image compression data supplied via the CPU bus 9.
The expansion circuit 31 expands the image (moving image / still image) compressed data received via the CPU bus 9 to the DRAM.
(Dynamic Random Access Me
Write to 21). The image compressed data is stored in, for example, a hard disk or a CD-ROM 17 not shown. The compressed image data is decompressed and output as 32-bit data to a frame buffer 25 provided on the computer main body side through a connector (not shown) provided on the portable computer main body side and a light port of the frame buffer 25. For more information on frame buffer 25, see USSN 07 / 906,83.
4 are described.

The DRAM 21 stores the calculation result of the microcode and the compressed data.

The output of the expansion circuit is connected to the YUV / RGB converter 35. YUV is a method of displaying using luminance and color coordinates, and is a method used in television, video, and the like. YUV / RGB converter 35
Performs conversion from YUV to RGB using the following equation. In addition, Y represents luminance and U and V represent chromaticity.

G = Y-0.509228V-0.194888U. ． ． (1a) R = Y + V. ． ． (1b) B = Y + U. ． ． (1c) However, 0.0 <G, R, B <1.0 0.0 <Y <1.0 −0.701 <V <+0.701 −0.886 <U <+0.886 YUV to RGB The conversion to is done on a pixel-by-pixel basis.
The image data of the RGB form output from the YUV / RGB converter 35 is written in the frame buffer 25.

The frame buffer 25 has two roles. One is that the display device is a monochrome LCD (Liquid
CRT in the case of Crystal Display)
By reading the display data written in the frame buffer at the timing of, at the timing of the monochrome LCD,
Used to display data on monochrome LCD at CRT timing. Another role is that when a TFT color LCD is used as a display device, it is not necessary to convert the CRT timing to the LCD timing by using the frame buffer 25. It is used as a memory for storing the image expansion data of the RGB form output from the circuit 35.

The VGA memory 23 is a VRAM for storing display data in the VGA graphic subsystem. Display data is written in the VGA memory 23 by the CPU via the CPU bus 9. The display data stored in the VGA memory 23 is read out via the display read port and output to the palette 39. The palette 39 color-converts the display data and outputs it to the multiplexer 41. The multiplexer 41 outputs the display data from the palette 39 to the DAC 47 when the display device is a CRT, and the frame buffer 25 when the display device is a color LCD.
And outputs the RGB data to the color LCD gradation circuit 45. In this embodiment, the DAC 47 has a 24-bit input, and the 18-bit data output from the palette 39 is further added with 6-bit dummy data and input as 24-bit data to the DAC 47. . It should be noted that the DAC 47 has an input of 18 bits, and 6 bits of the 24-bit image data output from the frame buffer 25 are deleted to be 18 bits, or converted to 18 bits by using a color lookup table. Alternatively, it may be input to the DAC.

It should be noted that in FIG. 2, VGA surrounded by a broken line
VGA where the part that is written as the core is conventionally known
Chips (eg, Para. USA, December 9, 1988)
dise Systems, Inc. "PVGA1A" chip shown in the PVGA1A specification issued by the company, and in the present invention, the pallet 3
9, a multiplexer 41, a monochrome LCD gradation control circuit 43, a color LCD gradation control circuit 45, and a DAC 47 are added to form a one-chip LSI.

The flow of display data when the display device is a monochrome LCD, a color LCD, or a CRT will be described below.

In the case of a monochrome LCD, the display data written in the VGA memory 23 is read out through the display read port and written in the frame buffer 25 through the write port of the frame buffer 25. The display data written in the frame buffer 25 is read at the display timing of the monochrome LCD, and the monochrome LC
It is output to the monochrome LCD via the D gradation control circuit 43.

In the case of a color LCD, VGA memory 2
The display data read from No. 3 is subjected to color conversion in the palette 39 and output to the color LCD by the multiplexer 41 via the color gradation control circuit 45.

In the case of a CRT, the display data output from the VGA memory 23 is color-converted via the palette 39 and output to the DAC 47 by the multiplexer 24.
The color is further converted by the DAC 47 and output to the CRT.

As shown in FIGS. 3 and 4, a window for MPEG video data is cut on the VGA display screen,
Display data of VGA and MPEG video data can be mixedly displayed. As a method of this mixed display,
There are two ways. The first method is to display VGA display data together with MPEG display data in a 24-bit structure as shown in FIG. This is done by writing VGA display data and MPEG display data to the frame buffer 25, and passing the color LC through the multiplexer 41.
Display on D or CRT. However, 16 or 256 colors are sufficient for graphics data, and
We don't even need 24 bits per pixel. The second method is
As shown in FIG. 3, VGA graphics data is 4 bits (16 colors) or 8 bits (25 bits) per pixel.
This is a method of displaying only image data in a 24-bit structure as a 6-color structure. With this configuration, graphic data can be accessed only by 4 bits or 8 bits, and therefore high-speed processing is possible. this is,
A method of outputting VGA graphics data to the multiplexer 41 via the VGA memory 23 and the palette 39, outputting image data of the frame buffer 25 to the multiplexer 41, and controlling switching by the multiplexer 41 to output to a color LCD or CRT. Is.

In the above-described embodiment, the expansion circuit and the DRAM are provided on the MPEG board, and the MPEG board is connected to the computer main body through the connector. However, the expansion circuit and the DRAM are connected to the computer. It may be standardly mounted in the main body.

Further, although the TFT color LCD is used in the above-mentioned embodiment, the STN color LCD may be used.

FIG. 5 shows the writing of the moving picture data shown in FIG.
5 is a detailed block diagram of read-out control of moving image data from FIG. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals.

Display area and write FIFO controller 4
Reference numeral 9 controls the display area and the write FIFO 53 based on the control information from the moving picture control register 51. The enlargement / reduction and read FIFO control unit 55 controls the enlargement / reduction of the moving image data and the read FIFO 57 based on the control information from the moving image control register 51. The superposition control unit 59 uses the moving image control register 51.
Based on the control information from, the switching timing of the multiplexer 63 is controlled so that the moving image data read from the read FIFO 57 and the display data read from the RAM 61 are overlapped and mixed display is performed. R
The AMDAC control circuit 61 uses the pallet 39 for the CRT.
8-bit data (P7-
0) is converted to RGB 6-bit data. DAC47
Converts the video data or display data output from the multiplexer 41 into RGB analog signals.

In this embodiment, the expanded moving image data output from the video decoder 19 or the system bus 13 can be vertically or horizontally enlarged or reduced and displayed at any position on the screen. Video data is, for example, 360x24
The image data has 0 dots and 60 frames / s. The data width is 16 bits and 65,536 colors can be displayed.
Reduction / enlargement is done in units of 1/64 vertically and horizontally, with a maximum of 10
It can be displayed in a range of up to 24x512 dots.

The moving picture data output start position from the video decoder is vertically synchronized with the number of dot clocks (DCLK) corresponding to the start X-direction offset set in the video decoder from the trailing edge of the moving picture data horizontal synchronizing signal (LPM). The signal (FPM) is defined by the number of dot clocks corresponding to the offset in the start Y direction from the falling edge of the signal (FPM), and is output only while the signal (MVDE) indicating the moving image data superimposing period is enabled.

The moving image data is written in the frame buffer 25. The video D is read according to the area to be displayed from the frame buffer (this is defined by the moving picture control register 51), and is combined with the display data from the video memory.
Input to AC. As a method of writing to the frame buffer 25, there are a method of directly writing by the CPU and a method of writing the output from the video decoder.

The moving image data read from the video decoder is performed in synchronization with the dot clock. As the dot clock, a clock obtained by dividing the memory clock by 8 (60 frames / s) or 16 (30 frames / s) is used. The memory access to the frame buffer 25 is one pixel access with 16 bits. The display size of the moving image data is determined by the start X direction / start Y direction register and the size X / size Y register and is written in the frame buffer 25. The frame buffer 25 is not written while the signal (MVDE) indicating the moving image data overlapping period is disabled. Shows the display area when the MVDE is in output mode. By stopping the writing to the frame buffer 25, the moving image display can be stopped without reading the moving image data from the video decoder.

The moving image data output from the video decoder is 24 bits (8 bits for each RGB), and the data to be written in the frame buffer 25 is 16 bits. In this case, the upper 5 bits are used for Red data and Blue data, and the upper 6 bits are used for Green data. FIG. 8 shows the structure of moving image data.

Frame buffer 2 for storing moving image data
5 uses 1350K bits (360x240x16 bits) of the video memory (256Kx16) 67 shown in Fig. 5. FIG. 9 shows the memory configuration of the frame buffer 25.

In order to display the moving picture data in real time, the moving picture data from the video decoder or the system bus is written in the frame buffer 25 as it is, and the frame buffer 25 is displayed within the time for displaying the screen (VGA).
It is necessary to read the moving image data of 360 x 240 dots x 16 bits / pixel. The moving image data read from the frame buffer 25 is performed in line units for the reduction processing.

Of the one-line display time (horizontal period), the time excluding the moving picture read time (360 dots × 16 bits) and the refresh time is assigned to the writing of the moving picture data.

In the moving picture data write, the moving picture data from the video decoder is written into a write FIFO (8 dots: 8 × 1).
6 dots) (described later), and when the write FIFO is full while the moving image data is being read from the frame buffer 25, the data is written to the frame buffer 25.
The writing is completed in the shortest two screens (VGA) for displaying the moving image data from the video decoder without interruption.
Figure 10 shows video data read / write (30 frames /
The timing of (s) is shown.

In moving image data reading, data for each line is stored in a read FIFO (360 dots: 360 × 16 bits) (described later). The range of moving image data to be displayed is defined by the horizontal / vertical display start register and the horizontal / vertical display end register, and is displayed in the determined overlapping range. To reduce or expand video data,
This is performed in units of 1/64 of moving image data output from the video decoder or the system bus independently in the horizontal and vertical directions. Horizontal / vertical reduction / enlargement scales are set in the horizontal and vertical scale registers. If the range to be displayed is smaller than the range of moving image data in the moving image data memory, it is reduced, and if it is large, it is enlarged.

In order to reduce the display range, a certain display dot in the horizontal direction and a certain display line in the vertical direction are thinned out and output with respect to the read and stored data of the read FIFO.
FIG. 11 shows a conceptual diagram of moving image data read in the reduction processing.

Similarly, to expand the display range, a certain display dot is inserted in the horizontal direction and a certain display line is inserted in the vertical direction. As the data insertion method, a method of simply rescanning the immediately preceding data and a method of calculating the halftone of the preceding and following data and inserting the data are inserted. FIG. 12 shows a conceptual diagram of halftone insertion in the enlargement processing. It may be displayed like a stripe depending on the difference in data before and after, and a smooth change can be realized by inserting an intermediate gradation. The halftone insertion mode is set by setting bit 1 of the moving image mode register.

Superimposition of moving image data is performed within a range determined by a combination of a window and a color key area. Which range is to be superimposed and displayed is selected by bit 5-2 of the moving image mode register. The window is horizontal /
Defined by vertical region start register and horizontal / vertical end register. The color key area indicates a case where the setting value of the color comparison register is compared with the color data (color lookup table selection) and all the bits match. FIG. 13 shows a conceptual diagram showing the position of superposition.
If the range determined above does not match the display range determined by the horizontal display start / end register and the vertical display start / end register, the superposition at that location is ignored. The start position of the moving image data is determined by the start address register value.

The moving image data can be panned in the horizontal and vertical directions. Set the column and row addresses required for panning in the horizontal panning and vertical panning registers.

The 18-bit RGB data output from the color look-up table of the video DAC and the 16-bit moving image data read from the frame buffer are superimposed on each other by converting the RGB of the moving image data into the MS of the RGB data.
Perform according to B. "0" is inserted in the least significant bit of the R data and B data of the moving image data. R in Figure 14
The conceptual diagram of mixing of GB data and moving image data is shown.

The following is a list of moving picture control registers.

1. Movie mode register D7: Movie data input 0: Decoder 1: CPU D6: Still movie display 0: No still movie 1: Still image D5-D2: Overlay range 0: VGA 1: Movie data VGA screen and movie data are displayed Select a range.

OVL3 color key area, window (F3) OVL2 color key area, window outside (F2) OVL1 color key area outside, window (F1) OVL0 color key area outside, window outside (F0) D1: intermediate Gradation insertion 0: Impossible 1: Acceptable D0: Display enable 0: Impossible 1: Acceptable 2. Start X direction register D7-D0: Video start X direction Indicates the position in the X direction at which video data output is started from the video decoder, and is the number of dot clocks (DCLK) counted from the trailing edge of the video data horizontal synchronization signal (LPM). 0
Set the range of -359. Set the same value as the offset in the start X direction set in the video decoder.

3. Start Y direction register D7-D0: Video start Y direction Indicates the position in the Y direction at which video data output is started from the video decoder, and is the horizontal sync signal (LPH) counted from the fall of the video data vertical sync signal (FPM). 0-23
A range of 9 is set. Set the same value as the start Y-direction offset set in the video decoder.

4. Size X register D7-D0: Moving image display width X direction The range of 0-719 is set by the number of dot clocks (DCLK) counted from the trailing edge of the moving image data horizontal synchronization signal (LPM). The display size defined by the size X and size Y registers must not exceed the image size decoded by the video decoder.

5. Size Y register D7-D0: Y direction of moving image display width The range of 0 to 479 is set by the dot clock (DCLK) counted from the trailing edge of the moving image data vertical synchronizing signal (FPM).

6. Horizontal display start register D7-D0: Horizontal display start Sets the horizontal display start. Display in the range defined by the horizontal display start / end register and vertical display start / end register. The set value must be smaller than the value of the horizontal display end register in the range of 0-1023 by the number of pixel clocks from the fall of the horizontal synchronizing signal (LPC).

7. Horizontal display end register D7-D0: Horizontal display end Set the horizontal display end. The setting value is in the range of 0-1023 from the falling edge of the horizontal sync signal (LPC) by the number of pixel clocks.

8. Vertical display start register D7-D0: Vertical display start Set the vertical display start. The set value must be smaller than the value of the vertical display end register in the range of 0-511, which is the number of pixel clocks from the fall of the vertical synchronizing signal (FPC).

9. Vertical display end register D7-D0: Vertical display end Set the vertical end that can be displayed. The set value is set within the range of 0 to 511, which is the number of pixel clocks from the fall of the vertical synchronization signal (FPC).

10. Start address register (High) D7: Start X direction bit 8 D6: Size X bit 9 D5: Size X bit 8 D4: Size Y bit 8 D3: Horizontal total dot number 9 D2: Horizontal total dot number Bit 8 D1: Vertical total dot number bit 8 D0: Display start address Set the linear address (16 bits) of the video data frame buffer.

11. Start address register (Middle) D7-D0: Display start address Set the linear address of the video data frame buffer.

12. Start address register (Low) D7-D0: Display start address Set the linear address of the video data frame buffer.

13. Horizontal area start register D7-D0: Horizontal area start register Set the horizontal start of the window. Display in the range defined by the horizontal start / end register and vertical start / end register. The set value must be smaller than the value of the horizontal area end register in the range of 0-1023 by the number of pixel clocks from the fall of the horizontal synchronizing signal (LPC).

14. Horizontal area end register D7-D0: Horizontal area end Set the horizontal end of the window. The setting value is
The number of pixel clocks is set to the range of 0-1023 from the fall of the horizontal synchronization signal (LPC).

15. Vertical area start register D7-D0: Vertical area start register Set the vertical start of the window. The setting value is
It must be smaller than the value of the vertical area end register in the range of 0-511 by the number of pixel clocks from the falling edge of the vertical synchronization signal (FPC).

16. Vertical area end register D7-D0: Vertical area end Set the vertical end of the window. The setting value is
The range is 0 to 511, which is the number of pixel clocks from the fall of the vertical synchronization signal (FPC).

17. Overflow register 0 D7-D6: Not used D5: Horizontal display start bit 9 D4: Horizontal display start bit 8 D3: Horizontal display end bit 9 D2: Horizontal display end bit 8 D1: Vertical display start bit 8 D0 : Vertical display end bit 8 18. Overflow register 1 D7: Not used D6: Horizontal panning bit 8 D5: Horizontal area start bit 9 D4: Horizontal area start bit 8 D3: Horizontal area end bit 9 D2: Horizontal area end bit 8 D1: Vertical area Start bit 8 D0: Vertical area end bit 8 19. Horizontal scale register However, the zoomed display area is the maximum display area (1024x
If it exceeds 512), the setting becomes invalid.

D5-D0: Horizontal scale Set horizontal scale of reduction / enlargement / 64 dots for moving image data stored in the frame buffer. The setting value is in the range of 1-63. When 0 is set, and when 1-31 is set at a zoom ratio of 2, 4, or 8 times,
Do not reduce / enlarge. In the case of enlargement, the magnification is set in combination with HZ1-0. HZ1-0 HSL5-0 (D5-D0) Magnification Unit X X 0 1 -0 0 X 1 -0 0 1-63 1 / 64-63 / 64 1/64 0 1 32-63 1-2 1-2 1/32 1 0 32-63 2-4 times 1/16 1 1 32-63 4-8 times 1/8 20. Vertical scale register However, the zoomed display area is the maximum display area (1024x
If it exceeds 512), the setting becomes invalid.

D5-D0: Vertical scale Scale for vertical / downscale / 64 lines is set for the moving image data stored in the moving image data memory. The setting value is in the range of 1-63. When 0 is set, and when 1-31 is set at a zoom magnification of 2, 4, or 8, no reduction / enlargement is performed.

21. Color comparison register D7-D0: Color comparison color data (color lookup table selection) and C
Comparison with MP7-0 (D7-D0) is performed. It is defined as a color key area when all bits are equal.

22. Color mask register D7-D0: Valid / invalid of color data 0: Valid
1: Invalid When valid, the color data value is compared with the color comparison register value. When invalid, the comparison result is the same regardless of the value of the color data.

23. Horizontal panning register D7-D0: Horizontal panning column address Set in the range of 0-359.

24. Vertical panning register D7-D0: Vertical panning column address Set in the range of 0-239.

25. Horizontal total register D7-D0: Number of horizontal total dots Video data horizontal sync signal (L
PM) cycle. When the moving image data is continuously read from the video decoder, the moving image data display width X direction size (size X register value-start X register value: 0 to 359) is set. When this value is smaller than the size of the moving image data display width in the X direction, the remaining data is ignored and the data of the next line is read at the trailing edge of the next moving image data horizontal synchronizing signal (LPM).

26. Vertical total register D7-D0: Vertical total number of dots Video data vertical sync signal (F
PM) cycle. When moving image data is continuously read from the video decoder, the moving image data display width in the Y direction size (size Y register value-start Y register value: 0 to 239) is set. When this value is smaller than the size of the moving image data display width in the Y direction, the remaining data is ignored and the next frame data is read at the trailing edge of the next moving image data vertical synchronization signal (FPM).

27. General control register D7-D3: Unused (= "0") D2: Video display enable signal 0: Input 1: Output D1: Vertical sync polarity 0: Positive polarity 1: Negative polarity D0: Horizontal synchronization polarity 0: Positive polarity 1 Negative polarity FIG. 15 is a circuit diagram showing a control circuit for receiving moving image data from the video decoder and writing it in the moving image data frame buffer 25.

According to this embodiment, the moving picture data is received from the video decoder on the basis of the parameter register group indicating the size and start position of the moving picture data, and the speed and the moving picture received from the video decoder by the write FIFO 53 temporarily stored. Adjust the writing speed to the data frame buffer and write to the video data frame buffer in real time. Further, it has a read-out FIFO 57 for adjusting the speed of reading from the moving picture data frame buffer 25 and the display speed and enlarging / reducing the data read out from the moving picture data frame buffer 25. Display video data.

In FIG. 15, a register group 71 holds moving image data from video data, and a counter 73 described later.
The count values from are stored in order. Counter 73
Selects a register that should hold moving image data from the register group 71. The counter 75 sequentially selects the values of the register group 71 by the multiplexer 77.
The frequency divider circuit 79 receives the memory clock as an input and outputs a control clock of frequency division by 2 and frequency division by 16. The multiplexer 77 selects from the register group 71 according to the output value of the counter 75. The moving picture control register 51 holds each format of moving picture data. The area control circuit 49 is the moving picture control register 5
The display area of the moving image data is controlled according to the value of 1. The memory control circuit 65 controls the address and the like of the moving picture data frame buffer 25 according to the value of the moving picture control register 51. The frame buffer memory 25 has a frame buffer function of storing moving image data.

FIG. 16 shows a frame buffer 2 for moving image data.
5 is a circuit diagram showing a control circuit for reading out data from No. 5 and performing enlargement / reduction processing. FIG.

The register group 81 holds the data from the moving image data frame buffer 25, and sequentially stores the data by the counter 83. The counter 83 selects a register holding data from the register group 81. The counter 85 sequentially selects the values of the register group 81 by the multiplexer 87 in order to output them. The multiplexer 87 selects from the register group 81 according to the value of the counter 85. The enlargement / reduction circuit 55 performs enlargement / reduction processing according to the value of the moving image control register 51. The moving picture control register 51 holds each format of moving picture data. The superposition control circuit 59 superimposes the output of the multiplexer 87 and the VGA video output.

17A to 17D are waveform charts showing the operation of each control circuit shown in FIG. 15 and 16. FIG. 17A is a waveform chart of the write FIFO, FIG. 17B is a waveform chart at the time of memory write, and FIG. FIG. 17D is a waveform diagram of the read FIFO, and FIG. 17D is a waveform diagram of the read FIFO.

Now, the moving picture data format is 16 bits / pixel, horizontal x vertical resolution x frequency is 360 dots x 2
A case of 40 dots × 30 Hz will be described.

The register group 71 is composed of 16 bits × 8 latches and can hold moving image data for 8 pixels. When the video data from the video decoder comes in,
The octal counter 73 counts up for each pixel.
The clock of the counter is the memory clock divided by 16. The area control circuit 49 determines the area to be displayed based on the size of the moving picture data set in the moving picture control register 51 and the value of the start position, and outputs an enable signal for the counter. According to this counter value, the moving image data is sequentially held in the register group 71. When all eight register groups 71 are full, the register groups 71 sequentially output the data in order to write to the frame buffer 25 for moving image data using the multiplexer 77. Therefore, the octal counter 75 is used. The clock of the counter 75 is a memory clock divided by 2, and operates at a speed eight times that of the counter 73. Writing to the frame buffer 25 is performed with two memory clocks, and the timing is generated by the memory control circuit 65. Therefore, the speed of fetching from the register group 71 and the frame buffer 25
The same writing speed is used, and when 8 pixels are held in the register group 71 from the video decoder, 8 pixels of moving image data is stored in the frame buffer 2.
Will be sent to 5.

At this point, the moving image data can be stored in the frame buffer 25 without impairing the moving speed.

Next, the data stored in the frame buffer 25 is read in the space for writing the moving image data in the frame buffer 25. The read control is the memory control circuit 65.
Done by. Writing to the frame buffer 25 is performed when the memory write in FIG. 17B is "H", and therefore can be used as the read time at other times. The read time is when the memory read shown in FIG. 17C is "H". As shown in FIGS. 17A-17D, the moving image data is 5
While writing 6 dots, 360 dots of moving image data are read out. The data read at this time is held in the register group 81. Register group 81 is 16 bits x
There are 360 units. That is, it is 1 for enlargement / reduction processing.
It is prepared for the line. The holding in the register group 81 is sequentially performed by the 360-ary counter 83. This counter clock is a memory clock divided by two. The register group 81 is filled up by one line, and sequentially output using the multiplexer 87 for display. For this purpose, a 360-ary counter 85 is used.
The clock of the counter 85 uses the pixel clock for display. Further, in order to perform the enlargement / reduction processing, the enlargement / reduction processing circuit 55 outputs the enable signal of the counter 85. The enlarging / reducing processing circuit 55 stops the counter in the case of the enlarging processing based on the horizontal and vertical scale ratios set in the moving image control register 51 and performs a plurality of scans, and in the case of the reducing processing, Scanning is performed by skipping the counter and thinning it out. The moving image data output from the multiplexer 87 is combined with the VGA video output by the superposition control circuit 59. The combined video output becomes an input of the video DAC, is converted into analog data, and is input to an external display device such as a CRT.

FIG. 21 is a detailed block diagram of the area control circuit 49 shown in FIG. 29A to 29H are waveform charts showing the timing of the vertical / horizontal display area.

The horizontal total register 1 shown in FIG.
47, the vertical total register 149, the start X direction register 151, the size X register 153, the start Y direction register 155, and the size Y register 157 are a part of the moving image control registers described above. The horizontal total and vertical total values are the horizontal / vertical counter 159.
(See Band 22G in FIG. 22) to generate a moving image data horizontal synchronization signal LPM (see FIG. 22E) and a moving image data vertical synchronization signal FPM (see FIG. 22A). The video data horizontal synchronizing signal LPM is supplied to the comparator 161.
The moving picture data vertical synchronization signal FPM is supplied to the comparator 163. The start X value and the size X value are further supplied to the comparator 161. The comparator 161 defines the horizontal display area of the moving image data according to these values. The comparator 161 outputs the value of the area X (see FIG. 22H) to AN.
The data is supplied to the enable terminal EN of the write FIFO 53 via the D gate 165.

The moving picture data vertical synchronizing signal FPM output from the horizontal / vertical counter 159 is supplied to the comparator 163. The start Y direction value and the size Y value are further supplied to the comparator 163. The comparator 163 defines the display area in the vertical direction of the moving image data according to these values. The comparator 163 sets the value of the area Y (see FIG. 22C) to A
It is supplied to the enable terminal EN of the write FIFO 53 via the ND gate 165. The frequency of the memory clock signal is divided by 2 by the frequency dividing circuit 167 to obtain the read clock signal RC.
It is supplied to the write FIFO 53 as K. further,
The memory clock signal is divided by 8 or 1 by the divider circuit.
The frequency is divided by 6, and switched by the multiplexer 169 to generate the dot clock signal DCLK (see FIG. 22D), which is the horizontal / vertical counter 159 and the comparator 161,
It is supplied to the write FIFO 53 as a write clock signal as well as being supplied to 163. F for light
The IFO 53 synchronizes with the write clock signal WCK,
16 dots / pixel (MR4-0, MG5-0,
MB4-0) (refer to FIG. 22F) is stored,
16 dots / p in synchronization with the read clock signal RCK
The video data (MP15-0) of the pixel is output. The write FIFO 53 outputs a full flag when moving image data is stored in full, and outputs an empty flag when moving image data is output and becomes empty.

FIG. 23 is a detailed block diagram of the enlargement / reduction processing circuit 55 shown in FIG. In FIG. 23, the arithmetic unit 1
Reference numeral 71 calculates the basic dot number of 64 dots in the reduction processing and the horizontal display dot number set in the horizontal scale register 173. In the horizontal scale register 173, how many dots of 64 dots are desired to be displayed is set. An initial value "1" is applied to the D input terminal of the 32-bit counter 175, and counting is performed as shown in FIG. 25B in synchronization with the pixel clock signal shown in FIG. 25A.
The 32-ary counter 175 is a 360-ary counter 85 described later.
Generate the load signal of. The output of the arithmetic unit 171 is -1 by the -1 circuit 172 and supplied to the A input terminal of the comparator 171. Further, the B input terminal of the comparator 171 has 3
The Q output from the binary counter 175 is applied. The comparator 177 compares the inputs of A and B, and when they match, outputs the value to the multiplexer 179. The comparator 181 is A
The horizontal scale value applied to the input is compared with the constant "32". The comparator 181 determines whether the reduction ratio is 1/2 or less. This is to obtain the data to be displayed because the data to be displayed is smaller than the data to be omitted when the reduction ratio is 1/2 or less. The details will be described later.

When A> B, the comparator 181 compares the comparator 1
A selection signal is output so that the multiplexer 179 selects the output of 77, otherwise "1". The output from the multiplexer 179 is 360 as a load signal.
It is supplied to the advance counter 85 (counter 85 shown in FIG. 16). The calculator 185 divides 64 dots by the number of horizontal display dots. The calculator 187 adds the output of the 360-ary counter 85 to the calculation result from the calculator 185. The output of the calculator 187 is supplied to the D input terminal of the 360-ary counter 85. The 360-base counter 85 counts as shown in FIG. 25C, and the multiplexer 87 (see FIG.
The selection condition of 6) is output. The calculator 189 calculates (A * B-1) the output (A input) from the -1 circuit 172 and the zoom magnification (B input) and supplies the result to the comparator 191.
The comparator 191 outputs the Q output from the cowtan 175 and the calculator 1
When the output is compared with the output from 89 and a match is found, the result shown in FIG.
The zoom signal indicated by D is output to the enlargement control circuit 193.
The enlargement control circuit 193 performs enlargement control in response to the zoom signal, and supplies the enable signal shown in FIG. 25E to the counter 85.

FIG. 24 is a detailed circuit diagram of the expansion control circuit shown in FIG. In FIG. 24, the pixel clock is set to 2
The frequency divided by 4, the frequency divided by 4, and the frequency divided by 8 are supplied to AND gates 195, 197, and 199, respectively. Furthermore, the 7-bit value of the horizontal scale register is AND gates 195, 1
97,199. In this embodiment, when bits 6 and 7 are "01", it is 1-2 times, and when it is "10", 2-4.
If the value is “11”, then the magnification will be 4 to 8 times and bit 0
From the value of 6-bit 5 to the value of 32-63 (1-2
1/64 unit is defined for double, 1/16 unit for 2-4, and 1/8 unit for 4-8. Each A
The outputs of the ND gates 195, 197, and 199 are ORed by the OR gate 201 to generate the expansion enable signal. The OR gate 203 takes the OR of the enlargement enable signal and the zoom signal to generate the ENABLE signal.

Conventionally, when displaying moving image data or still image data in an area in which the horizontal and vertical directions are reduced, certain dots are thinned out in the horizontal direction according to the scale value in the horizontal direction, and vertical directions are set in the vertical direction. A line is thinned according to the scale value. As a method of thinning out,
It was standard that the number of dots in the horizontal direction was divided by a value obtained by thinning the number of dots to be displayed from the number of dots in the horizontal direction and the value was -1. (Refer to FIG. 18A and 18B) However, the above method is effective when the reduction ratio is 1 to 1/2, but when the reduction ratio is reduced to 1/2 or less, the thinning number becomes continuous, so There is a problem that another means for controlling is required, the number of circuits is increased, and if the number of consecutive times is not properly controlled, a specific dot is lost and display quality is deteriorated.

In this embodiment, a display controller for reducing and displaying the data from the frame buffer at an arbitrary screen position has a reducing means which is divided according to the reduction ratio, and performs a linear thinning method to display quality. A good display controller can be obtained.

In this embodiment, it is necessary to omit certain dots in order to obtain the data to be displayed by being reduced from the original horizontal display data. The dropout rate is calculated from the output of the parameter register that stores the number of horizontal display dots (horizontal scale), and when the count value matches the counter value, the dropout is performed periodically. Output an enable signal to drop it,
This becomes the load enable of the line counter for determining the memory data selection condition. The memory data is held by a plurality of latches, a dot to be displayed (not missing) is selected by a multiplexer for the number of lines, and is sent to a video output circuit. In the circuit which determines the ratio of the dots to be dropped and generates the load enable signal of the line counter, the reduction ratio is divided into cases to indicate the optimal drop ratio, and the display dots are always shown at equal intervals.

In FIG. 19, the moving picture control register 51 sets the number of display dots in the horizontal direction (horizontal scale value). The arithmetic unit 91 executes (A ÷ (A−B)) − 1.
The arithmetic unit 93 executes A ÷ B. The arithmetic unit 95 executes A + B. The comparator 99 is effective when A = B.
(The comparator 99 outputs a logic "1" when A = B, otherwise outputs a logic "0"). The comparator 101 is effective when A> B. (When A> B, the comparator 101 outputs logic “1”, otherwise, outputs logic “0”) Counter 10
7 generates a load signal for the counter 109. The multiplexer 105 selects the output of the comparator 99 when the output of the comparator 101 is "0", and selects the constant "1" when it is "1". The counter 103 is set with a constant "1" in response to the load signal LD, and counts in synchronization with the pixel clock signal. The counter 107 is the multiplexer 1
The selection condition of 09 is output. The register 111 holds memory data. The multiplexer 109 is the register 11
Select a value of 1.

Next, the operation of the above configuration will be described. A case where the size of the data stored in the frame buffer is 360 dots in the horizontal direction and the reduction rates are 1/4 and 3/4 will be described. The reduction processing in the horizontal direction is performed in units of 64 dots. Therefore, when the reduction ratio is 1/4, the scale value indicating the number of dots to be displayed in the horizontal direction is set to 16 dots. If the reduction ratio is 1/2 or less, the amount of data to be displayed is smaller than the amount of data to be omitted, so the data to be displayed is obtained.

First, the number of horizontal display dots (= 16) is output from the moving picture control register 51, and the arithmetic unit 93 outputs 64 ÷
16 = 4 is output. In addition, A =
16 and B = 32 are compared, and the multiplexer 105 selects "1" from this result. Therefore, counter 1
07 is always in the load enable state, and the adder 95 loads the output value of itself plus the output value "4" of the computing unit 93. As a result, the output values of the counter 107 are 0, 4, 8, 12 ,. ． ． It becomes 60, and 0, 4, 8, 1 of the memory data latched by the register 111
2 ,. ． ． The 60th data is sequentially selected by the multiplexer 109 and sent to the video output circuit.

When the reduction ratio is 3/4, the number of dots in the horizontal direction (= 48) is output from the moving picture control register 51, and the arithmetic unit 91 calculates 64 ÷ (64−48) −1 = 3, and The arithmetic unit 93 calculates 64 ÷ 48 = 1. The output value of the counter 103 and the output value of the arithmetic unit 91 (=
3) is compared by the comparator 99, and if they match, an enable signal is generated. The comparator 101 compares A = 48 and B = 32, and the multiplexer 105 selects the output of the comparator 99. Multiplexer 105
Periodically outputs 0, 0, 1, 0, 0, 1 and the adder 9
A value obtained by adding "1" indicated by the calculator 93 to the output value of itself is loaded by 5. As a result, the output values of the counter 107 are 0, 1, 2, 4, 5, 6, 8 ,. ． ． 62, which is memory data 0, 1, 2, 4, 5, 6, 8 ,. ． ． The 62nd data is sequentially selected by the multiplexer 11 and sent to the video output circuit.

Next, a method for easily superposing and displaying data having a moving image standard such as MPEG in the VGA display controller in accordance with a display control method such as VGA will be described.

In this embodiment, each RGB has 6 bits × 25.
From each value of the 6 color look-up tables, 256 colors (8 bits) are identified using a certain formula, and a color identification register that stores the value, 24 dots per pixel indicated by 8 bits for each RGB It has a conversion table for converting the moving image data of 18 bits into 1-pixel data represented by 6 bits, and a comparator for identifying a color from the 18-bit data using the formula and comparing it with the color identification register. , The closest value is selected by comparison, and the address of the color identification register is given to obtain 8-bit data. As a result, the moving image data is written and read as 8-bit data in the moving image data storage frame buffer. The read data is combined with the VGA display data and becomes the selected address (8 bits) of the color lookup table.

FIG. 20 is a circuit diagram for memory access of moving image data. In addition, in FIG. 20, a portion surrounded by a broken line is composed of one chip of a highly integrated semiconductor element. In FIG. 20, the conversion table 121 is composed of 6-bit × 256 registers, and RGB 8-bit moving image data output from the MPEG video decoder is converted into RGB 6-bit data (CR5-0, CG5).
-0, CB5-0) and output to the color identification circuit 123. Each RGB 8-bit data from the MPEG decoder is converted to 6-bit data because the RGB output from the VGA display controller is 6-bit each.
In order to superimpose the display data of each RGB 6 bits output from the display controller and the image data from the MPEG decoder, the image data of each RGB 8 bits is RG.
B Convert to image data of 6 bits each. Conversion table 1
For details of No. 21, see Japanese Patent Application No. 4-1 by the same inventor
No. 47698. The color lookup table 125 is provided in the DRAM 21 shown in FIG.
Each of RGB has 6 bits x 256 registers, and 8-bit color data (S
A7-0) is converted into 6-bit RGB values and output to the color identification circuit 123. The color identification circuit 123 converts the 6-bit RGB image data output from the conversion table 121 into 8-bit color identification data (MC7-0), and also outputs the 6-bit RGB data output from the color lookup table 125. The display data is converted into 8-bit color identification data (DC7-0). In the color identification circuit 123, the RGB 6-bit total 18 bits output from the conversion table 121 or the RGB 6-bit total 18 bits from the color lookup table 125 are 8-bit data (MC7-0) or (DC7-).
The conversion to 0) is because the memory capacity becomes huge when stored as 18-bit color data and it takes time to access the memory. The color identification register 127 is composed of 8 bits × 256 pieces, and 8-bit color identification data (D) obtained by converting the 6-bit RGB value output from the color lookup table 125 by the color identification circuit 123.
C7-0) is retained. The comparator 129 uses the 8-bit color identification data (MC7-0) obtained by converting the RGB form moving image data by the color identification circuit 123, and the RGB 6-bit values output from the color lookup table 125 by the color identification circuit. Converted 8-bit data (DC
7-0) and outputs the address of the color lookup table having the closest value. 2 according to VGA specifications
Since 16 colors out of 56 colors can be displayed, display data of 256 different colors is not stored in the color lookup table. Actually, since 256 colors are divided into 16 equal values, the address of the color lookup table having the value closest to the 16 colors is output. The memory control circuit 131 controls read access and write access to the memory. The overlay control circuit 133 controls overlay of the moving image data and the VGA display data supplied via the memory control circuit 131. The overlay method is "windowing" or "c".
A known method such as “color keying” can be used. For details of the method, see, for example, Ch.
ips and Technologies, In
c. PC Video Data Sheet "82
C9001A PC Video ".

Video DAC (color lookup table and DA set when setting up the display subsystem)
256 colors are identified from each value of the color lookup table in the combination of C) by using a certain formula, and the values are stored in the color identification register (256) 127.

RGB is output from the MPEG video decoder by converting a 24-bit / 1-pixel moving image data represented by 8 bits for each RGB into 6 bits by using a conversion table composed of 6 bits × 256. 6 each
Convert to data of 18 bits / pixel indicated by bits.

The data represented by each 6 bits of RGB is discriminated into 256 colors by using the above formula, and compared with the value of the color discrimination register 127, and the address (8 Give a bit). Therefore, the data represented by 6 bits for each of RGB is 8-bit data. The 8-bit data is stored in the frame buffer 25 prepared for storing the moving image data. Similarly, when reading out, it is read out as 8-bit data, and V
It is combined with the GA display data (8 bits) and used as the selection address of the color lookup table.

Therefore, when the moving image data is displayed, the color of the color look-up table closest to the color identified by the above formula is selected.

According to this embodiment, if moving image data in which one pixel is represented by a large number of bits is directly accessed to the memory, a huge frame buffer for storage must be prepared, and the memory access method becomes complicated. By adjusting the number of display colors and the memory access method, the frame buffer can be configured with a small number, resulting in low cost, and the easy memory access method can easily support a standard VGA display controller.

26 and 27 are detailed circuits of the superposition control circuit 133 shown in FIG. FIG. 26 is a circuit for generating pixel data selection conditions, and FIG. 27 is a circuit for superimposing moving image data.

In FIG. 26, the comparator 205 compares the color data (PA7-0) (which becomes an address for selecting the color lookup table shown in FIG. 20) with the color comparison register 207 of the moving picture control registers. To do. It is defined as a color key area when all bits are equal. The OR gate 207 takes the OR of the comparison result from the comparator 205 and the color mask register 209. The color mask register 209 indicates whether the color data is valid or invalid. When enabled, the color data value is compared to the color comparison register value. When invalid, the comparison result is the same regardless of the value of the color data. OR gate 207
Outputs a color key signal of "0" (mismatch) or "1" (match).

The comparator 211 compares the horizontal area start register 213, the horizontal area end register 215, and the horizontal counter value, and ANDs the coincidence or non-coincidence signal.
Output to the gate 219. Further, the comparator 221 compares the vertical area start register 223, the vertical area end register 225, and the vertical counter value, and outputs a match or mismatch signal to the AND gate 219. AN
The D gate outputs a window signal of "0" or "1". The gate 227 has a color key signal of "0" and wi
When the window signal is "0", the signal indicating the F0 area shown in FIG. 13 is output, and when the color key signal is "0", the window is displayed.
When the ow signal is "1", a signal indicating the F1 area is output, and the color key signal is "1" and the window signal is "1".
When the color key signal is "1" and the window signal is "1", a signal indicating the F2 area is output when 0 "and a signal indicating the F3 area is output. AND gate 229 AND with the video mode register 233 The moving image mode register 233 indicates the overlapping range, that is, the range for displaying the VGA screen and the moving image data, that is, when bit 2 of the moving image mode register 233 is “1”, outside the color key area and outside the window. Indicates the (F0) area, and bit 3
When is "1", inside the window outside the color key area (F
1) area, and when bit 4 is "1", it indicates an outside window (F2) area in the color key area, and bit 5 is "1".
1 "indicates the window (F3) area within the color key area. The OR gate 231 takes the OR of the output from the AND gate 229 and outputs the signal PDSEL (0: VGA display data, 1 indicating pixel data selection condition). : Video data) is output.

In FIG. 26, the comparator 235 includes a horizontal display start register 237 and a horizontal display end register 23.
9 and the horizontal counter value are compared, and if they match, the display X signal is output. The comparator 241 includes a vertical display start register 243 and a vertical display end register 24.
5 and the vertical counter are compared, and when they match, the display Y signal is output. The OR gate 251 takes the OR of the outputs from the comparators 235 and 241 and supplies it to the AND gate 253. Video data from the video data register 259 is further supplied to the AND gate 253. As a result, the range of data to be displayed in the horizontal direction and the vertical direction is defined, and the moving image data in the range is supplied to the multiplexer 257. The VGA display data is further supplied to the multiplexer 257, and the moving image data or the VGA display data is selectively output according to the pixel data selection condition generated by the circuit shown in FIG.

Note that in FIG. 2, the YU is placed on the MPEG board.
A V / RGB converter is provided, and the computer main body side is configured to store image data in a frame buffer in R, G, B forms. May be configured to store YUV form image data. Hereinafter, this example will be described with reference to FIG. Note that the same parts as those in FIG. In FIG. 28, the graphics subsystem built in the computer main body is a display subsystem for displaying graphics software, and for example, VGA Video Graphics Ar.
Rays). The graphics subsystem connected to the main body of the portable computer via an expansion connector is a display subsystem for displaying images called multimedia, and is, for example, DVI (Int.
(registered trademark of el Corporation) (Digi
It is composed of a tal video interactive board.

On the DVI board, the PB chip 1 and the single port dynamic random access memory (D
RAM) 33 is mounted. The PB chip 141 has a function of expanding image compressed data supplied via the CPU bus 9. The PB chip 141 is, for example, 82750PB PIXEL PRO manufactured by Intel Corp.
CESSOR can be applied. For a detailed description of this PB chip 1, see "DVI" issued by Intel Corporation.
Technology i750 VideoProc
essor Technical Specifica
"tions". PB chip 141 is C
While expanding the image (moving image / still image) compressed data received via the PU bus 9, the DRAM (Dynamic R)
and access memory 3). The image compression data is stored in, for example, a hard disk (not shown) such as a CDROM. The compressed image data is decompressed and output as 32-bit data to a frame buffer 7 provided on the computer main body side through a connector (not shown) provided on the portable computer main body side and a frame buffer write port. For more information about frame buffer 25, see USSN 07 /
906, 834.

Although the Intel PB chip has both compression and decompression functions, the present invention requires only the decompression function, so a dedicated PB chip may be created.

The DRAM 21 stores the calculation result of the microcode and the compressed data. (For details of the calculation results of microcode and compressed data, see "DVI
Technology i750 Video Pr
processor Technical Spec
“Cations”. In this embodiment, the decompressed YUV video data is the frame buffer 2
Written in 5.

The frame buffer 25 has two roles. One is that the display device is a monochrome LCD (Liquid
CRT in the case of Crystal Display)
By reading the display data written in the frame buffer at the timing of, at the timing of the monochrome LCD,
Used to display data on monochrome LCD at CRT timing. Another role is that when the TFT color LCD is used up as a display device, it is not necessary to convert the CRT timing to the LCD timing by using the frame buffer, so the image output from the PB chip is used for this frame buffer. Used as a memory to store decompressed data.

The output of the frame buffer 25 is YUV /
It is connected to the RGB converter 35. YUV / RG
The output of the B converter 9 is connected to the multiplexer 11.

The VGA memory 23 is a VRAM for storing display data in the VGA graphic subsystem. Display data is written in the VGA memory 23 by the CPU 1 via the CPU bus 9. The display data stored in the VGA memory 23 is read out via the display read port and output to the palette 39. The palette 39 color-converts the display data and outputs it to the multiplexer 41. The multiplexer 41 outputs the display data from the palette 39 to the DAC 47 when the display device is a CRT, and the YUV / RG when the display device is a color LCD.
The RGB data from the B converter 35 is output to the color LCD gradation circuit 45.

As shown in FIGS. 29 and 30, the DVI window is opened on the VGA display screen to display VGA and DV.
Each display data of I can be mixedly displayed. There are two methods for this mixed display. The first method is
As shown in FIG. 30, VGA display data is displayed together with DVI display data in a 24-bit configuration. This writes VGA display data and DVI display data to the frame buffer 25,
Color LC via conversion circuit 35 and multiplexer 41
Display on D or CRT. However, 16 or 256 colors are sufficient for graphics data, and
We don't even need 24 bits per pixel. The second method is
As shown in FIG. 29, the VGA graphics data is set to 1
4 bits per pixel (16 colors) or 8 bits (2
This is a method of displaying only the image data in a 24-bit structure as a structure of (56 colors). With this configuration, graphic data can be accessed only by 4 bits or 8 bits, and therefore high-speed processing is possible. This is the graphics data of VGA to VGA memory 2
3, the image data in the frame buffer 25 is output to the multiplexer 41 while being output to the multiplexer 41 via the palette 39.
This is a method of outputting to a multiplexer 41 via a V / RGB conversion circuit 35, switching control by the multiplexer 41, and outputting to a color LCD or CRT.

In the embodiment shown in FIG. 2, the expansion circuit 31, the DRAM 21, and the YUV / YUV / on the MPEG board.
Although the RGB converter 35 is provided and the MPEG board is connected to the computer main body through the connector, as shown in FIG. 31, the expansion circuit 31, the DRAM 21,
Alternatively, the YUV / RGB converter 35 may be standardly mounted in the computer main body.

Further, in the embodiment shown in FIG. 28, the PB chip 141 and the DRAM 21 are provided on the DVI board, and the DVI board is connected to the computer main body through the connector. As shown, the PB chip 141 and the DRAM 21 may be standardly mounted in the computer main body.

In the embodiment shown in FIG. 2, the common frame buffer 25 is used to store the MPEG moving picture data and the monochrome LCD display data. However, as shown in FIG. The data storage buffer 143 and the monochrome LCD display data frame buffer 145 may be commonly controlled by the memory control circuit in the VGA chip.

Similarly, in the embodiment shown in FIG. 28, the DVI
Although the storage of the moving image data and the storage of the display data for monochrome LCD are performed using the common frame buffer 25, as shown in FIG. 34, the storage buffer 147 for the DVI moving image data is provided on the DVI board. This DVI
The moving image data storage buffer and the monochrome LCD display data storage frame buffer 145 may be commonly controlled by the memory control circuit in the VGA chip.

Although the TFT color LCD is used in the above-mentioned embodiment, the STN color LCD may be used.

[0122]

According to the present invention, two different display systems, for example, YUV data of MPEG standard and RGB data of VGA standard are display-controlled by a common display circuit. Therefore, the display system is simplified. Furthermore, because of the monochrome LCD, C
It has a frame buffer for converting RT display timing to monochrome LCD display timing.
In the case of the TFT color LCD, the frame buffer is not used because the refresh operation is not required. Therefore, by storing the image data expanded by the expansion circuit in the frame buffer, the monochrome LCD frame memory and the video memory for the image data are configured by a common memory (frame buffer). Therefore, the display system can be further simplified. further,
Since the memory used by the expansion circuit for expansion is composed of DRAM, an inexpensive display system can be obtained.

According to the present invention, the frame buffer is T
Since the FT color LCD and the monochrome LCD are commonly used, the circuit can be simplified. Furthermore, the DB chip that was conventionally provided on the DVI board is eliminated,
Since only the expansion is performed by the DVI board, the display circuit can be shared and the circuit configuration can be simplified. In addition, conventional D
Although the VRAM is provided on the VI board, in the present invention, an inexpensive DRAM is used in place of the expensive VRAM, which contributes to the cost increase of the entire system.

Further, by adopting the writing and reading FIFOs for reading and writing the moving image data, the moving speed of the moving image data can be maintained and a smooth moving image display can be realized. Further, the control circuit having the read-out FIFO makes it possible to enlarge / reduce and superimpose it on the multifunctional VGA video output.

Further, by selecting the dots which are classified according to the reduction ratio, the display dots are displayed at equal intervals, which enables smooth reduction display.

Further, according to the present invention, 256 kinds (8 bits) of colors are identified from each value of each color look-up table of 6 bits each of RGB × 256 color lookup tables, and the color identification for storing the values is performed. Register, a conversion table for converting moving image data of 24 dots / 1 pixel represented by 8 bits each of RGB to data of 18 bits / 1 pixel represented by 6 bits each, and a color from this 18 bit data using the above formula Is provided, and a comparator for comparing with the color identification register is provided. By comparing, the closest value is selected and the address of the color identification register is given to obtain 8-bit data. As a result, the moving image data is written and read as 8-bit data in the moving image data storage frame buffer. The read data is VG
It is combined with the display data of A and becomes the selection address of the color lookup address. If moving image data showing one pixel with many bits is directly accessed to the memory, an enormous storage frame buffer must be prepared, and the memory access method becomes complicated, but it matches the number of VGA display colors and the memory access method. As a result, it can be configured with a small number of frame buffers, resulting in low cost,
Moreover, the standard VGA display controller can be easily supported by an easy memory access method.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire multimedia display control system of the present invention;

2 is a block diagram showing a first embodiment of the multimedia display control system shown in FIG. 1;

3 is a conceptual diagram showing mixed display of 4-bit or 8-bit VGA graphic data and 24-bit MPEG moving image data in the embodiment shown in FIG. 2;

FIG. 4 is a diagram illustrating a 24-bit V in the embodiment shown in FIG.
A conceptual diagram showing mixed display of GA graphic data and 24-bit MPEG moving image data;

5 is a detailed block diagram of writing control of moving image data shown in FIG. 2 into a frame buffer and reading control of moving image data from the frame buffer;

FIG. 6 is a waveform chart showing the read timing of moving image data in the vertical direction;

FIG. 7 is a waveform diagram showing the timing of reading moving image data in the horizontal direction;

FIG. 8 is a diagram showing a bit configuration of moving image data;

FIG. 9 is a diagram showing a memory configuration of a frame buffer;

FIG. 10 is a waveform diagram showing the read / write timing of moving image data;

FIG. 11 is a conceptual diagram of moving image data read in reduction processing;

FIG. 12 is a conceptual diagram of halftone insertion in enlargement processing;

FIG. 13 is a conceptual diagram showing the position of superimposition of moving image data and display data;

FIG. 14 is a conceptual diagram of mixing of moving image data and display data;

FIG. 15 is a circuit diagram showing a control circuit for receiving moving image data from a video decoder and writing it in a moving image data frame buffer;

FIG. 16 is a circuit diagram showing a control circuit for reading out data from a moving image data frame buffer and performing enlargement / reduction processing;

17 is a waveform diagram showing the operation of each control circuit shown in FIGS. 15 and 16, FIG. 17A is a waveform diagram of a write FIFO, FIG. 17B is a waveform diagram at the time of memory write, and FIG.
7C shows a waveform diagram at the time of memory read, and FIG. 17D shows a waveform diagram of the read FIFO;

FIG. 18 is a waveform diagram showing an example of thinning in the case of a reduction ratio of 3/4 (horizontal dot number 64, display dot number 48);

FIG. 19 is a circuit diagram showing horizontal reduction processing;

FIG. 20 is a circuit diagram for memory access of moving image data;

21 is a detailed block diagram of the area control circuit 49 shown in FIG. 15;

FIG. 22 is a waveform diagram of each signal shown in FIG. 21;

23 is a detailed block diagram of the enlargement / reduction processing circuit shown in FIG. 16;

FIG. 24 is a block diagram for horizontal enlargement control;

FIG. 25 is a waveform diagram of the signals appearing in FIGS. 23 and 24;

FIG. 26 is a part of the detailed block diagram of the overlay control circuit shown in FIG. 20, showing a circuit for generating pixel data selection conditions;

FIG. 27 is a part of the detailed block diagram of the overlay control circuit shown in FIG. 20, which is a circuit diagram for overlaying moving image data;

FIG. 28 is a block diagram showing another embodiment of the present invention, which is a block diagram showing the configuration when the DVI boat is connected to the computer main body;

29. In the embodiment shown in FIG. 28, 4-bit or 8-bit graphics data and 24-bit D
Conceptual diagram showing mixed display with VI video data;

FIG. 30 is a conceptual diagram showing mixed display of 24-bit graphics data and 24-bit DVI moving image data in the embodiment shown in FIG. 28;

FIG. 31 is a modification of FIG. 2 and is an MPEG shown in FIG.
On-board decompression circuit, DRAM, and YUV / RGB
A block diagram showing an example in which a conversion circuit is standardly mounted in a computer main body;

FIG. 32 is a block diagram showing a modified example of FIG. 28, showing an example in which the decompression circuit on the DVI board and the DRAM are standardly mounted in the computer body;

FIG. 33 shows a VGA with a frame buffer for storing MPEG moving image data and a frame buffer for displaying a monochrome LCD.
Block diagram of common control by memory control circuit in chip;

FIG. 34 is a block diagram in the case of commonly controlling the DVI moving image data storage frame buffer and the monochrome LCD display frame buffer by a memory control circuit in the VGA chip.

[Explanation of symbols]

1 ... CPU, 31 ... Decompression device, 21 ... DRAM, 35 ...
YUV / RGB converter, 23 ... VGA memory, 25
... Frame buffer, 39 ... Palette, 41 ... Multiplexer, 43 ... Monochrome LCD gradation control device, 45 ... Color LCD gradation control device, 47 ... DAC, 49 ... Region control / write FIFO control circuit, 53 ... Write FIFO,
51 ... Movie control register, 55 ... Enlargement / reduction / read FI
FO control circuit, 57 ... Read FIFO, 59 ... Overlay control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G09G 3/20 Z 8729-5G 3/36 7319-5G 5/02 9175-5G 5/40 4232- 5G

Claims (48)

[Claims] 1. A display control system in a portable computer having a flat panel display unit, wherein image data supplied to the portable computer from outside is R (red), G (green), B (blue).
means for receiving in the form of e); used for converting the display timing for the CRT display device into the display timing for the flat panel display,
Frame buffer memory means used for storing the image data; video memory means for storing text data and graphics data; palette means for color conversion of display data output from the video memory means; Selecting means for selectively outputting the image data outputted from the frame buffer means and the display data outputted from the palette means; the flat panel by controlling the gradation of the display data outputted from the selecting means A display control system comprising: a gradation control means for outputting to a display unit; and a D / A converter means for converting the display data output from the selecting means into R, G, B analog signals. . 2. The image data is moving image data (movi).
The display control system according to claim 1, wherein the display control system is an ng picture data). 3. The moving image data is MPEG (Movie).
ng Pcture Experts Group)
The display control system according to claim 2, wherein the display control system is video data. 4. The moving image data is DVI (Digital).
3. The display control system according to claim 2, wherein the display control system is video data. 5. The display control system according to claim 1, wherein the image data is still image data. 6. The display control system according to claim 5, wherein the still image data is JPEG video data. 7. A graphics subsystem (VGA core) for controlling read / write of display data to said video memory means and display data to said frame buffer memory means and read / write of image data, further comprising: The graphic subsystem, the palette means, the selection means, the gradation control means, and the D / A converter means are integrated by a highly integrated semiconductor device.
The display control system according to claim 1, wherein the display control system comprises a chip. 8. The graphics subsystem is VGA
The display control system according to claim 7, which has a (Video Graphics Arrays) standard. 9. The apparatus further comprises means for displaying together 2n (n is a positive integer of 8 or more) bits of image data and graphic data having a bit configuration smaller than the number of configuration bits of the image data. The display control system according to claim 1, wherein the display control system is a display control system. 10. In a portable computer equipped with a flat panel display unit and a connector for connecting an option board, a decompression circuit for decompressing Y, U, V image compression data, and a Y decompressed by the decompression circuit. , U, V, signals R,
An MPEG (Motion Picture E) equipped with a YUV / RGB conversion circuit for converting into G and B signals.
xperts Group) Option board (MPE)
G board); is used to temporarily store the expanded image data input from the YUV / RGB conversion circuit via the connector, and displays the display timing for a CRT display device on the flat panel display. Frame buffer memory means used for converting display timing for display; video memory means for storing text data and graphics data; palette means for color converting display data output from the video memory means; Selecting means for selectively outputting the image data output from the frame buffer means and the display data output from the palette means; and controlling the gray scale of the display data output from the selecting means to control the flatness. Gradation control means for outputting to the panel display unit; Display control system characterized by comprising a D / A converter means for converting the display data outputted from the means R, G, to an analog signal B. 11. A graphics subsystem (VGA core) for controlling read / write of display data to said video memory means and read / write of display data to said frame buffer memory means and image data, 11. The graphic subsystem, the palette means, the selecting means, the gradation control means, and the D / A converter means are composed of a high integration semiconductor device in one chip. Display control system. 12. The graphics subsystem is a VG
12. The display control system according to claim 11, which has an A (Video Graphics Arrays) standard. 13. A means for displaying together 2n (n is a positive integer of 8 or more) bits of image data and graphic data having a bit configuration smaller than the number of configuration bits of the image data are mixedly displayed. Claim 10
The display control system described in 1. 14. A portable computer equipped with a flat panel display unit and a connector for connecting an option board, a decompression circuit for decompressing Y, U, V image compression data, and a compression decompressed by the decompression circuit. A DVI (Digital Video) that is equipped with a memory that stores image data
o Interactive option board (DV)
I board); used to temporarily store the expanded YUV image data input from the expansion circuit via the connector, and display timing for a CRT display device for the flat panel display. Frame buffer memory means used for converting to display timing; YUV / RGB converting means for converting the YUV image data output from the frame buffer memory means into RGB form; text data and graphics data Video memory means for storing;
Palette means for color-converting display data output from the video memory means; selection means for selectively outputting image data output from the frame buffer means and display data output from the palette means; Gradation control means for controlling the gradation of the display data output from the selecting means and outputting the same to the flat panel display unit; and the display data output from the selecting means into R, G, B analog signals. A display control system comprising: a D / A converter means for converting. 15. A graphics subsystem (VGA core) for controlling read / write of display data to said video memory means and read / write of display data to said frame buffer memory means and image data, further comprising: The graphics subsystem, the YU
15. The V / RGB conversion means, the palette means, the selection means, the gradation control means, and the D / A converter means are composed of a highly integrated semiconductor device in one chip. Display control system described. 16. The graphics subsystem is a VG
The display control system according to claim 14, wherein the display control system has an A (Video Graphics Arrays) standard. 17. A means for mixing and displaying 2n (n is a positive integer of 8 or more) bit image data and graphic data having a bit configuration smaller than the number of configuration bits of the image data are provided. 15. The method according to claim 14,
The display control system described in 1. 18. A memory means for storing the compressed image data is a dynamic random access.
15. The memory according to claim 14, wherein the memory is composed of a memory.
The display control system described in 1. 19. In a portable computer having a flat panel display unit, decompressing means for decompressing YUV image compressed data; memory means for storing compressed image data decompressed by said decompressing means; decompressing by said decompressing means. It is used to temporarily store the recorded YUV image data,
Frame buffer memory means used to convert display timing for the T display device to display timing for the flat panel display; YUV image data output from the frame buffer memory means to RGB
YUV / RGB conversion means for converting to the form; video memory means for storing text data and graphics data; palette means for color conversion of display data output from the video memory means; output from the frame buffer means Selecting means for selectively outputting the image data to be displayed and the display data output from the palette means; controlling the gradation of the display data output from the selecting means and outputting to the flat panel display unit. 20. The display control according to claim 19, further comprising: gradation control means; and D / A converter means for converting the display data output from the selection means into R, G, B analog signals. system. 20. A graphic subsystem for controlling read / write of display data to said video memory means and read / write of display data and image data to said frame buffer memory means, said graphic subsystem. , The expansion means, the memory means, the YUV / RGB conversion means, the palette means, the selection means, the gradation control means, and the D /
20. The display control system according to claim 19, wherein the A converter means is composed of a high integration semiconductor device on one chip. 21. The graphics subsystem is a VG
The display control system according to claim 20, wherein the display control system has an A standard. 22. A means for displaying mixedly 2n (n is a positive integer of 8 or more) bits of image data and graphic data having a bit configuration smaller than the number of configuration bits of the image data are provided. The feature of claim 19
The display control system described in 1. 23. A computer comprising a flat panel display unit, a connector for connecting an option board, and a system bus, the computer being connected to the system bus and the portable computer via the connector, A decompression circuit for decompressing Y, U, and V image compression data,
Y, U, V expanded by the expansion circuit, the signal R,
An MPEG (Motion Picture Ex) equipped with a YUV / RGB conversion circuit for converting into G and B signals and a first frame buffer for temporarily storing the RGB image data output from the YUV / RGB conversion circuit.
and a display panel for a CRT display device into a display timing for the flat panel display, while temporarily storing image data output from the first frame buffer via the system bus. Second frame buffer means used to store the data; video memory means for storing text data and graphics data; palette means for color-converting display data output from the video memory means; second frame buffer Selecting means for selectively outputting the image data output from the means and the display data output from the palette means; the flat panel display unit by controlling the gradation of the display data output from the selecting means Gradation control means for outputting to the above; D / A converter means for converting the display data output from the selecting means into R, G, B analog signals; and read / write of image data for the first frame buffer, and display data for the video memory means. Read / write and read / write of display data and image data to the second frame buffer means
A display control system comprising: a graphic subsystem for controlling lights. 24. The graphics subsystem is a VG
24. The display control system according to claim 23, which has an A standard. 25. The palette means, the selection means, the gradation control means, the D / A converter means, and the graphic subsystem are constituted by one chip of a highly integrated semiconductor device. Item 24. The display control system according to Item 23. 26. A means for displaying together image data of 2n (n is a positive integer of 8 or more) bits and graphic data having a bit configuration smaller than the number of configuration bits of the image data are provided. 24. The method according to claim 23,
The display control system described in 1. 27. A computer provided with a flat panel display unit, a connector for connecting an option board, and a system bus, the computer being connected to the system bus and the portable computer via the connector, A decompression circuit for decompressing Y, U, and V image compression data,
DVI mounted with a first frame buffer for temporarily storing the RGB image data output from the decompression circuit
(Digital Video Interactive
e) an option board; temporarily stores image data output from the first frame buffer via the system bus, and converts display timing for a CRT display device into display timing for the flat panel display. Second frame buffer means used for the display; YUV output from the second frame buffer
YUV / RGB conversion means for converting form image data into RGB image data; video memory means for storing text data and graphics data; palette means for color conversion of display data output from the video memory means Selecting means for selectively outputting the image data output from the YUV / RGB converting means and the display data output from the palette means; controlling the gradation of the display data output from the selecting means Gradation control means for outputting the display data output from the selecting means to R, G, B analog signals; and the first frame buffer. Image data read / write, display data read / write to the video memory means DOO, and display data to the second frame buffer means, and the image data read /
A display control system comprising: a graphic subsystem for controlling lights. 28. The graphics subsystem is a VG
The display control system according to claim 27, which has an A standard. 29. The YUV / RGB conversion means, the palette means, the selection means, the gradation control means, the D
28. The display control system according to claim 27, wherein the A / A converter means and the graphic subsystem are composed of a high integration semiconductor device in one chip. 30. A means for mixing and displaying 2n (n is a positive integer of 8 or more) bits of image data and graphic data having a bit configuration smaller than the number of configuration bits of the image data are further provided. 27. The method according to claim 27, wherein
The display control system described in 1. 31. A one-chip display controller configured by a highly integrated semiconductor device, wherein a video memory for storing display data is a CPU (cent).
read / write port for access by a local processing unit); a read port for reading display data stored in the video memory into a palette;
A read port used for converting display timing for an RT display device into display timing for a flat panel display and for reading out to a frame buffer used for storing image data; A write port for writing the read display data into the frame buffer; a write port for writing image data into the frame buffer; a read port for reading image data from the frame buffer; to the video memory A graphics subsystem for controlling read / write of display data and read / write of image data to the frame buffer; palette for color conversion of display data output from the video memory; output from the frame buffer Image de A switching circuit for switching and outputting the display data output from the palette; a gradation control circuit for controlling the gradation of the display data output from the switching circuit and outputting to the flat panel display unit; and D / A for converting display data output from the switching circuit into R, G, B analog signals
One-chip display cotton controller, which is provided with a converter. 32. A one-chip display controller including a highly integrated semiconductor device, wherein a video memory for storing display data is a CPU (cent).
read / write port for access by a local processing unit); a read port for reading display data stored in the video memory into a palette;
A read port used for converting a display timing for an RT display device into a display timing for a flat panel display, and for reading to a frame buffer used for storing YUV image data; A write port for writing the display data read from the memory into the frame buffer;
A write port for writing image data to the frame buffer; a read port for reading image data from the frame buffer; a read / write of display data to the video memory and a read / write of image data to the frame buffer A graphic subsystem for controlling light; a palette for color conversion of display data output from the video memory; a YUV / RGB conversion circuit for converting YUV image data output from the frame buffer into RGB image data The YU
A switching circuit for switching and outputting the image data output from the V / RGB conversion circuit and the display data output from the palette; a flat panel display unit for controlling the gradation of the display data output from the switching circuit And a D / A converter for converting the display data output from the switching circuit into R, G, B analog signals. 33. Frame buffer means for storing decompressed image data; means for receiving the decompressed image data in real time and temporarily holding the decompressed image data, which is provided before the frame buffer means; Controlling means for holding the decompressed image data based on the control information from the means for holding the display control information of the image data. And a means for writing the image data to the frame buffer means in real time, the multimedia display control system. 34. The multimedia display control system according to claim 33, wherein the means for temporarily holding the image data comprises a FIFO register. 35. The multimedia display control system according to claim 33, wherein the image data includes MPEG moving image data and DVI moving image data. 36. A means for temporarily holding data read from the frame buffer means; a means for holding control information of the image information to be read; and a control information from the control information holding means. 34. The multi according to claim 33, further comprising means for reading out image data from said frame buffer means, holding it in said temporary holding means, and enlarging / reducing the read image data. Media display control system. 37. The multimedia display control system according to claim 36, wherein the means for temporarily holding the read image is configured by a FIFO register. 38. The multimedia display control system according to claim 36, further comprising means for superimposing image data from said temporary holding means and display data from a high resolution graphic subsystem. 39. The display data from the high resolution graphics subsystem is VGA (Video Graph).
39. The multimedia display control system according to claim 38, comprising display data of ics Arrays. 40. The multimedia display control system according to claim 33, wherein the control information of the image data includes information for controlling a display area of the moving image data. 41. A unit for receiving and temporarily holding the expanded image data, a unit for holding control information for displaying the image data, a unit for writing the image data in real time to the frame buffer unit, A unit for temporarily holding the image data read from the frame buffer unit, a unit for holding the control information of the image information to be read, a unit for enlarging / reducing the read image data, and the image data, 39. The multimedia display control system according to claim 38, wherein the means for superimposing the display data from the resolution graphic subsystem is constituted by one chip. 42. In a display controller for reading out still image data or moving image data stored in a frame buffer and enlarging or reducing it to an arbitrary size and displaying it at an arbitrary position on a screen to be displayed, Means for holding a value indicating the size of the stored data, horizontal and vertical scale values indicating the reduction ratio, and a value indicating the area of the window to be displayed; and a specific dot of the still image data or the moving image data. A means for performing a reduction process by omitting it; and determining whether the reduction ratio is such a reduction ratio that the amount of data to be displayed is smaller than the amount of data to be omitted, and if so, obtain the data to be displayed. A display controller comprising: means for changing a rate of dropping. 43. Means for converting decompressed moving image data of each RGB n bits to moving image data of each RGB m (n> m) bits supplied from the outside; display of moving image data and high resolution graphic subsystem Means for superposing the data; means for converting the n-bit display data from the high resolution graphic subsystem or an n-bit output from the superposing means into color data for each RGB m-bit; Means for converting the output from the means for converting to moving image data into n-bit color identification data, and converting the output from the means for converting to RGB m-bit color data into n-bit color identification data; Means for holding n-bit color identification data obtained by converting m-bit color data for each RGB;
A means for comparing the n-bit color identification data obtained by converting the bit moving image data with the color identification data held by the holding means and writing the closest color identification data to the frame buffer as n-bit moving image data. A video data display control system characterized by being provided. 44. In a portable computer equipped with a flat panel display unit and a connector for connecting an option board: decompression means for decompressing YUV image compression data; and compressed image data decompressed by said decompression means. Memory means for storing; YUV / RGB conversion means for converting the YUV image data expanded by the expansion means into RGB form;
It is used to temporarily store the image data converted into the RGB form by the YUV / RGB conversion means, and also used to convert the display timing for the CRT display device into the display timing for the flat panel display. Frame buffer memory means; video memory means for storing text data and graphics data; palette means for color-converting display data output from the video memory means; image data output from the frame buffer means Selecting means for selectively outputting the display data output from the pallet means; gradation control means for controlling the gradation of the display data output from the selecting means to output to the flat panel display unit And; and the display data output from the selecting means. Portable computer, characterized in that a D / A converter means for converting the data into R, G, analog signals B. 45. A graphics subsystem for controlling read / write of display data to said video memory means and read / write of display data to said frame buffer memory means and image data, said graphics subsystem. , The expansion means, the memory means, the YUV / RGB conversion means, the palette means, the selection means, the gradation control means, and the D /
The portable computer according to claim 44, wherein the A-converter means is composed of a highly integrated semiconductor device on one chip. 46. The graphics subsystem is a VG
The portable computer according to claim 45, which has an A standard. 47. Further comprising means for displaying together 2n (n is a positive integer of 8 or more) bits of image data and graphic data having a bit configuration smaller than the number of configuration bits of the image data. Claim 44.
The portable computer described in. 48. In a portable computer having a flat panel display unit, means for receiving image data externally supplied to the portable computer; and display timing for a CRT display device to display timing for the flat panel display. Frame buffer memory means used for converting and used for storing said image data; video memory means for storing text data and graphics data; display data output from said video memory means Palette means for color-converting the image data; selection means for selectively outputting image data output from the frame buffer means and display data output from the palette means; display data output from the selection means Gradation control means for controlling the tone and outputting to the flat panel display unit; and D / A converter means for converting the display data output from the selecting means into R, G, B analog signals. A portable computer characterized in that.