JPH0658964B2 - Semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor device such as a MIS type field effect transistor having a structure in which an insulating film is formed on a III-V group compound semiconductor substrate.

[Prior Art] A semiconductor device having a structure in which an insulating film is formed on a III-V group compound semiconductor substrate is, for example, III-V.
There is a field effect transistor having a MIS type configuration in which a metal layer is arranged on a group compound semiconductor substrate with an insulating film interposed therebetween. Among III-V compound semiconductors, InP is an inverted MI
It has attracted attention because it is relatively easy to fabricate S-type field effect transistors. However, since the characteristics of the interface between the insulating edge and the semiconductor are excellent, and the technology for forming an insulating film that can withstand practical use has not yet been established, an Inp-MIS type field effect transistor with satisfactory electrical characteristics has been realized. However, there are problems that the effective mobility of electrons is small and that the drain current drifts greatly with time.

The insulating film is roughly classified into (1) a method of oxidizing the surface of the semiconductor itself to form an oxide film, and (2) a method of depositing an oxide or a nitride on the semiconductor surface by an appropriate method. There are two types.

A common drawback of III-V group compound semiconductors is that the vapor pressure of the V group element (phosphorus (P) in the case of InP) is high, and when a high temperature process such as thermal oxidation established in silicon is applied. It is possible that the semiconductor surface itself is decomposed or thermal transformation occurs, and the electrical characteristics between the insulating film and the semiconductor interface are significantly deteriorated. Therefore, when using a III-V group compound semiconductor, it is indispensable to form a film by a low temperature process.

For example, when the anodic oxidation method is used, it is possible to form a film at room temperature and avoid the problem of evaporation of the group V element in a high temperature process, but the formed film has poor insulation and is chemically unsuitable. It had the drawback of being stable.

In the deposition method, considering the effect of interdiffusion at the interface, it is desirable that the constituent element of the insulating film is close to the constituent element of the semiconductor. From this point, the conventionally studied nitrogen phosphide (P ₃ N ₅ ) contains phosphorus (P), which is a component of InP,
It is convenient. However, in order to form P ₃ N _5, the usual method using phosphine (PH ₃ ) and ammonia (NH ₃ ) requires heating the InP substrate to 500 ° C or higher, and thermal degradation of the substrate surface is unavoidable. Met. Therefore, high performance
The MIS field effect transistor could not be realized.

[Object] Therefore, in view of the above points, an object of the present invention is to provide an insulating film.
An object of the present invention is to provide a semiconductor device provided with an insulating film having excellent interface characteristics with a III-V group compound semiconductor and which can withstand practical use.

Another object of the present invention is to provide a semiconductor device suitable for constituting a high performance Inp-MIP type field effect transistor.

[Structure of the Invention] In order to achieve such an object, in the present invention, an inorganic polymer (PON) _n, which is an insulating film containing P similarly to P ₃ N ₅ and capable of chemical deposition at a temperature of 500 ° C. or less, and An insulating polymer film containing a polymer of phosphorylamide (P ₂ O ₂ N ₃ H ₃ ) _n is arranged on a III-V group compound semiconductor.

[Examples] In forming a semiconductor device of the present invention, first, a III-V group compound semiconductor substrate, for example, an InP substrate is placed in a quartz reaction tube heated in an electric furnace, and one end of the reaction tube is placed. Ammonia (NH ₃ ) diluted with argon gas and phosphorus oxytrichloride (POCl ₃ ) or phosphorus oxytribromide (POB)
r ₃ ) 36 by supplying argon gas containing steam
It was possible to deposit a polymer film mainly composed of (PON) _n having a thickness of 0.1 μm and further containing phosphorylamide (P ₂ O ₂ N ₃ H ₃ ) _n under conditions of 0 ° C. and about 15 minutes. At low temperatures below 300 ℃, phosphorylamide-dominant polymer films were obtained.

In addition, phosphorus trichloride (PCl ₃ ) or phosphorus tribromide (PBr ₃ ) and ammonia and nitric oxide (N ₂ O), or phosphine (PH ₃ )
And chemical vapor deposition using ammonia and nitric oxide (P
It was possible to form an insulating polymer film containing (ON) _n and (P ₂ O ₂ N ₃ H ₃ ) _n .

Here, the polymer film containing (PON) _n and (P ₂ O ₂ N ₃ H ₃ ) _n means (P ₂ O ₂ N ₃ H ₃ ) _n or NH ₃ that escapes from this in the form of ammonia. (PON) _n is the main component, but it also contains the other polymer in addition to it, and also contains various polymers whose composition changed continuously between the compositions of both polymers. Means the membrane.

Hereinafter, a (PON) _n film will be described as an example of such a polymer film.

Figure 1 shows the above method on n-type and p-type InP substrate (PON)
_{This is} a capacitance (pF) -voltage (V) characteristic measured between a semiconductor and a metal in a MIS diode formed by forming an _n film with a thickness of about 0.1 μm and then forming a gold electrode on the film.

The solid line shows the frequency of 1 MHz and the broken line shows the case of 83.3 Hz.

When the (PON) _n film of the present invention is used, as is apparent from FIG. 1, by applying a voltage of about −5 V on the P substrate, a capacitance equal to the insulating film capacitance is obtained. That is, the accumulation layer can be formed on the P substrate. This means that the interface density in the vicinity of the valence band of the semiconductor is small, and the Coulomb scattering of the electric field created by the charge centers of these traps is reduced.Therefore, an n-channel MIS field effect transistor using this insulating film is applied. There are fewer factors that limit the effective mobility of, and high effective mobility is expected.

On the other hand, in the conventional P-type Inp MIS diode using the insulating film, it is difficult to form the storage layer generated when a negative voltage is applied. This is because the interface order density generated at the insulating film-semiconductor interface is extremely large in the vicinity of the valence band, and the Fermi order is pinned.

Next, an example of a process of manufacturing the inverted Inp-MIS field effect transistor using the above-described polymer film as a gate insulating film will be described with reference to FIGS. 2 (a) to 2 (f).

First, as shown in FIG. 2 (a), silicon (Si ⁺ ) ions are implanted into the surface of the semi-insulating InP substrate 1 (accelerating voltage 200 KeV,
After the dose amount 2 × 10 ¹⁴ cm ^-2 ), heat treatment is performed at 800 ° C for 3 minutes by the lamp annealing method, and the surface is n ⁺
Layer 2 was formed. The thickness of this n ⁺ layer 2 was about 0.5 μm.

Then, as shown in FIG. 2B, a SiO ₂ film 3 having a thickness of 1 μm was formed on the n ⁺ layer 2 by a normal chemical vapor deposition method.

Further, as shown in FIG. 2 (C), the SiO ₂ patterns 3-1 and 3-2 having a rectangular shape were left only in the portions corresponding to the source and drain electrodes, and the other portions were removed by a photo process. .

Further, the n ⁺ layer 2 and the substrate 1 between the patterns 3-1 and 3-2 and the substrate 1 were etched to a depth of 1 μm with a sulfuric acid etchant to form a channel portion 4, and the source 5 and the drain 6 were separated.

Then, using POCl ₃ and NH ₃ , at 360 ° C. for 10 minutes,
As shown in FIG. 2 (d), the polymer film 7 is patterned into a pattern 3
-1,3-2, source 5, drain 6, and deposited on the surface of the substrate 1. Its thickness was 1000Å.

It was patterned with a buffered hydrofluoric acid solution as shown in FIG. 2 (e). By removing the SiO ₂ films 3-1 and 3-2, contact windows for the source and drain electrodes are formed on the polymer film 7.
Opened 8-1,8-2.

Then, as shown in FIG. 2 (f), contact windows 8-1, 8-2
Source electrode 9 and drain electrode 10 are formed on the source 5 and drain 6 by vapor deposition of AuGeNi alloy via
The gate electrode 11 was formed on the polymer film 7 by vapor deposition of Au / Al.

Through the above steps, the MIS type field effect transistor shown in FIG. 3 could be formed. In the above example, a special process was introduced to open the contact windows of the source and drain electrodes. However, this is because the (PON) _n film is chemically extremely stable, so that window formation may not be possible by the usual wet etching method. It depends on what you cannot do. By applying a positive voltage Vg to the gate electrode 11, the inversion layer 12 is formed and its surface layer
The electron moves through 12. In this example, the channel length and width are 10 μm and 130 μm, respectively.

The drain current-drain voltage characteristic with the gate voltage of the semiconductor device formed as described above as a parameter
Shown in the figure. As can be seen from this characteristic, such a semiconductor device exhibited the characteristics of a field effect transistor, and an effective electron mobility exceeding 1000 cm ² / V · sec was obtained. This value is about two orders of magnitude higher than when using a PN film produced by a conventional high temperature process. This is due to the effect of forming the insulating film in a low temperature state and the accompanying reduction in the interface order density.

As another electrical characteristic of the MIS field effect transistor, the drift characteristic of the drain current Id is shown in FIG. Here, the drain current Id (10 of 10 ^-6 seconds after application of the gate voltage
^The value standardized by ^-6 seconds is shown with respect to the time axis (logarithmic scale).

The solid line 13 in the figure is an experimental value when the polymer film according to the present invention is used. No drift is observed even under extremely severe conditions such as a gate voltage of 1 V and a drain voltage of 0.1 V, and after 10 ⁴ seconds. The drain current could be maintained almost constant. On the other hand, an example of using a conventional insulating film is shown in comparison with a broken line 13. In this case, most of the insulating films show a large drift, and the drain current value is
After 10 ⁴ seconds, it has fallen to less than 20% of the initial value. Although not shown here, in the case of the device according to the present invention, it was confirmed that the drain current value did not change even after 3 × 10 ⁵ seconds.

Thus far, there has been no MIS field effect transistor that does not exhibit drift over a long period of time. That is, when the gate insulating film is formed by the conventional method, there is a serious problem that the drain current of the MIS field effect transistor sharply decreases with time, but this is because the denseness of the gate insulating film is poor. Therefore, there are a large number of electron trap orders with large time constants in the film, and the main cause is that the electrons as current carriers in the inversion layer decrease with time due to the electron traps in this order.

On the other hand, in the MIS type field effect transistor using the polymer film according to the present invention, it is judged that the electron trap order in the film is extremely low because the gate insulating film is highly dense.

[Effects] As described above, according to the present invention, it is possible to configure a field effect transistor using an insulating film having a good interface characteristic between the insulating film and the semiconductor, and to provide a semiconductor device having excellent characteristics. It has the great advantage of being easy to manufacture.

[Brief description of drawings]

FIG. 1 is a voltage-capacitance characteristic diagram of an insulating film used in the present invention, FIGS. 2 (a) to 2 (f) are sectional views sequentially showing an example of a manufacturing process of a semiconductor device of the present invention, and FIG. FIG. 4 is a cross-sectional view showing an example of the structure of a semiconductor device, FIG. 4 is a drain voltage-drain current characteristic diagram in the semiconductor device of the present invention, and FIG. 5 is a drain current drift characteristic diagram in the semiconductor device of the present invention. 1 ... InP substrate, 2 ... n ⁺ layer, 3 ... SiO ₂ film, 3-1,3-2 ... SiO ₂ pattern, 4 ... Channel portion, 5 ... Source, 6 ... Drain, 7 ... Polymer film, 8- 1, 8-2 ... Contact window, 9 ... Source electrode, 10 ... Drain electrode, 11 ... Gate electrode, 12 ... Inversion layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiichi Yamaguchi 3-9-11 Midoricho, Musashino-shi, Tokyo Inside Nippon Telegraph and Telephone Public Corporation Musashino Electro-Communications Research Laboratory (72) Inventor Yukihiro Hirota 3-9 Midoricho, Musashino-shi, Tokyo No. 11 in Nippon Telegraph and Telephone Public Corporation Musashino Electro-Communications Research Laboratory (56) References JP-A-58-68935 (JP, A)

Claims (1)

[Claims] 1. A III-V compound semiconductor substrate, wherein an inorganic polymer film containing (PON) _n and (P ₂ O ₂ N ₃ H ₃ ) _n is arranged on the substrate. Semiconductor device.