JPH0658949B2 - Semiconductor imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] [Field of Industrial Application] The present invention relates to a static induction transistor (Static Induction T
ransistor, hereinafter abbreviated as SIT. ) Type image sensor (SIT image sensor) and charge transfer device (Charge C
oupIed Device, hereinafter abbreviated as CCD. ) Integrated semiconductor imaging device. The present invention provides a semiconductor image pickup device that has excellent characteristics of low light sensitivity, low noise, high speed, wide dynamic range, etc., and can be easily configured with peripheral circuits. It is widely used as a solid-state image sensor.

[Conventional technology]

Conventionally, as a solid-state image sensor, a photodiode and a MO are used.
Pixels composed of S switch transistors are arranged in a matrix and signals are read out by an XY address system.
There are an OS type image sensor, a CCD type image sensor in which a pixel and a signal transfer unit are composed of charge transfer elements, and a CPD (Charge Priming Device) type image sensor in which a MOS type image sensor and a CCD type image sensor are combined. .

Further, a solid-state image pickup device by SIT was already proposed by the present inventor in 1978, and is disclosed in JP-A-55-15229, "Semiconductor image pickup device", and JP-A-59-45781, "Semiconductor image pickup device". There is.

An example of a system in which a SIT photosensor is used as a photodetector and a CCD is used as a signal transfer circuit is disclosed in Japanese Patent Laid-Open No. 59-108463.
No. “Solid-state imaging device”.

[Problems to be solved by the invention]

Most of the read methods of the SIT image sensor proposed so far are XY address methods.
In order to operate the SIT image sensor configured in an N × M matrix, N-stage and M-stage output shift registers are required. In particular, when high-speed reading is required or for a large-scale sensor matrix, a large-scale pulse generation circuit that outputs high-speed pulses is required, which makes circuit design difficult and requires a more advanced process technology.

On the other hand, the CCD type image sensor has a drawback that it has a low photosensitivity, although the drive circuit can be constructed relatively easily.
The MOS type image sensor and the CPD type image sensor also have a light sensitivity of 1 or less.

In the system disclosed in Japanese Patent Laid-Open No. 59-108463, in which the SIT photosensor is used in the photodetector and the CCD is used in the signal transfer circuit, a load resistor and a video power source are connected to all the signal reading lines, and a gate address is provided. The parallel signal output on each signal read line read in is input to the CCD, and the read portion is a one-line CCD. In this signal reading method, it is necessary to connect a load resistance and a video power supply voltage having the same value on each signal reading line, and the configuration and operation are complicated. Also,
Since the CCD for the transfer circuit is a one-line CCD, 1
The next gate line cannot be addressed until the photocell on the gate line is read. That is, the reading speed is limited in terms of high-speed reading.

[Means for solving problems]

In order to solve the above-mentioned problems, in the present invention, the photodetection unit is composed of an SIT photocell having excellent photosensitivity characteristics, and the signal transfer unit can be driven by a two-phase or three-phase pulse. We propose a semiconductor image pickup device which is composed of a frame transfer type or interline type vertical CCD capable of accumulating and transferring optical information, a horizontal CCD of one line, and a SIT amplifier as a signal output circuit.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention in which the photodetector is composed of a gate storage type SIT photosensor whose source is grounded, the signal transfer part is composed of a frame transfer type CCD, and the output circuit is composed of a SIT amplifier. The circuit diagram of an Example is shown.

Each SIT photocell is composed of an electrostatic induction phototransistor and a gate capacitor that is read close to the gate of the electrostatic induction phototransistor. In the SIT photosensor having an N × M matrix, the drains of the SIT photocells arranged in the same row are read lines RL1 ... 1, RL2 ... 2, RL3.
, ..., RLM ... 4, and the gate capacitors of the SIT photocells arranged in the same column have common gate address lines GL1 ... 5, GL2 ... 6, GL3.
... 7, ..., GLN ... 8 are connected. Each read line is connected to a precharge power supply V _p ... 10 Through a precharge MOS transistor 9. Further, each read line is connected to a diode 12 forming a signal storage capacitor via a transfer MOS transistor 11, and further connected to a signal transfer vertical CCD 14 via an input gate 13. A horizontal CCD 15 is connected to the final stage of the vertical CCD 14. The final stage of the horizontal CCD 15 is connected to the SIT amplifier 16. A refresh MOS transistor 17 and a signal storage diode 18 are provided at the gate of the SIT amplifier.
Are connected. Vertical CCD 14 and horizontal CCD 1
Each of 5 is driven by a two-phase clock.

Next, the operation of the embodiment shown in FIG. 1 will be described. During the light accumulation time, the light incident from the surface of each SIT photocell generates electron-hole pairs in the depleted high-resistance region between the source and drain of the SIT photocell, and the electrons are drained. However, the holes are accumulated in the gate region which is in a floating state in terms of direct current in the gate capacitor. When reading the signal, first transfer pulse φ
_The transfer MOS transistor 11 is turned on by _T ... 19, the precharge MOS transistor 9 is turned on by the precharge pulse φ _P ... 20, and the read line and the signal storage diode 12 are turned on by the precharge power supply V.
It is biased to a constant potential by _P ... After the precharge pulse φ _T ... 20 is cut off, the first gate address φ _G1 ... 21 is applied, and the optical information of each SIT photocell arranged in the first column is stored in the signal storage diode 12. At this time, the current flowing between the source and drain of the SIT photocell is a current obtained by amplifying the optical information accumulated in the gate region of the SIT photocell. The optical gain of SIT, that is, the ratio of the number of electrons in the output current to the number of incident photons is very large, and data exceeding 10 ⁸ in terms of direct current has been obtained. For this reason, the SIT photocell has a very low photosensitivity and a large output current can be obtained. After the first gate address pulse φ _G1 ... 21 is cut off, the transfer pulse φ _T ... 19 is also cut off. Next, the input gate pulse φ _I ...
25 and vertical CCD driving two-phase clock φ _1A ... 26,
The optical information is transferred to the vertical CCD by φ _2A ... 27.
Then, the transfer pulse φ _T ... 19 And the precharge pulse φ _P ... 20 are applied again, the read line and the signal storage diode 12 are biased, and the precharge pulse φ _P ... 20 is cut off. phi _{G2 ...} 22 is applied, the optical information of each SIT photocell in the second column are collected in a signal storage diode.
After cutting off the second gate address pulse φ _G2 ...
The transfer pulse φ _T ... 19 is also cut off, and the optical information is sent to the vertical CCD. In this way, the optical information of all SIT photocells is sent to the vertical CCD. The optical information sent to the vertical CCDs is sequentially sent to the horizontal CCDs, and the horizontal CCDs drive the two-phase clocks φ _1B ... 28, φ _2B ...
29, it is sent to the SIT amplifier 16 of the output circuit.
The gate of the SIT amplifier 16 is
By applying the refresh pulse φ _R ... 30 to the refresh MOS transistor 17, the refresh power supply V
It is biased to a constant value by _R ... 31. At this time, the signal storage diode 18 is also biased. In this state, S
Optical information is sent to the gate of the IT amplifier, and its amplified current is obtained at the output. By configuring the signal transfer unit with the CCD, the configuration of the peripheral circuit for outputting the drive pulse is simplified. In the XY address type SIT image sensor, when the sensor matrix is composed of N × M photocells, an N-stage output gate address shift register and an M-stage output read line selection shift register are provided. Is required. When the sensor matrix becomes large-scale or in the case of high-speed read operation, the shift register becomes large-scale and high speed is required. In particular, the read line selection shift register needs to operate at high speed. On the other hand, in the circuit system shown in FIG. 1, all the CCDs of the signal transfer unit are driven by the two-phase clocks, so that the configuration of the peripheral circuit is simplified. In particular, the two-phase clock φ _1B ... 28, φ _2B ...
The configuration of 29 is simplified. The SIT photocell has a very high photosensitivity, an excellent weak photosensitivity characteristic, and a wide dynamic range. In order to make full use of the characteristics of this SIT photosensor, it is necessary to design the charge capacity of the diode 12 that constitutes the signal storage capacitor to a size that can sufficiently accept the saturated output current of the SIT photocell. The SIT amplifier is suitable for an output circuit because it has a small distortion and a large output can be obtained. The output circuit is C
FDA method (Floating Diffusion Amplifier method) and FGA method (Floa
ting Gate Amplifier method), DFGA method (Distributed F)
loating Gate Amplifier method).

FIG. 2 shows another embodiment of the present invention in which the photodetector is composed of a source follower mode SIT photosensor, the signal transfer is composed of a frame transfer type CCD, and the output circuit is composed of a SIT amplifier. A circuit diagram is shown.

Each SIT photocell is composed of a static induction phototransistor having a capacitor at the gate. In the SIT optical sensor composed of N × M matrix,
The drain of the SIT photocells, common to all the cells of the n-type buried regions or be connected is formed in the drain bias power supply V _D ... 101 by n-type substrate, the source of the SIT photocell arranged in the same row, each row The common read lines RL1 ... 102, RL2 ... 103, RL3 ... 1
04, ..., RLM ... 105, and the gate capacitors of the SIT photocells arranged in the same column are
Gate address lines GL1 ... 106, GL common to each column
2 ... 107, GL3 ... 108, ..., GLN ... 109. Each read line has a preset M
It is grounded through the OS transistor 110. The other circuit configuration is the same as that of the embodiment shown in FIG. Second
In the figure, 111 is a transfer MOS transistor, 1
12 is a diode which constitutes a signal storage capacitor, 1
13 is an input gate, 114 is a vertical CCD for signal transfer, 1
15 is a horizontal CCD for signal transfer, 116 is a SIT amplifier,
117 is a refresh MOS transistor, 118 is a signal storage diode, φ _T ... 119 is a transfer pulse, φ _R ... 120 is a preset pulse, and φ _G1 ... 12
_{1, φ G2 ... 122, φ} G3 ... 123, ......, φ GN ...
124 is a gate address pulse, φ _I ... 125 is an input gate pulse, φ _1A ... 126, φ _2A ... 127 is a two-phase pulse for driving a signal transfer vertical CCD, φ _1B ... 128, φ
_2B ... 129 is a two-phase pulse for driving a signal transfer horizontal CCD,
φ _R ... 130 is a refresh pulse of the SIT amplifier, V
_R ... 131 indicates a refresh power supply. Each SIT
The electrostatic induction phototransistor that constitutes the photocell is
All S formed by n-type buried region or n-type substrate
An n ⁺ region common to IT photocells, a high resistance region formed thereon by an epitaxial growth layer, an n ⁺ region formed in a stripe shape on the surface of the high resistance region, and a surface n ⁺ region are formed in a stripe shape. Has a surface gate structure consisting of the p ⁺ gate region. Since the static induction phototransistor is operated in the upright mode in which the surface n ⁺ region serves as the source and the buried region or the n ⁺ region of the substrate serves as the drain, the source follower mode SIT photosensor includes the first
A larger output can be obtained than the SIT optical sensor shown in the illustrated embodiment. The timing of the drive pulse is the same as in the embodiment of FIG. Diode 11 forming a signal storage capacitor
2 is preset to zero potential before receiving light information from the SIT photocell. When the SIT photocell is not exposed to light, the signal storage diode 112 is
When the potential is still zero and light is incident on the SIT photocell, the signal storage diode 112 is discharged by the amount of the current flowing through the SIT photocell with respect to the light intensity, and is reverse biased to the positive potential. The amount of charge transferred by the CCD is
When the light intensity is zero, the amount of saturated charges is saturated, and the operation decreases as the light intensity increases, which is the reverse operation of the embodiment shown in FIG.

In FIG. 3, the photodetector is composed of a gate storage type SIT photosensor in which the source of each cell is grounded, the signal transfer part is composed of an interline CCD, and the output circuit is SI.
FIG. 3 shows a circuit diagram of an embodiment of the present invention composed of a T amplifier.

Each SIT photocell is composed of a static induction phototransistor having a capacitor at the gate. The source of each cell is grounded, and the gate capacitor is connected to the gate address terminals GT ... 201 common to all cells. The precharge MOS transistor 202 and the signal storage diode 203 are connected to the drain terminal of each SIT photocell, and further connected to the input gate 204. Precharge MOS transistor 202
The drain of is connected to the common pre-charge power supply V _P ... 205. Optical information is passed through the input gate to vertical C
The data is transferred to the CD 206 and further sent to the horizontal CCD 207. The final stage of the horizontal CCD 207 is the SIT amplifier 20.
8 is connected. 209 is a refresh MOS transistor, and 210 is a signal storage diode. At the time of signal reading, all the precharge MOS transistors 202 are driven by a common precharge pulse φ _P ... 211, and all the signal storage diodes 203 are biased to a constant value by the precharge power supply V _P ... 205. φ _P
After the cutoff, the gate address pulse φ _G ... 212 causes the optical information of all SIT photocells to be stored in the signal storage diode 203. Next, the input gate pulse φ _I ...
213, vertical CCD driving two-phase clock φ _1A ... 21
4, φ _2A ... 215, optical information is imaged on the vertical CCD 206 and further transferred to the horizontal CCD 207. Horizontal C
The optical information transferred to the CD 207 is sent to the output SIT amplifier 208. The horizontal CCD 207 is driven by two-phase clocks φ _1B ... 216, φ _2B ... 217 for driving the horizontal CCD. The embodiment shown in FIG. 3 is an interline system, and all SIT photocells are simultaneously addressed by the same gate address pulse φ _G ... 212. Therefore, even when the scale is increased, it is possible to operate with two sets of two-phase pulses for driving the CCD and the other four pulses. Source follower mode and interline CC
There is also a D configuration.

FIG. 4 (a) is a schematic circuit diagram of a connection portion between the SIT photocell and the signal transfer CCD in the embodiment of the present invention, and FIG. 4 (b) is a schematic circuit diagram of FIG. 4 (a). It is an example of a cross-sectional structure corresponding to a circuit. In FIG. 4 (a), 30
1 is an electrostatic induction phototransistor forming an SIT photocell, 302 is a gate capacitor, 303 is a signal storage diode, 304 is a CCD cell, 305 is an input gate, φ _G ... 306 is a gate address pulse, V _P ... 30
Reference numeral 7 indicates a precharge power source, φ _P ... 308 indicates a precharge pulse, and φ _I ... 309 indicates an input gate pulse.
In FIG. 4B, the SIT photocell, the signal storage diode and the CCD are formed on a common n ⁺ substrate 310. SIT photocells is composed of ^{n +} substrate 310 ^{n +} source regions and ^{n +} drain region 311, ^{p +}
An electrostatic induction phototransistor including a gate region 312, an n ⁻ high resistance layer 313, and a polysilicon electrode 314, an insulating film 315 such as a silicon nitride film, and a transparent conductive material layer 316 such as SnO _2. It is composed of a gate capacitor. One SIT photocell is electrically isolated from the surrounding area by an isolation region 317 made of silicon dioxide SiO ₂ or the like. The diode forming the signal storage capacitor is composed of the p well 318 and the n ⁺ diffusion region 319 provided in the p well 318. An input gate composed of a SiO ₂ film 320, an electrode region 321 and a p well 318 is provided adjacent to the n ⁺ diffusion region 319. Further, a CCD is formed next to the input gate. Reference numeral 322 is an electrode area of the CCD. The p ⁺ region 323 is a diffusion region for making ohmic contact with the p well, 324 is an aluminum electrode forming a gate address line, 325 and 326 are aluminum electrodes, and 327 is SiO ₂ . The drain of the SIT photocell and the signal storage diode are electrically connected.
The n ⁺ substrate 310 and the p well 318 are grounded. Reference numeral 328 is a precharge MOS transistor, which can be provided on the same substrate by a known method.

FIG. 5A shows a signal transfer C in the embodiment of the present invention.
FIG. 5B is a circuit diagram of a connection portion between the CD and the output circuit, and FIG. 5B is an example of a sectional structure corresponding to the circuit of FIG. 5A. In FIG. 5A, 401 is a signal transfer CCD at the final stage, 402 is a signal storage diode, and 403.
Is an SIT amplifier, 404 is a refresh MOS transistor, 405 is an output gate, φ _R ... 406 is a refresh pulse, φ ₀ ... 407 is an output gate pulse, and V _R ... 4
Reference numeral 08 denotes a refresh power supply. In FIG. 5B, the CCD, output gate, refresh MOS transistor, and SIT amplifier are formed on a common n ⁺ substrate 409. Reference numeral 410 is an electrode at the final stage of the signal transfer CCD, 411 is an output gate electrode, and 412 is an SiO.
₂ and the p well 413 form a MIS structure CCD. The refresh MOS transistor includes an n ⁺ drain region 414, an n ⁺ source region 415 and a gate oxide film 4.
16, a gate electrode 417, a drain electrode 418, and a source electrode 419. The SIT amplifier has p ⁺ source region 420, p ⁺ drain region 421, n ⁺ gate region 4422, p ⁻ high resistance region 423, and source electrode 424.
And a gate electrode 425 and a drain electrode 426. 427 is an isolation region and 428 is SiO ₂ .

The structure of FIGS. 4 (b) and 5 (b) can be easily manufactured by a conventional process technique.

In the embodiment of the present invention shown in FIGS. 1 to 3, the output circuit may be the FDA method, the FGA method, or the DFGA method conventionally used in the CCD type image sensor. It is also effective to use a SIT amplifier in the output circuit of the conventional CCD image sensor. The present invention can be applied not only to area sensors configured in a matrix but also to line sensors.

〔The invention's effect〕

According to the present invention, it is possible to realize a solid-state imaging device which has a very high photosensitivity as compared with a conventional solid-state imaging device, particularly has a high weak light detection ability, and can relatively easily configure a drive pulse circuit.
The present invention is particularly effective in applications where the sensor matrix is large-scale and high-speed reading is required. In particular, the SIT, which has an excellent photodetection ability, is used as the photocell, and the CCD, which simplifies the configuration of the peripheral driver, is used as the information transfer section. .

[Brief description of drawings]

In FIG. 1, the photodetector is composed of a gate storage SIT photosensor whose source is grounded, the signal transfer is composed of a frame transfer CCD, and the output circuit is SI.
Circuit diagram of one embodiment of the present invention including a T amplifier, 2nd
In the figure, the photodetector is composed of a source follower mode SIT photosensor, and the signal transfer unit is a frame transfer CCD.
FIG. 3 is a circuit diagram of another embodiment of the present invention in which the output circuit is a SIT amplifier, and FIG. 3 is a gate storage type SIT photosensor in which the source of each cell is grounded in the photodetector. The signal transfer unit is an interline CCD
And a circuit diagram of an embodiment of the present invention in which the output circuit is composed of a SIT amplifier. FIG. 4 (a) is a schematic view of the connecting portion of the SIT photocell and the signal transfer CCD in the embodiment of the present invention. An example of a circuit diagram, FIG. 4 (b) is an example of a sectional structure corresponding to the circuit of FIG. 4 (a), and FIG. 5 (a) is a connection between a signal transfer CCD and an output circuit in the embodiment of the present invention. An example of a circuit diagram of a part, FIG. 5 (b) is an example of a sectional structure corresponding to the circuit of FIG. 5 (a). 1, 2, 3, 4, 102, 103, 104, 105 ...
Readout lines 5, 6, 7, 8, 106, 107, 1
08, 109, 201 ... Gate address line, 9,
202, 328 ... Precharge MOS transistor,
10, 205, 307 ... Precharge power supply, 11, 1
11 ... Transfer MOS transistor, 12, 1
8, 112, 118, 203, 210, 303, 402
... Signal storage diodes, 13, 113, 204, 30
5 ... Input gate, 14, 114, 206 ... Vertical CCD for signal transfer, 15, 115, 207 ... Horizontal CCD for signal transfer, 16, 116, 208, 403 ... SIT amplifier, 17, 117, 209, 404 ... Refresh MOS transistor, 19, 119 ... Transfer pulse, 20, 211, 308 ... Precharge pulse,
21, 22, 23, 24, 121, 122, 123, 1
24, 212, 306 ... Gate address pulse, 2
5, 125, 213, 309 ... Input gate pulse, 2
6, 27, 28, 29, 126, 127, 128, 12
9, 214, 215, 216, 217 ... CCD driving two-phase clock pulse, 30, 130, 218, 406 ...
… Refresh pulse, 101 …… Drain power supply, 11
0 ... Preset MOS transistor, 120 ... Preset pulse, 31, 131, 219, 408 ... Refresh power supply, 301 ... Electrostatic induction phototransistor, 302 ... Gate capacitor, 304, 401 ...
CCD cell, 310, 409 ... n ⁺ substrate, 311 ...
n ⁺ drain region, 312 ... p ⁺ gate region, 313
... n ^- high resistance layer, 314 ... polysilicon electrode, 31
5 ... Insulating film, 316 ... Transparent electrode, 317, 427 ...
... Separation regions, 318, 413 ... P-well, 319 ...
n ⁺ diffusion region, 320, 327, 412, 416, 42
8 ... SiO ₂ film, 321, 322, 410, 411 ...
... CCD electrode area, 323 ... p ⁺ diffusion area, 32
4, 325, 326, 417, 418, 419, 42
3, 424, 425 ... Aluminum electrode, 405 ... Output gate, 407 ... Output gate pulse, 414 ... MOS
N ⁺ drain region of transistor, 415 ... n ⁺ source region of MOS transistor, 420 ... p ⁺ source region, 421 ... p ⁺ drain region, 422 ... n ⁺ gate region, 423 ... p ^- high resistance region

Claims (2)

[Claims] 1. A photocell having an electrostatic induction phototransistor and a capacitor connected to a control electrode of the electrostatic induction phototransistor, wherein one main electrode of the electrostatic induction phototransistor is grounded is n × m. Of photodetectors arranged in a matrix, and n vertical gate address lines GL connected to the m capacitors each.
_j (j = 1 to n), m signal read lines RL _i (i = 1 to m) connected to the other n main electrodes of the static induction transistor, and transfer to the signal read lines. A diode for accumulating an output signal obtained by amplifying an incident light input flowing to the photocell connected through a MOS transistor, and n × for accumulating and transferring signals of all the photocells connected to the diode. m frame transfer type vertical CCD and one line horizontal CC connected to the final stage of the vertical CCD
A semiconductor image pickup device, wherein D and an output circuit formed of a static induction transistor connected to the horizontal CCD are connected to the same semiconductor substrate. 2. A photocell having a static induction phototransistor and a capacitor connected to a control electrode of the static induction phototransistor, wherein one main electrode of the static induction transistor is grounded is n × m. A photodetector arranged in a matrix, a gate address line connected to all of the capacitors and capable of simultaneously selecting all of the photocells, and connected to the other main electrode of the static induction transistor to the photocells. A diode for accumulating an output signal that amplifies the incoming optical input flowing;
An n × m interline vertical CCD connected to the diode through a connection transfer MOS transistor to store and transfer signals of all the photocells
And a one-line horizontal CCD connected to the final stage of the vertical CCD, and an output circuit composed of an electrostatic induction transistor connected to the horizontal CCD are formed on the same semiconductor substrate. apparatus.