JPH0658772A - Signal processing circuit of encoder - Google Patents

Abstract

PURPOSE:To obtain pulses in constant duty even if temperature drift is generated in the output signals of an encoder by computing comparing levels with a CPU based on the output signals of the encoder at every specified time. CONSTITUTION:Differential amplifiers 101 and 102 amplify the output signals in a phase A and a phase B from an encoder, respectively. The output signals are inputted into a CPU 109 through a multiplexer 107 and an A/D converter 108 after sampling and holding in a sample/hold circuits 105 and 106, respectively. The CPU 109 computes the midpoints of the signals based on the peak values on the respective positive side and negative side of the output signals of the amplifiers 101 and 102. The midpoints are imparted as the comparing levels to comparators 103 and 104 through D/A converters 110 and 111, respectively. Therefore, the phase A pulses and the phase B pulses without the effects of temperature drifts are obtained from the comparators 103 and 104, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoder signal processing circuit.

[0002]

2. Description of the Related Art A conventional encoder signal processing circuit is shown in FIG.
As shown in, the A-phase and B-phase output signals of the encoder are differentially amplified by the differential amplifiers 201 and 202, respectively, and then compared with a certain level fixed by the comparators 203 and 204, for example, pulsed in comparison with 0V. The pulse signal was multiplied by the multiplication circuit 205.

[0003]

In the conventional encoder signal processing circuit described above, when a temperature drift occurs in the encoder output signal due to a change in environmental temperature, the pulse duty of the incremental phase changes, and accurate position detection can be performed. There was a drawback to say no. An object of the present invention is to provide an encoder signal processing circuit that can obtain a pulse with a constant duty without being affected by temperature drift even if the encoder output signal has a temperature drift.

[0004]

An encoder signal processing circuit according to the present invention includes a first differential amplifier and a second differential amplifier for differentially amplifying A-phase and B-phase output signals of an encoder, respectively. A first comparator for comparing the output signal of the amplifier with a first comparator level; a second comparator for comparing the output signal of the second differential amplifier with a second comparator level; First and second sample and hold circuits for sampling and holding the output signal of the second differential amplifier, a multiplexer for switching and outputting the output signals of the first and second sample and hold circuits, and an output signal of the multiplexer A / D to convert analog to digital
The output signals of the converter and the first and second differential amplifiers are taken in through the first and second sample and hold circuits, the multiplexer, and the A / D converter for one cycle or more, and the first and second comparators are loaded. CPU to calculate rate level
And the first and second D / A converters that perform digital / analog conversion on the first and second comparator levels and output to the first and second comparators respectively, and the outputs of the first and second comparators. A multiplication circuit for inputting a signal and outputting a pulse signal obtained by multiplying the output signal by a predetermined multiple.

[0005]

Function: The encoder output signal is taken into the CPU at regular intervals, the comparator level is calculated, and the result is given to the comparator, whereby pulse shaping can be performed without being affected by the temperature drift of the encoder output signal. The first,
The number of multiplications can be easily increased by providing a plurality of second comparators and providing a plurality of comparator levels from the CPU to the plurality of comparators.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of an encoder signal processing circuit of a first embodiment of the present invention, and FIG. 2 is a waveform diagram of signals of respective parts thereof. The differential amplifiers 101 and 102 respectively receive the A-phase and B-phase output signals of the encoder, remove common mode noise, and amplify the common mode noise. Differential amplifier 101, 102
Output signal (Fig. 2 (1)) is sample and hold (S
H) After being sampled and held by the circuits 105 and 106 for one cycle or more, they are input to the CPU 109 via the multiplexer 107 and the A / D converter 108. CP
U109 peak value of the positive side and negative side of the output signal of the differential amplifier 101 + V _APEAK, -V _APEAK, peak value + V _BPEAK the positive and negative of the output signal of the differential amplifier 102, -V
Knowing _BPEAK , peak value + V _APEAK and −V _APEAK midpoint V _Ahalf , peak value + V _BPEAK and −V _BPEAK midpoint V
_Bhalf is calculated, and D / A converters 110 and 1 are respectively calculated.
It is given to the comparators 103 and 104 via 11 as a comparator level. Therefore, the comparator 10
3 and 104, the A-phase pulse and the B-phase pulse that are not affected by the temperature drift are obtained as shown in FIGS. 2B and 2C, respectively. The multiplication circuit 112 in the latter stage is an A-phase pulse,
By inputting a B-phase pulse and generating an incremental pulse at each rising and falling edge, the waveform shown in FIG.
A pulse multiplied by 4 as shown in is output. FIG. 3 is a block diagram of an encoder signal processing circuit according to a second embodiment of the present invention,
FIG. 4 is a waveform diagram of the signals of the respective parts.

The difference between this embodiment and the first embodiment is that
Comparators 113 and 1 as phase and B phase comparators
14 is added, and the D / A converter 11 is added to this.
5, 116 is added, and the multiplication circuit 117 outputs an 8 multiplication pulse.

A-phase pulse or B-phase pulse (FIG. 4 (2))
Alternatively, when (5)) is multiplied by 8, the encoder A-phase and B-phase output signals are passed through the SH circuits 105 and 106, the multiplexer 107, and the A / D converter 108 in the same manner as in the first embodiment. , And if those signals are perfect sine waves, the peak value of one of the A-phase or B-phase signals (positive peak value and negative peak value)
1/2 ^{1/2 of the above} is newly obtained, and these values are set as the comparison level from the CPU 109 to the D / A converter
5, 116 through comparators 113, 11 respectively
4 gives pulses A1 and A2 with a constant duty of 360 ° cycle and 45 ° width as shown in FIGS. 4 (3) and 4 (4). These pulses A1 and A2 and the A-phase and B-phase pulses (FIGS. 4 (2) and 4 (5)) are applied to the multiplication circuit 1
17 is input. The multiplication circuit 117 generates an incremental pulse at the rising and falling edges of each pulse, and outputs an 8-times multiplication pulse as shown in FIG. 4 (6).

In the case of further multiplication, the CPU determines the comparison level in the same manner as described above (for example, 2
It can be realized by a multiplication circuit similar to the above, which is given to a plurality of comparators via a D / A converter of a plurality of channels, by calculating a comparator level at every 2.5 ° and 11.25 °.

[0010]

As described above, the present invention has the following effects. (1) The invention of claim 1 comprises a sample and hold circuit, a multiplexer, an A / D converter, a CPU, and a D / A converter, and inputs the output signals of the A phase and B phase of the encoder for one cycle or more, and outputs the output signals. By calculating the comparator level from the signal and giving it to the comparator via the D / A converter, it is possible to obtain a pulse with a constant duty without being affected by the temperature drift of the encoder output signal. (2) The invention of claim 2 has the same configuration as claim 1, and by adding a comparator and a D / A converter, it is possible to obtain a pulse of a constant duty without being affected by temperature drift of the encoder output signal. , And the multiplication number can be easily increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an encoder signal processing circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of signals at various parts of the encoder signal processing circuit of FIG.

FIG. 3 is a block diagram of an encoder signal processing circuit according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram of signals of various parts of the encoder signal processing circuit of FIG.

FIG. 5 is a block diagram of a conventional example of an encoder signal processing circuit.

[Explanation of symbols]

 101, 102 Differential amplifier 103, 104, 113, 114 Comparator 105, 106 Sample and hold circuit 107 Multiplexer 108 A / D converter 109 CPU 110, 111, 115, 116 D / A converter 112, 117 Multiplier circuit

Claims (2)

[Claims] 1. A first differential amplifier and a second differential amplifier for differentially amplifying A-phase and B-phase output signals of an encoder, respectively, and an output signal of the first differential amplifier is compared with a first comparator level. A first comparator, a second comparator for comparing the output signal of the second differential amplifier with a second comparator level, and sample and hold the output signals of the first and second differential amplifiers, respectively. First and second sample and hold circuits, a multiplexer for switching and outputting the output signals of the first and second sample and hold circuits, an A / D converter for analog / digital conversion of the output signals of the multiplexer, Output signals of the first and second differential amplifiers, first and second sample and hold circuits, the multiplexer, and the A / D
A CPU that takes in one or more cycles via a converter and calculates the first and second comparator levels, and performs digital / analog conversion of the first and second comparator levels, respectively, and outputs them to the first and second comparators. An encoder signal processing circuit having first and second D / A converters, and a multiplication circuit which inputs the output signals of the first and second comparators and outputs a pulse signal obtained by multiplying the output signals by a predetermined multiple. . 2. The encoder signal processing circuit according to claim 1, wherein there are a plurality of first and second comparators, and therefore a plurality of first and second D / A converters.