JPH065870A - Semiconductor memory - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a semiconductor memory device capable of collectively and selectively erasing a plurality of memory cell transistors provided in the semiconductor memory device partially and selectively. [Structure] On a substrate 2 having a first conductivity type, for example N type, or in a well 2 ′ having a first conductivity type, for example N type, a second conductivity type, for example P A well 7 having a type is formed, and a memory cell transistor 10 having a channel having a first conductivity type, for example, N type is formed in the well 7 having the second conductivity type, for example, P type. Semiconductor memory device 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of partially changing a memory state of a memory cell transistor.

[0002]

2. Description of the Related Art Conventionally, a non-volatile semiconductor memory device called a flash memory has a structure in which information stored in respective memory cell transistors constituting the non-volatile memory device is electrically stored. It has a function that can be erased collectively. However, in recent years, due to the sophistication of information, the increase in density, the complexity of information processing, etc., one semiconductor memory device is also required to have multiple functions and added value. Also in a semiconductor memory device, in addition to the function of collectively erasing each information stored in a plurality of memory cell transistors forming the semiconductor memory device, the information can be individually or partially erased. There is a demand for a device having a function capable of writing and batch erasing.

However, in a conventional semiconductor memory device, for example, a flash memory, its substrate or well is common to the entire cell array, so that predetermined information is written or erased. In the case of, the entire memory cell composed of transistors is
I could only write or erase. That is,
As to an example of a conventional flash type semiconductor memory device, a semiconductor memory device having a memory cell transistor using a nonvolatile memory element will be described with reference to FIGS. 7 to 9. explain.

FIG. 7 is a cross-sectional view of the nonvolatile memory element 10 which constitutes the above memory cell transistor.
A diffusion layer 3, 3 ′ having a second conductivity type, eg N type, is formed on the main surface of the substrate 2 having a conductivity type, eg P type.
A channel region 4 functioning as an active layer is formed in the region between the diffusion layers 3 and 3 '. On the other hand, above the channel region 4, a floating gate 5 and a control gate 6 are stacked as shown in the figure to form a FET MOS transistor.

In the write operation of the non-volatile memory element 10 having such a structure, a high potential voltage is applied to the control gate 6 and a low potential voltage is applied to the substrate 2, as the principle is explained in FIG. By applying the voltage to form a predetermined potential difference between the two, charges move from the channel region 4 formed in the substrate 2 into the floating gate 5, and the charges are accumulated in the floating gate 5. As a result, information is stored.

To erase the information stored in the nonvolatile memory element 10, as shown in FIG. 8, a low potential voltage is applied to the control gate 6 contrary to FIG. By applying a high potential voltage to 2, the electric charge accumulated in the floating gate 5 moves to the substrate side, and the storage state is canceled. Here, as shown in FIG. 9, the detailed configuration of the conventional nonvolatile memory element 10 is such that the N-type diffusion layers 3 and 3 ′ are provided on the main surface of the P-type substrate 2. Has been formed.

Although the channel region 4 is formed in the region between the diffusion layers 3 and 3 ', it is omitted in FIG. In addition, the floating gate 5 is arranged above the diffusion layers 3 and 3'and across both ends thereof in a direction perpendicular to the arrangement direction of the diffusion layers 3 and 3 '. Further, a control gate 6 is continuously formed above the floating gate 5 in the same direction as the arrangement direction of the floating gates 5 and perpendicular to the bit lines.

That is, the writing or erasing operation of information in the nonvolatile memory element 10 composed of such a memory cell transistor is controlled by the difference between the potential of the substrate 2 and the voltage applied to the control gate 6.
In the conventional configuration of the semiconductor memory device mainly composed of the nonvolatile memory element, since the potential of the substrate 2 is the same for all the nonvolatile memory elements 10, the substrate 2 and the control gate are Since the voltage difference between 6 is determined by the voltage related to the control gate 6,
Currently, only batch writing and batch erasing operations can be performed.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention that, in the above-mentioned prior art, it is difficult to selectively write or erase information collectively for memory cell transistors in a specific area. It is an object of the present invention to provide a semiconductor memory device which can solve the above problems and can collectively and selectively erase collectively a plurality of memory cell transistors provided in the semiconductor memory device.

[0010]

In order to achieve the above object, the present invention basically adopts the following technical constitution. That is, a well having the second conductivity type is formed over a predetermined region on a substrate having the first conductivity type or in a well having the first conductivity type, and the second conductivity type is formed. This is a semiconductor memory device in which a memory cell transistor having a channel having the first conductivity type is formed in an existing well.

[0011]

In the present invention, since the structure as described above is adopted, it is possible to change the voltage applied to each well. Therefore, the control gate of each memory cell transistor constituting the semiconductor memory device is controlled. Since the potential difference between the channel region 6 and the channel region can be selectively made larger than the potential difference in the memory cell transistors in the other regions, it is possible to selectively execute the writing or erasing operation of information with respect to a predetermined memory cell transistor. Is possible.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific example of a semiconductor memory device according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a cross-sectional view showing the configuration of a specific example of a semiconductor memory device according to the present invention. In the figure, on a substrate 2 having a first conductivity type, for example N type, or a first conductivity type, for example, A well 7 having a second conductivity type, eg, P type, is formed in a well 2 ′ having an N type over a predetermined region, and the well 7 having the second conductivity type, eg, P type, is formed in the well 7 ′. First conductivity type,
For example, a semiconductor memory device 1 in which a memory cell transistor 10 having an N-type channel is formed is shown.

Incidentally, 9 in FIG. 1 is the channel region 4
Is a tunnel oxide film formed on the upper surface, and 11 is an isolation insulating film. To explain the structure of the present invention in more detail with reference to FIG. 2, FIG. 2 is a plan view of the semiconductor memory device 1 according to the present invention shown in FIG. A predetermined region 8 of the substrate 2 having N type,
A well 7 having a second conductivity type, eg, P type, is formed over 8 ′, 8 ″, and a well 7 having the second conductivity type, eg, N type, is formed in the well 7 with a first conductivity type, eg, N type. A semiconductor memory device 1 in which a memory cell transistor 10 having a channel having a mold is formed is shown.

That is, in the semiconductor memory device 1 according to the present invention, in a proper substrate 2, over a predetermined region,
A well portion 7 having a conductivity type different from that of the substrate is provided, and a plurality of memory cell transistors 10 are independently formed and arranged in the well portion 7. In the above embodiment of the present invention, the first conductivity type has been described as N-type and the second conductivity type has been described as P-type, but it may be configured in the opposite relationship. Not to mention the matter.

1 and 2, an example in which a well portion having a specific conductivity type is formed in a substrate having a specific conductivity type is shown. The well portion according to the present invention may be further formed in the well portion having a specific conductivity type provided on the substrate. In FIG. 2, the predetermined area 8,
The configuration of each memory cell transistor 10 arranged and formed in each well portion 7 formed in 8 ′ and 8 ″ is, for example, a diffusion layer 3 having a conductivity type different from that of the well portion 7. 3 ′ are arranged facing each other with a predetermined gap for forming the channel region 4.

The conductivity type of the diffusion layers 3 and 3'is made of a material having the first conductivity type, that is, N-type conductivity in the above specific example. Further, as is apparent from FIG. 2, the floating gate 5 having a predetermined length is arranged above the diffusion layers 3 and 3 ′ in a direction substantially perpendicular to the arrangement direction of the diffusion layers 3 and 3 ′. Further, a control gate 6 is formed above the floating gate 5 so as to be continuous in the same direction as the arrangement direction of the floating gates 5.

In FIG. 2, the memory cell transistors 10 are preferably arranged in a matrix, and the control gates 6 are arranged in the same direction as the word lines in the semiconductor memory device. It is preferable that they match, and the arrangement direction of the diffusion layers 3 and 3 ′ is
It is preferable that the direction coincides with the direction of the bit line in the semiconductor memory device.

Also, in the semiconductor memory device according to the present invention, the well portion 7 individually includes a plurality of memory cell transistors 10 arranged in a line in the direction of the bit lines as shown in FIG. In order to include them, they may be arranged and formed in parallel with each other, or may include a plurality of sets of a plurality of memory cell transistors 10 arranged in a line in the direction of the bit line. It may be arranged and formed in the same manner.

Further, in some cases, it may be arranged intermittently also in the bit line direction. That is, in the semiconductor memory device according to the present invention, since the well portion 7 is formed separately, it is formed in the control gate 6 and the well portion 7 of the memory cell transistor 10 for each well portion. Since it is possible to change the potential difference of the voltage applied between the memory cell transistor 10 and the channel region 4, the memory cell transistor 10 in a predetermined region or the control gate in a predetermined individual memory cell transistor 10 Since the potential difference between the channel region and the channel region can be selectively set to the writable level and at the same time the erasable potential difference can be selectively set, predetermined information is selected for the memory cell transistor 10 in the semiconductor memory device. It is possible to write or erase the data.

The memory cell transistor 10 used in the semiconductor memory device according to the present invention is preferably composed of, for example, a non-volatile memory element, and the non-volatile memory element includes a control gate 6 and a floating gate. 5 is included. FIG. 3 is a circuit diagram showing a specific example of the semiconductor memory device 1 according to the present invention. As described above, the plurality of memory cell transistors 10 are each composed of a nonvolatile memory element. Are arranged in a matrix along the word lines WL and the bit lines BL.

As is apparent from FIG. 3, the control gate 6 of each memory cell transistor 10 is connected to the word line WL of the semiconductor memory device 1, and the back gate C is connected to the bit line BL. Has been done. That is, in this specific example, the back gate C indicates the potential of the channel region 4 formed in the well portion 7.

FIG. 4 is a diagram for explaining the operation when the semiconductor memory device according to the present invention is used to write or erase predetermined information in the selected specific storage means. FIG. 4A illustrates an example of a case in which predetermined information is written only in the four memory cell transistors 101 to 104 arranged along the bit line BL1. First, the word line WL1 To all the word lines WL4 to high voltage and only the bit line BL1 to negative voltage, and at the same time all other bit lines BL2 to BL
The voltage of 3 is maintained at 0V.

By setting such a state, the bit line B concerned
The potential difference between the control gate 6 and the channel region 4 in all the memory cell transistors 10 arranged along L1 is set to the potential difference required to write information in the floating gate 5, that is, the memory cell in question. The threshold value Vth of the transistor 10 becomes high, and as a result, predetermined information is stored, but the potential difference between the control gate 6 and the channel region 4 of the other memory cell transistor 10 is necessary for writing information. No information is stored because the potential difference is not set.

FIG. 4B shows two memory cell transistors 101 arranged along the bit line BL1.
An example in which predetermined information is written to only 102 is described. First, the word line WL1 and the word line W
Only L2 is set to a high voltage, only bit line BL1 is set to a negative voltage, and at the same time, the voltage of all other bit lines BL2 to BL3 is maintained at 0V.

By setting such a state, the bit line B concerned
Memory cell transistors 1 arranged along L1
The potential difference between the control gate 6 and the channel region 4 in 01 and 102 is the floating gate 5 concerned.
Is set to a potential difference necessary for writing information, that is, the threshold value Vth of the memory cell transistor 10 becomes high, and as a result, predetermined information is stored, but the control gate 6 of the other memory cell transistor 10 is stored.
The potential difference between the channel region 4 and the channel region 4 is not set to the potential difference required to write information, so information is not stored.

FIG. 4C shows three memory cell transistors 101, 1 arranged along the bit line BL1.
An example in which predetermined information is written only in 03 and 104 is described. First, only the word line WL1, the word line WL3, and the word line WL4 are set to a high voltage, and only the bit line BL1 is set to a negative voltage. At the same time as setting the voltage, the voltage of all other bit lines BL2 to BL3 is maintained at 0V.

In such a state, predetermined information is stored in the memory cell transistors 101, 103 and 104 by the same principle as described above, but no information is stored in the other memory cell transistors. In the specific example, the storage information can store a certain type of data in an encoded form.
It can be considered that the data 011 is stored.

In contrast to FIG. 4A, FIG. 5A erases the predetermined information stored in the four memory cell transistors 101 to 104 arranged along the bit line BL1. First, all of the word lines WL1 to WL4 are set to a negative voltage and only the bit line BL1 is set to a high voltage, while all the other bit lines BL2 are set. BL3 voltage is 0
Keep at V.

By setting such a state, the bit line B concerned
The potential difference between the control gate 6 and the channel region 4 in all the memory cell transistors 101 to 104 arranged along L1 is opposite to that in the case of FIG. Since a state in which charges flow from the gate 5 to the channel region 4 is formed, as a result, the memory cell transistor 1
The predetermined information stored in 01 to 104 is erased, but the potential difference between the control gate 6 and the channel region 4 of the other memory cell transistors 10 is set to the potential difference required to erase the information. Information is not erased because it does not occur.

5 (B) and 5 (C) are shown in FIG. 4 (B).
4C shows the case of erasing information of the memory cell transistor corresponding to FIG. 4C, and the principle thereof is shown in FIG.
It is similar to (A). Further, FIG. 6A shows a case where a data writing operation is performed on the memory cell transistors arranged in a region having a predetermined width. For example, the memory cells arranged along the bit line BL1. When writing predetermined information to the four memory cell transistors 111 and 112 arranged along the transistors 101 and 102 and the bit line BL2, first, the word line WL1 and the word line WL2 are set to a high voltage. , The bit lines BL1 and BL2 are set to a negative voltage, and at the same time, the voltage of the other bit line BL3, the other word line WL3, and the word line WL4 is maintained at 0V.

By setting such a state, the memory cell transistors 101, 102,
The potential difference between the control gate 6 and the channel region 4 in 111 and 112 is set to the potential difference required to write information in the floating gate 5, and as a result, predetermined information is stored, but other memory cell transistors Information is not stored because the potential difference between the control gate 6 and the channel region 4 of 10 is not set to the potential difference required for writing information.

Therefore, information is written in the memory cell transistor in a predetermined area. On the other hand, FIG. 6B shows a case where information erasing operation is performed on the memory cell transistors arranged in a region having a predetermined width. For example, the memory arranged along the bit line BL1. Cell transistors 101, 1
02 and the bit line BL2, when erasing the predetermined information stored in the four memory cell transistors 111 and 112, the word line WL1 and the word line WL2 are first set to negative. And the bit lines BL1 and BL2 are set to a positive high voltage, and at the same time, the voltages of the other bit lines BL3, other word lines WL3, and word lines WL4 are maintained at 0V.

By setting such a state, the memory cell transistors 101, 102,
The potential difference between the control gate 6 and the channel region 4 in 111 and 112 forms a state in which charges flow from the floating gate 5 to the channel region 4, and as a result, is stored in the memory cell transistor. Although the predetermined information that has been erased is erased, the control gate 6 of the other memory cell transistor 10 is erased.
Since the potential difference between the channel region 4 and the channel region 4 is not set to the potential difference required for erasing information, information is not erased.

[0034]

According to the semiconductor memory device of the present invention, it is possible to selectively write and erase information with respect to the memory cell transistor in a specific region.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a specific example of a semiconductor memory device according to the present invention.

FIG. 2 is a plan view showing a configuration of a specific example of a semiconductor memory device according to the present invention.

FIG. 3 is a diagram illustrating a circuit configuration of a specific example of a semiconductor memory device according to the present invention.

FIG. 4 is a diagram illustrating an operation for writing information in the semiconductor memory device according to the present invention.

FIG. 5 is a diagram illustrating an operation when erasing information in the semiconductor memory device according to the present invention.

FIG. 6 is a diagram illustrating an operation for writing and erasing information in a memory cell transistor in a selected area in the semiconductor memory device according to the present invention.

FIG. 7 is a diagram showing a configuration of a specific example of a memory cell transistor used in a conventional semiconductor memory device.

FIG. 8 is a diagram showing a configuration of a specific example of a memory cell transistor used in a conventional semiconductor memory device.

FIG. 9 is a perspective view showing a configuration of a specific example of a memory cell transistor used in a conventional semiconductor memory device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device 2 ... Substrate 3 ... Diffusion layer 4 ... Channel region 5 ... Floating gate 6 ... Control gate 7 ... Well part 8 ... Isolation region 9 ... Tunnel oxide film 10 ... Memory cell transistor, non-volatile memory element 11 ... Insulation Separation layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 16/04

Claims (7)

[Claims] 1. A substrate having a first conductivity type, or
A well having the second conductivity type is formed over a predetermined region in the well having the first conductivity type, and a channel having the first conductivity type is formed in the well having the second conductivity type. A semiconductor memory device having a memory cell transistor formed therein. 2. The semiconductor memory device according to claim 1, wherein the wells having the second conductivity type are formed in a plurality of columns arranged in parallel with each other. 3. The semiconductor memory device according to claim 1, wherein the memory cell transistor is composed of a nonvolatile memory element. 4. The semiconductor memory device according to claim 3, wherein the nonvolatile memory element includes a control gate and a floating gate. 5. The semiconductor memory device according to claim 1, wherein the memory cell transistors are arranged in an array along the word line and bit line directions. 6. The semiconductor memory device according to claim 5, wherein the well portion having the second conductivity type is formed along the direction of the bit line. 7. The memory state of the memory cell transistor is changed by potentials individually applied to the well portion having the second conductivity type and the gate portion of the memory cell transistor. The semiconductor memory device according to claim 1.