JPH0658621B2 - Disk controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk device, and more particularly to a disk control device capable of supporting various formats.

[Conventional technology]

A conventional disk controller is a hard disk drive as described in, for example, μPD7261AD (hard disk drive controller manufactured by NIDEC CORPORATION). sector. Disk, software. sector. The data transfer was performed by selecting the format of the disk device to be connected from the two types of disk formats.

However, when a plurality of disk devices of different formats are connected, a disk controller for controlling the disk devices of various formats is further required, which increases the scale and the cost.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider controlling disk devices of various formats by one disk controller, and a plurality of disk controllers are required for the above control, resulting in a large scale. There is also a problem that the cost becomes high.

Further, as disclosed in Japanese Patent Laid-Open No. 61-156427, there is known a technique of changing the sector length by changing a data pattern for controlling a gate for reading or writing data in a disk device. ing.

However, even in such a case, reliability is improved by adding new error correction element information to a combination of a plurality of pieces of element information forming a sector, or the number of pieces of element information is reduced to 1 sector. There is a problem in that it is not possible to configure format information that is a combination of arbitrary element information according to the purpose of the user, such as shortening the length to improve the format efficiency.

An object of the present invention is to provide a disk controller that controls disk devices of several formats.

Another object of the present invention is to provide a disk control device which allows a user to configure a plurality of pieces of element information constituting the format information of the disk device in an arbitrary combination.

[Means for solving problems]

To achieve the above object, in the present invention, in a disk control device for controlling data transfer between a host device and a disk device, each of a plurality of element information constituting format information stored in the disk device is handled. Processing content information indicating the content of the processing operation to be performed, and processing length information indicating the processing length corresponding to each of the plurality of element information,
Based on information storage means for accumulating in any order from the host device according to the combination of the plurality of element information, processing content information stored in the information storage means, and processing length information corresponding to the processing content information. Then, a processing means for performing data transfer processing is provided between the disk device and the disk device by using format information by an arbitrary combination of the plurality of element information.

Further, the processing means is provided with a counting means for setting the processing length information accumulated in the information accumulating means as an initial count value, and the counting means counts according to the processing execution of the processing means. The processing end instruction signal is generated at the end of counting.

Further, the processing means is provided with a means for generating an address in the information storage means in which the processing content information and the processing length information corresponding to the processing content information are stored, and the processing from the counting means is completed. The address is updated by an instruction signal, and the processing content information and the processing length information corresponding to the processing content information are read from the information storage means based on the updated address.

[Work]

The information storage means stores the processing content information corresponding to the element information forming the format information and the processing length information from the host in an arbitrary order according to the combination of the element information forming the format information. It is also possible to support format information having a combination of element information. Further, since the processing content information stored at the address in the information storage means corresponding to the address generated by the address generation means and the processing length information corresponding thereto are output, the processing content information stored in the information storage means and the corresponding processing length information are output. The processing length information can be read sequentially.

The processing means performs data transfer processing between the host and the disk device based on the processing content information stored in the information storage means and the processing length information corresponding to the processing content information. Data can be transferred between the host and the disk device for any combination of information.

The counting means sets the processing length information accumulated in the information accumulating means as an initial count value, decrements the count value according to the execution of the processing by the processing means, and the count value is "0".
If so, a processing end signal is generated in the address generating means, so that the processing of the length corresponding to the processing length information can be performed.

The address generating means updates the address by the processing end signal generated by the counting means and outputs it to the processing means, and the processing means reads out the processing content information stored in the information storage means in correspondence with the address. So
The processing content information accumulated in the information accumulating unit can be sequentially read according to the end of the processing.

〔Example〕

 An embodiment of the present invention will be described below.

FIG. 1A shows the configuration of the main part of the disk control device. 1 is a command buffer 1 for storing information on processing contents, 2 is a command buffer 2 for storing information on processing lengths,
3 is a counter for counting the processing length, 4 is an address counter for the command buffers 1 and 2, 5 is a jump pointer register for storing a jump destination pointer, 6 is a retry pointer register for storing a retry destination pointer,
Reference numeral 7 is a control unit that controls the disk control device, and 8 is a memory unit that stores various types of information.

FIG. 1 (b) is a block diagram showing a detailed configuration of the control unit 7 in FIG. 1 (a). 701 is a control circuit constituted by a ROM storing a microprogram, and 702 is data serial / parallel. A conversion circuit for conversion, 703 is an ECC / CRC circuit, 704 is a comparison circuit for comparing the ID part, 705 is a loop counter, 706 is a verification data buffer, and 707 is data for temporarily storing data from the host. It is a buffer. Regarding the overall configuration, Hitachi hardware. disk. Users of the controller (HD63463). Please refer to the manual (issued in June 1985).

Figure 2 shows the light of the disk unit. It is a processing flow of a 1st example at the time of formatting.

FIG. 3 shows the process flow of FIG. The control information stored in the command buffers 1 and 2 when formatting is shown.

FIG. 4 shows a read .. of a disk device formatted by the processing flow shown in FIG. It is a processing flow at the time of performing data.

FIG. 5 shows the read process in the process flow shown in FIG. The control information stored in the command buffers 1 and 2 when performing data is shown.

FIG. 6 shows a write operation of the disk device formatted by the processing flow shown in FIG. It is a processing flow at the time of performing data.

FIG. 7 shows a write flow in the processing flow shown in FIG. The control information stored in the command buffers 1 and 2 when performing data is shown.

Figure 8 shows software. sector. It is an example of a data format.

First, light. The format will be described with reference to FIGS. 2 and 3. Generally, in the processing flow shown in FIG. 2, the format shown in FIG. 8 is performed. Well, second
In the figure, reference numeral 21 has an index pulse sent from the disk device. At 22, the gap between sectors and the sync field in front of the ID part are written. At 23, the address mark of the ID part and the ID information such as the cylinder address, head address, sector address, etc. are written.
At 24, a known CRC is written. CRC is a code for checking whether the ID part is correctly recorded when it is read. At 25, the gap between the ID part and the data part and the sync field in front of the data part are written. At 26, the address mark in the data section and the data are written. At 27, a known ECC is written. ECC is a code for checking whether the data is correctly recorded when the data part is read. In 28, if the loop counter 705, which sets the number of loops in this processing flow in advance, that is, the number of sectors to be formatted according to an instruction from the host, is 0, the processing is terminated, and if not 0, the processing proceeds to the next processing. At 29, the contents of the loop counter 705 are decremented, and the process proceeds to the first processing 2 of the sector format. When formatting is performed by such processing, the format shown in FIG. 8 is obtained.

In the present invention, in order to perform the format shown in FIG. 8, the host first stores the information of the processing contents and the information of the processing length as shown in FIG. 3 from the memory 8 of FIG. 1 in the command buffers 1 and 2 in advance. Keep it. The memory 8 stores commands or parameters for controlling the disk device.

Next, the host sets the number of sectors in the loop counter 705 by the start signal and activates this device. At that time, the address counter 4 outputs the address φ of the command buffers 1 and 2 as the A-1 signal. The command buffers 1 and 2 output the contents of address 0. Since the output information of the command buffer 1 is the index pulse weight at this time, the control unit 7 waits until the index pulse is input from the disk device as the C-7 signal. The output of the command buffer 2 is loaded into the counter 3. Its value is 0.

The control unit 7 keeps C-1 until the index pulse is input.
Set the signal to 0. At this time, the counter 3 does not count,
Disable the C-6 signal. When the index pulse is detected, the C-1 signal is set to 1 and the counter 3 is operated. Since the preset value of the counter 3 is 0, immediately C-6
The signal is set to 1 to notify the address counter 4 that the processing is completed. The address counter 4 increments the address and outputs the address 1 as an A-1 signal to the command buffers 1 and 2. The command buffers 1 and 2 output the contents of address 1.

At this time, the output information of the command buffer 1 is a fixed pattern write / jump pointer set. The output of the command buffer 2 is the value of the gap and sync field length, and the counter 3 loads it. At this time, the control unit 7
The -1 signal and the C-4 signal are set to 1. As a result, the counter 3 becomes valid and decrements the set value. The jump pointer register 5 loads the A-1 signal, that is, 1 (jump pointer set). Further, the control unit 7 outputs the fixed pattern of the gap and sync field to the disk device as the D-3 signal to write the gap and sync field. The counter 3 decrements the set gap and sync field length, and when it becomes 0, sets the C-6 signal to 1. At this time, the address counter 4 increments the address 1 and outputs the address 2 as the A-1 signal to the command buffers 1 and 2, so that the command buffers 1 and 2 output the control information of the address 2.

In this way, the control unit 7, particularly the control circuit 701, only has to perform the processing in accordance with the processing content information output from the command buffer, and it is not necessary to count the processing length or monitor the processing end. That is, the counter 3 decrements the loaded value in synchronization with the system clock, and notifies the address counter 4 when it becomes 0. The address counter 4 receives this instruction, increments the address, and outputs it to the command buffers 1 and 2. Further, the control circuit 701 may process the output of the command buffer 1, that is, the processing content information in byte units. Therefore, hereinafter, only the processing of the control unit 7 will be described step by step.

Next, the processing content information input as the D-2 signal by the control unit 7 is the host data write of the address 2. Here, the address mark and ID information output from the host via D-3 are output as an ID section and written to the disk device. When the processing for the byte length of the ID part is completed, the information of the CRC write processing of the command buffer 1 and the address 3 is output. The control unit 7 calculates the CRC data at the time of writing the ID part by the known built-in ECC / CRC circuit 703, so here the CRC data is output via D-3 and written to the disk device. .

Next, the control unit 7 writes the gap of the processing of the address 4 and the fixed pattern of the sync field to the disk device via D-3.

Next, the control unit 7 writes the address mark of the data portion of the processing of the address 5. Further, the data pattern of the data part of the processing of address 6 is written. Both the address mark and the data are sent from the host via D-4.

Next, the information of the processing content input by the control circuit 701 is ECC write / jump. When writing the data section, EC
Since the C / CRC circuit 703 calculates the ECC data, the ECC data is written to the disk here. (ECC
(Write) Further, the control circuit 701 sets the C-5 signal to 1.
As a result, the jump pointer register 5 sets its contents to A
-2 signal, and the address counter 4 loads the A-2 signal and outputs it as the A-1 signal. The content of the jump pointer register 5 is the address 2 as described above.
It has been updated by the Jimp pointer set. That is, the content is 1, and this jump processing causes a jump to address 1. Therefore, the control circuit 701 further formats one sector according to the processing contents from the command buffer 1.

At this time, the host decrements the contents of the loop counter 705 in which the number of loops of the processing flow has been set in advance. Therefore, when the content of the loop counter 705 becomes 0, the control circuit 701 sets the C-5 signal to 0. At this time, the end processing of the next address 8 is performed and the formatting of the disk device is completed.

In the above description, the description of the clock that decrements the set value of the counter 3 is omitted, but the system clock used in this device, that is,
It operates with the read clock during read / verify, and operates with the write clock during write. That is, when reading data from the disk device in this device, C-7
The read / verify operation is performed in synchronization with the read clock input signal of the signals. When writing data to the disk device, the write operation is performed in synchronization with the write clock input signal of the C-7 signal. These clocks are used as clocks for the counter 3 during each operation. When data is transferred from the host during read / write, the converter 702 and the host cannot be synchronized, so the data buffer 707 is used. This buffer is F
It goes without saying that an IFO circuit may be used.

Next, in the lead. Data No. 4
This will be described with reference to FIGS. Generally, the disk device of the format shown in FIG. 8 is read by the processing flow shown in FIG. The read processing flow will be described in detail below. At 41, after detecting the sync field, it waits until the address mark is detected. At 42, the ID information in the ID section is verified. At 43, CRC check of the ID part is performed. Four
In 4, if there is a mismatch in the processing of 42 or if there is a CRC error in the processing of 43, jump to 41. At 45, after detecting the sync field, the wait is performed until the address mark of the data section is detected. At 46, the data section is read and output to the host. At 47, ECC check of the read data section is performed. At 48, if an ECC error occurs, the process ends. If not, the next process starts. At 49, if the loop counter 705 is 0, the process is terminated. If not, the next process is performed. At 50, the contents of the loop counter 7005 are decremented and the process 4 is entered.

According to the present invention, even at the time of reading, the host first sends the information of the processing contents and the agent information of the processing length as shown in FIG.
It is stored in the command buffers 1 and 2 in the figure in advance.

Next, the host initializes the loop counter 705 with the start signal and activates this device. At this time, the address counter 4 outputs the address φ to A-1, and the command buffers 1 and 2 detect the address mark / retry. Outputs the jump pointer set and address mark byte length respectively. Therefore, the control circuit 701 waits until the sync field is detected and further the address mark is detected. Also, the C-1 signal is set to 0 until the address mark is detected, the operation of the counter 3 and the C-
6 Disable the signal. Therefore, the processing of address 0 is continued until the address mark is detected. In addition, the control circuit 70
1 sets the C-2 and C-4 signals to 1 and stores the address 0 being processed in the jump pointer register 5 and the retry pointer register 6.

When the address mark is detected by the byte length of the address mark, the process for address 1 is started. The information of this processing content is
Buffer verification / retry. The verification buffer 706 prepared in the control unit 7 stores the ID information to be verified by the host in advance, and the comparator 704
To verify the data read from the disk device. If the verification result does not match with the C-73 signal, the control circuit 701 sets the C-3 signal to 1. As a result, the retry pointer register 6 changes its contents to A-2.
The signal is output as a signal, and the address counter 4 loads this content and outputs it as an A-1 signal. Since the content of the retry pointer register 6 is 0, the process for address 0 is performed again (retry). The C-75 signal sent from the control circuit 701 to the verify buffer 706 increments the contents of the verify buffer 706 and / or the buffer 706.
Is used to set the timing of sending the contents of the to the comparator 704. Now, the ID part is verified by the byte length, and if all match, the process of address 2 is started. The information of this processing content is CRC check / retry. At this time,
The control unit 7 uses the ECC / CRC circuit 703 to check the CRC of the ID unit. If CRC error occurs, set C-3 signal to 1,
The contents of the retry pointer register 6 are changed to the address counter 4
To the address 0 processing again (retry).

If CRC is checked for the byte length and it is normal, address 3
Move to processing. The information of this processing content is the detection of the address mark. The control unit 7 detects the sync field,
Further, the C-1 signal is set to 0 and waits until the address mark is detected.

When the byte length of the address mark is detected, the process for address 4 is started. The information of this processing content is data read. Therefore, the byte length data of the data portion is read from the disk device and output to the host.

Next, the ECC check processing of the address 5 is performed. ECC / CRC
The circuit 703 checks the ECC for the byte length, and if abnormal, terminates, and if normal, moves to processing of the next address 6.

The information on the processing content of address 6 is buffer change / jump. In multi-sector processing of reading two or more sectors, it is necessary to verify and read the ID section of the first sector and then change the data of the ID section to be verified for reading the next sector. Therefore, the control circuit 70
1 changes the data of the buffer 706 storing the ID information to be verified described above by the C-75 signal (buffer change). Also, the contents of the loop counter 705 (C
If the (-74 signal) is not 0, the C-5 signal is set to 1 and the content of the jump pointer register 5 is output to the address counter 4 and further output to the command buffer 1 to perform the processing from the address 0 again. At this time, the contents of the loop counter 705 are decremented (jump). If the content of the loop counter 705 is 0, the next process is performed. Then, at address 7, the read process of the disk device is completed.

Next, the light. About the data No. 6
This will be described with reference to FIGS. Generally, in the process flow shown in FIG. 6, a write operation of the disk device of the format shown in FIG. Do the data. The write processing flow will be described in detail below.

At 61, after detecting the sync field, the wait is performed until the address mark is detected. At 62, the ID information in the ID section is verified. At 63, CRC check of the ID part is performed. In 64, if there is a mismatch in the process of 62 or if there is a CRC error in the process of 63, jump to 1. At 65, the sync field is written. At 66, the address mark as the data part and the data sent from the host are written to the disk. At 67, the ECC data in the data section is written. At 68, if the loop counter = 0, it is not likely to end, and the process proceeds to the next step. At 69, the contents of the loop counter are decremented, and the process 61 is entered.

According to the present invention, the host first obtains the processing content information and the processing length value as shown in FIG. 7 from the command buffer 1 of FIG.
And 2 are stored in advance.

Next, the host activates the device by the start signal.
The processing contents of addresses 0 to 2 of the command buffer are the same as those at the time of reading described above, and therefore will be omitted.

After the CRC check processing of address 2, fixed pattern write processing of address 3 is performed. Here, the sync field is written.

The information of the processing content of the address 4 is the host data write. That is, the address mark is written as the data portion, and further the data sent from the host as the D-4 signal is written.

When the data of byte length is written, the ECC data of the processing of address 5 is written.

Next, the buffer change / jump processing of address 6 is performed.
When performing the multi-sector processing as described in the read processing, it is necessary to change the verification data of the ID section, so the ID data of the buffer 706 incorporated in the control section 7 is changed via C-75. (Change buffer). If the content of the loop counter 705 is not 0, set the C-5 signal to 1
Then, the loop counter 705 is decremented and the process for the address 0 is started. (Jump) If the content of the loop counter is 0, the next process is executed. And address 7
Then, the write processing of the disk device is completed.

As a second embodiment of the present invention, a write format process, a write process, and a read process of a hard sector special format will be described below.

First, the write format process will be described with reference to FIGS. 9 and 10.

FIG. 9 is a write format processing flow. In 71, index pulse wait is performed. At 72, write the gap and sync field. At 73, the address mark of the data section is written. At 74, the data part is written. At 75, a known ECC is written. At 76, the sector pulse is waited. At 77, write the gap and sync field. At 78, the address mark of the data section is written. At 79, the data section is written. EC in 80
Write C. At 81, if the loop counter is not 0, the following processing is executed. If 0, the process ends. At 82, the loop counter is decremented and jumps to 76.

The above processing shows the case where the number of sectors of one track is two or more, and if the initial value of the loop counter 705 is 2, it is a 4-sector format.

According to the present invention, during the write format, the information on the processing content and the information on the processing length as shown in FIG. 10 are stored in advance in the command buffers 1 and 2 of FIG.

Next, the host activates this device by the START signal.
In this process, the basic operation of the present invention is the same as the write format process described with reference to FIG. Therefore, an outline of this processing will be described here.

In FIG. 10, at address 0, the index pulse is first waited. When the index pulse is detected, the fixed pattern of the gap and sync field is written at the address 1 by the designated byte length. Next, at address 2, the address mark and ID information sent from the host are written as address mark / ID. At address 3, the data fixed pattern of the data part is divided by the byte length of the data part. At address 4, the ECC of the data part is written.
Address 5 waits for the sector pulse,
Is stored in the jump pointer register. After this, 2
Format the sectors after the first sector. address
At 6, 7 and 8, the gap, sync field, address mark / ID, and data section are written as in the case of the contents of addresses 1, 2 and 3. At address 9, write the ECC of the data part,
If the content of the loop counter 705 is not 0, the loop counter 705 is decremented and the process of the address 5 is started. 0
If so, the process moves to address A and the process ends.

Next, the read processing will be described with reference to FIGS. 11 and 12.

FIG. 11 is a read processing flow. First, at 111, the index pulse or sector pulse is waited. 11
In 2, the address mark is detected after detecting the sync field, and the ID information is verified as in the previous embodiment. 113
Then, if they do not match, the process jumps to 111, and if they match, the next process is performed. At 114, the data section is read. At 115, an ECC check is performed, and at 116, if an ECC error occurs, the process ends, and if normal, the next process starts. In 117, if the content of the loop counter 705 is 0, the process is ended, and if it is not 0, the next process is performed. At 118, decrement with the loop counter 705
Jump to 111.

In the present invention, at the time of reading, the information of the processing content and the information of the processing length as shown in FIG. 12 are stored in the command buffers 1 and 2 of FIG.

This device is started by sending a START signal from the host, and first, at address 0, the index pulse or sector pulse is waited. Also, the lit write pointer 6 and the jump pointer 5 are set. In the address 1, after detecting the sync field, the address mark is detected, and the ID information is further verified with the contents of the verification buffer. At this time,
If address mark detection or verify disagreement occurs, jump to address 0. At address 2, the data part is read and transferred to the host. At address 3, the ECC is checked, and if an error occurs, the process ends. At address 4, ID
Change the verify data of information, loop counter 705
If is not 0, decrement and jump to address 0. If it is 0, the process moves to address 5 and the process is terminated.

Next, the write processing will be described with reference to FIGS. 13 and 14.

When writing the special format shown in FIG. 15, the ID information of the sector physically immediately preceding the sector to be written is verified, and if they match, the desired sector is written. Therefore, the write processing flow is shown in FIG.

The write process will be described with reference to FIG. At 131, the index pulse or sector pulse is waited. In 132, after detecting the sync field, the address mark is detected and the ID information is verified. In 133, if there is no match, jump to 131. At 134, the index pulse or the sector pulse is waited. In 135, write gap and sync field. At 136, the address mark and ID information are written. At 137, the data part is written. At 138, write the ECC. At 139, if the loop counter 705 is 0, the process is terminated. If it is not 0, the next process is performed. At 140, the loop counter 705 is decremented and jumped to 131.

In the present invention, at the time of writing, the information on the processing content and the information on the processing length as shown in FIG. 14 are stored in the command buffers 1 and 2 of FIG.

When the host sends a START signal, the device starts up and waits for an index pulse or sector pulse at address 0. Also, the retry pointer 6 and the jump pointer 5 are set. At address 1, the address mark is detected after the sync field is detected, and the ID information is verified with the contents of the verification buffer 706. If no address mark is detected or ID information does not match, address 0
Jump to. Index pulse at address 2 /
Wait the sector pulse. At address 3, the gap and sync fields are written. At address 4, the address mark and ID information sent from the host are written. At address 5, the data sent from the host is written as the data section. At address 6, ECC is written, and if the loop counter 705 is 0, the process moves to address 7 and the processing ends. If it is not 0, the verification data of the ID information is changed, the loop counter 705 is decremented, and the address is moved to 0.

The embodiment of the format, read and write processing of the disk device having the format shown in FIGS. 8 and 15 has been described above in detail, but various formats can be handled by changing the information stored in the command buffer. There is nothing to say.

〔The invention's effect〕

As described in detail above, according to the present invention, the processing content information and the processing length corresponding to each of the plurality of pieces of element information are set for any combination of the plurality of pieces of element information that form the format information of the disk device. Data transfer can be performed between the host and the disk device based on the information. Therefore, regardless of the soft sector / hard sector, it is possible to support various formats in which a plurality of pieces of element information forming the format information are freely formed. Further, since one disk control device can support disk devices that employ the above-mentioned various formats, the device can be made compact and economical.

Further, according to the present invention, since a plurality of different formats can be mixed on the same disk device, it is not necessary to prepare as many disk devices as there are types of formats, and the device can be miniaturized and economically excellent. ing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a disk control device of an embodiment of the present invention, FIG. 2 is a processing flow for formatting, FIG. 3 is a diagram showing control information at the time of formatting, and FIG. 4 is processing for reading. Flow, FIG. 5 is a diagram showing control information at the time of reading, FIG. 6 is a processing flow for writing, FIG. 7 is a diagram showing control information at the time of writing, FIG. 8 is a diagram showing a format, FIG. 9 Is a processing flow for performing write formatting of a special format, FIG. 10 is a diagram showing control information at the time of write formatting, FIG. 11 is a processing flow for performing reading at the same time, and FIG. 12 is a diagram showing control information at the time of reading , FIG. 13 is a processing flow for similarly writing, FIG. 14 is a diagram showing control information at the time of writing, and FIG. 15 is a diagram showing a special format. 1 and 2 ... Command buffer, 3 ... Counter, 4
...... Address counter, 5 ...... Jump pointer register, 6 ...... Retry pointer register, 7 ...... Control section.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuji Kawamura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Masayuki Tsumaka Hayano, Mobara-shi, Chiba 3300 Address Mobara Factory, Hitachi, Ltd. (72) Inventor Hiroshi Kurihara 3300 Hayano, Mobara City, Chiba, Ltd., Mobara Factory, Hitachi, Ltd. (56) References JP 61-156427 (JP, A) JP 61 -115124 (JP, A) JP-A-58-219659 (JP, A)

Claims (5)

[Claims] 1. A disk control device for controlling data transfer between a host device and a disk device, showing contents of processing operations corresponding to each of a plurality of element information constituting format information stored in the disk device. Information storage means for storing processing content information and processing length information indicating processing lengths corresponding to each of the plurality of element information from the host device in an arbitrary order according to a combination of the plurality of element information. Based on the processing content information accumulated in the information accumulating means and the processing length information corresponding to the processing content information, data is formed between the disk device and the format information by an arbitrary combination of the plurality of element information. A disk control device having a processing means for performing a transfer process. 2. The processing means has a counting means for setting the processing length information accumulated in the information accumulating means as an initial count value, and the counting means counts according to the processing execution of the processing means. The disk control device according to claim 1, wherein a processing end instruction signal is generated at the end of counting the initial count value. 3. The processing means stores an address in the information storage means in which the processing content information and the processing length information corresponding to the processing content information are stored, and stores the generated address. Means for updating the address according to the processing end instruction signal from the counting means, and based on the updated address, the processing content information from the information storage means and the processing content information corresponding to the processing content information. The disk control device according to claim 2, wherein the processing length information is read out. 4. The plurality of element information are address marks,
The disk control device according to claim 1, which has element information of ID information, CRC, data, and ECC. 5. The information storage means has a first command buffer for storing the processing content information and a second command buffer for storing the processing length information. Disk control device